1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h 4 * processor hardware monitoring 5 * 6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net> 8 * 9 * Implementation notes: 10 * - CCD register address information as well as the calculation to 11 * convert raw register values is from https://github.com/ocerman/zenpower. 12 * The information is not confirmed from chip datasheets, but experiments 13 * suggest that it provides reasonable temperature values. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/err.h> 18 #include <linux/hwmon.h> 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pci_ids.h> 23 24 #include <asm/amd/node.h> 25 #include <asm/cpuid/api.h> 26 #include <asm/processor.h> 27 28 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 29 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 30 MODULE_LICENSE("GPL"); 31 32 static bool force; 33 module_param(force, bool, 0444); 34 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 35 36 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 37 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 38 #endif 39 40 /* CPUID function 0x80000001, ebx */ 41 #define CPUID_PKGTYPE_MASK GENMASK(31, 28) 42 #define CPUID_PKGTYPE_F 0x00000000 43 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 44 45 /* DRAM controller (PCI function 2) */ 46 #define REG_DCT0_CONFIG_HIGH 0x094 47 #define DDR3_MODE BIT(8) 48 49 /* miscellaneous (PCI function 3) */ 50 #define REG_HARDWARE_THERMAL_CONTROL 0x64 51 #define HTC_ENABLE BIT(0) 52 53 #define REG_REPORTED_TEMPERATURE 0xa4 54 55 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 56 #define NB_CAP_HTC BIT(10) 57 58 /* 59 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 60 * and REG_REPORTED_TEMPERATURE have been moved to 61 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 62 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 63 */ 64 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 65 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 66 67 /* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */ 68 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 69 70 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ 71 (offset) + ((x) * 4)) 72 #define ZEN_CCD_TEMP_VALID BIT(11) 73 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) 74 75 #define ZEN_CUR_TEMP_SHIFT 21 76 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) 77 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16) 78 79 /* 80 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius. 81 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature. 82 * Do not round off to zero for negative Tctl or Tdie values if the flag is set 83 */ 84 #define AMD_I3255_STR "3255" 85 86 /* 87 * PCI Device IDs for AMD's Family 17h-based SOCs. 88 * Defining locally as IDs are not shared. 89 */ 90 #define PCI_DEVICE_ID_AMD_17H_M90H_DF_F3 0x1663 91 92 /* 93 * PCI Device IDs for AMD's Family 1Ah-based SOCs. 94 * Defining locally as IDs are not shared. 95 */ 96 #define PCI_DEVICE_ID_AMD_1AH_M50H_DF_F3 0x12cb 97 #define PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3 0x127b 98 99 struct k10temp_data { 100 struct pci_dev *pdev; 101 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 102 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 103 int temp_offset; 104 u32 temp_adjust_mask; 105 u32 show_temp; 106 bool is_zen; 107 u32 ccd_offset; 108 bool disp_negative; 109 }; 110 111 #define TCTL_BIT 0 112 #define TDIE_BIT 1 113 #define TCCD_BIT(x) ((x) + 2) 114 115 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) 116 117 struct tctl_offset { 118 u8 model; 119 char const *id; 120 int offset; 121 }; 122 123 static const struct tctl_offset tctl_offset_table[] = { 124 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 125 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 126 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 127 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 128 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ 129 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ 130 }; 131 132 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 133 { 134 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 135 } 136 137 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 138 { 139 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 140 } 141 142 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 143 unsigned int base, int offset, u32 *val) 144 { 145 pci_bus_write_config_dword(pdev->bus, devfn, 146 base, offset); 147 pci_bus_read_config_dword(pdev->bus, devfn, 148 base + 4, val); 149 } 150 151 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 152 { 153 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 154 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 155 } 156 157 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 158 { 159 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 160 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 161 } 162 163 static u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) 164 { 165 return PCI_SLOT(pdev->devfn) - AMD_NODE0_PCI_SLOT; 166 } 167 168 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) 169 { 170 if (amd_smn_read(amd_pci_dev_to_node_id(pdev), 171 ZEN_REPORTED_TEMP_CTRL_BASE, regval)) 172 *regval = 0; 173 } 174 175 static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval) 176 { 177 u16 node_id = amd_pci_dev_to_node_id(data->pdev); 178 179 return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval); 180 } 181 182 static long get_raw_temp(struct k10temp_data *data) 183 { 184 u32 regval; 185 long temp; 186 187 data->read_tempreg(data->pdev, ®val); 188 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; 189 if ((regval & data->temp_adjust_mask) || 190 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK) 191 temp -= 49000; 192 return temp; 193 } 194 195 static const char *k10temp_temp_label[] = { 196 "Tctl", 197 "Tdie", 198 "Tccd1", 199 "Tccd2", 200 "Tccd3", 201 "Tccd4", 202 "Tccd5", 203 "Tccd6", 204 "Tccd7", 205 "Tccd8", 206 "Tccd9", 207 "Tccd10", 208 "Tccd11", 209 "Tccd12", 210 }; 211 212 static int k10temp_read_labels(struct device *dev, 213 enum hwmon_sensor_types type, 214 u32 attr, int channel, const char **str) 215 { 216 switch (type) { 217 case hwmon_temp: 218 *str = k10temp_temp_label[channel]; 219 break; 220 default: 221 return -EOPNOTSUPP; 222 } 223 return 0; 224 } 225 226 static int k10temp_read_temp(struct device *dev, u32 attr, int channel, 227 long *val) 228 { 229 struct k10temp_data *data = dev_get_drvdata(dev); 230 int ret = -EOPNOTSUPP; 231 u32 regval; 232 233 switch (attr) { 234 case hwmon_temp_input: 235 switch (channel) { 236 case 0: /* Tctl */ 237 *val = get_raw_temp(data); 238 if (*val < 0 && !data->disp_negative) 239 *val = 0; 240 break; 241 case 1: /* Tdie */ 242 *val = get_raw_temp(data) - data->temp_offset; 243 if (*val < 0 && !data->disp_negative) 244 *val = 0; 245 break; 246 case 2 ... 13: /* Tccd{1-12} */ 247 ret = read_ccd_temp_reg(data, channel - 2, ®val); 248 249 if (ret) 250 return ret; 251 252 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; 253 break; 254 default: 255 return ret; 256 } 257 break; 258 case hwmon_temp_max: 259 *val = 70 * 1000; 260 break; 261 case hwmon_temp_crit: 262 data->read_htcreg(data->pdev, ®val); 263 *val = ((regval >> 16) & 0x7f) * 500 + 52000; 264 break; 265 case hwmon_temp_crit_hyst: 266 data->read_htcreg(data->pdev, ®val); 267 *val = (((regval >> 16) & 0x7f) 268 - ((regval >> 24) & 0xf)) * 500 + 52000; 269 break; 270 default: 271 return ret; 272 } 273 return 0; 274 } 275 276 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, 277 u32 attr, int channel, long *val) 278 { 279 switch (type) { 280 case hwmon_temp: 281 return k10temp_read_temp(dev, attr, channel, val); 282 default: 283 return -EOPNOTSUPP; 284 } 285 } 286 287 static umode_t k10temp_is_visible(const void *drvdata, 288 enum hwmon_sensor_types type, 289 u32 attr, int channel) 290 { 291 const struct k10temp_data *data = drvdata; 292 struct pci_dev *pdev = data->pdev; 293 u32 reg; 294 295 switch (type) { 296 case hwmon_temp: 297 switch (attr) { 298 case hwmon_temp_input: 299 if (!HAVE_TEMP(data, channel)) 300 return 0; 301 break; 302 case hwmon_temp_max: 303 if (channel || data->is_zen) 304 return 0; 305 break; 306 case hwmon_temp_crit: 307 case hwmon_temp_crit_hyst: 308 if (channel || !data->read_htcreg) 309 return 0; 310 311 pci_read_config_dword(pdev, 312 REG_NORTHBRIDGE_CAPABILITIES, 313 ®); 314 if (!(reg & NB_CAP_HTC)) 315 return 0; 316 317 data->read_htcreg(data->pdev, ®); 318 if (!(reg & HTC_ENABLE)) 319 return 0; 320 break; 321 case hwmon_temp_label: 322 /* Show temperature labels only on Zen CPUs */ 323 if (!data->is_zen || !HAVE_TEMP(data, channel)) 324 return 0; 325 break; 326 default: 327 return 0; 328 } 329 break; 330 default: 331 return 0; 332 } 333 return 0444; 334 } 335 336 static bool has_erratum_319(struct pci_dev *pdev) 337 { 338 u32 pkg_type, reg_dram_cfg; 339 340 if (boot_cpu_data.x86 != 0x10) 341 return false; 342 343 /* 344 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 345 * may be unreliable. 346 */ 347 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 348 if (pkg_type == CPUID_PKGTYPE_F) 349 return true; 350 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 351 return false; 352 353 /* DDR3 memory implies socket AM3, which is good */ 354 pci_bus_read_config_dword(pdev->bus, 355 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 356 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 357 if (reg_dram_cfg & DDR3_MODE) 358 return false; 359 360 /* 361 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 362 * memory. We blacklist all the cores which do exist in socket AM2+ 363 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 364 * and AM3 formats, but that's the best we can do. 365 */ 366 return boot_cpu_data.x86_model < 4 || 367 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 368 } 369 370 static const struct hwmon_channel_info * const k10temp_info[] = { 371 HWMON_CHANNEL_INFO(temp, 372 HWMON_T_INPUT | HWMON_T_MAX | 373 HWMON_T_CRIT | HWMON_T_CRIT_HYST | 374 HWMON_T_LABEL, 375 HWMON_T_INPUT | HWMON_T_LABEL, 376 HWMON_T_INPUT | HWMON_T_LABEL, 377 HWMON_T_INPUT | HWMON_T_LABEL, 378 HWMON_T_INPUT | HWMON_T_LABEL, 379 HWMON_T_INPUT | HWMON_T_LABEL, 380 HWMON_T_INPUT | HWMON_T_LABEL, 381 HWMON_T_INPUT | HWMON_T_LABEL, 382 HWMON_T_INPUT | HWMON_T_LABEL, 383 HWMON_T_INPUT | HWMON_T_LABEL, 384 HWMON_T_INPUT | HWMON_T_LABEL, 385 HWMON_T_INPUT | HWMON_T_LABEL, 386 HWMON_T_INPUT | HWMON_T_LABEL, 387 HWMON_T_INPUT | HWMON_T_LABEL), 388 NULL 389 }; 390 391 static const struct hwmon_ops k10temp_hwmon_ops = { 392 .is_visible = k10temp_is_visible, 393 .read = k10temp_read, 394 .read_string = k10temp_read_labels, 395 }; 396 397 static const struct hwmon_chip_info k10temp_chip_info = { 398 .ops = &k10temp_hwmon_ops, 399 .info = k10temp_info, 400 }; 401 402 static void k10temp_get_ccd_support(struct k10temp_data *data, int limit) 403 { 404 u32 regval; 405 int i; 406 407 for (i = 0; i < limit; i++) { 408 /* 409 * Ignore inaccessible CCDs. 410 * 411 * Some systems will return a register value of 0, and the TEMP_VALID 412 * bit check below will naturally fail. 413 * 414 * Other systems will return a PCI_ERROR_RESPONSE (0xFFFFFFFF) for 415 * the register value. And this will incorrectly pass the TEMP_VALID 416 * bit check. 417 */ 418 if (read_ccd_temp_reg(data, i, ®val)) 419 continue; 420 421 if (regval & ZEN_CCD_TEMP_VALID) 422 data->show_temp |= BIT(TCCD_BIT(i)); 423 } 424 } 425 426 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 427 { 428 int unreliable = has_erratum_319(pdev); 429 struct device *dev = &pdev->dev; 430 struct k10temp_data *data; 431 struct device *hwmon_dev; 432 int i; 433 434 if (unreliable) { 435 if (!force) { 436 dev_err(dev, 437 "unreliable CPU thermal sensor; monitoring disabled\n"); 438 return -ENODEV; 439 } 440 dev_warn(dev, 441 "unreliable CPU thermal sensor; check erratum 319\n"); 442 } 443 444 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 445 if (!data) 446 return -ENOMEM; 447 448 data->pdev = pdev; 449 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ 450 451 if (boot_cpu_data.x86 == 0x17 && 452 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) { 453 data->disp_negative = true; 454 } 455 456 data->is_zen = cpu_feature_enabled(X86_FEATURE_ZEN); 457 if (data->is_zen) { 458 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 459 data->read_tempreg = read_tempreg_nb_zen; 460 } else if (boot_cpu_data.x86 == 0x15 && 461 ((boot_cpu_data.x86_model & 0xf0) == 0x60 || 462 (boot_cpu_data.x86_model & 0xf0) == 0x70)) { 463 data->read_htcreg = read_htcreg_nb_f15; 464 data->read_tempreg = read_tempreg_nb_f15; 465 } else { 466 data->read_htcreg = read_htcreg_pci; 467 data->read_tempreg = read_tempreg_pci; 468 } 469 470 if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { 471 switch (boot_cpu_data.x86_model) { 472 case 0x1: /* Zen */ 473 case 0x8: /* Zen+ */ 474 case 0x11: /* Zen APU */ 475 case 0x18: /* Zen+ APU */ 476 data->ccd_offset = 0x154; 477 k10temp_get_ccd_support(data, 4); 478 break; 479 case 0x31: /* Zen2 Threadripper */ 480 case 0x47: /* Cyan Skillfish */ 481 case 0x60: /* Renoir */ 482 case 0x68: /* Lucienne */ 483 case 0x71: /* Zen2 */ 484 data->ccd_offset = 0x154; 485 k10temp_get_ccd_support(data, 8); 486 break; 487 case 0xa0 ... 0xaf: 488 data->ccd_offset = 0x300; 489 k10temp_get_ccd_support(data, 8); 490 break; 491 } 492 } else if (boot_cpu_data.x86 == 0x19) { 493 switch (boot_cpu_data.x86_model) { 494 case 0x0 ... 0x1: /* Zen3 SP3/TR */ 495 case 0x8: /* Zen3 TR Chagall */ 496 case 0x21: /* Zen3 Ryzen Desktop */ 497 case 0x50 ... 0x5f: /* Green Sardine */ 498 data->ccd_offset = 0x154; 499 k10temp_get_ccd_support(data, 8); 500 break; 501 case 0x40 ... 0x4f: /* Yellow Carp */ 502 data->ccd_offset = 0x300; 503 k10temp_get_ccd_support(data, 8); 504 break; 505 case 0x60 ... 0x6f: 506 case 0x70 ... 0x7f: 507 data->ccd_offset = 0x308; 508 k10temp_get_ccd_support(data, 8); 509 break; 510 case 0x10 ... 0x1f: 511 case 0xa0 ... 0xaf: 512 data->ccd_offset = 0x300; 513 k10temp_get_ccd_support(data, 12); 514 break; 515 } 516 } else if (boot_cpu_data.x86 == 0x1a) { 517 switch (boot_cpu_data.x86_model) { 518 case 0x40 ... 0x4f: /* Zen5 Ryzen Desktop */ 519 data->ccd_offset = 0x308; 520 k10temp_get_ccd_support(data, 8); 521 break; 522 } 523 } 524 525 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 526 const struct tctl_offset *entry = &tctl_offset_table[i]; 527 528 if (boot_cpu_data.x86 == entry->model && 529 strstr(boot_cpu_data.x86_model_id, entry->id)) { 530 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ 531 data->temp_offset = entry->offset; 532 break; 533 } 534 } 535 536 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, 537 &k10temp_chip_info, 538 NULL); 539 return PTR_ERR_OR_ZERO(hwmon_dev); 540 } 541 542 static const struct pci_device_id k10temp_id_table[] = { 543 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 544 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 545 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 546 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 547 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 548 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 549 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 550 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, 551 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 552 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 553 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 554 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 555 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, 556 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M40H_DF_F3) }, 557 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, 558 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, 559 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M90H_DF_F3) }, 560 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) }, 561 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, 562 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) }, 563 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, 564 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, 565 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) }, 566 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) }, 567 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, 568 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, 569 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, 570 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M50H_DF_F3) }, 571 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) }, 572 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) }, 573 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3) }, 574 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 575 {} 576 }; 577 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 578 579 static struct pci_driver k10temp_driver = { 580 .name = "k10temp", 581 .id_table = k10temp_id_table, 582 .probe = k10temp_probe, 583 }; 584 585 module_pci_driver(k10temp_driver); 586