1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h 4 * processor hardware monitoring 5 * 6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net> 8 * 9 * Implementation notes: 10 * - CCD register address information as well as the calculation to 11 * convert raw register values is from https://github.com/ocerman/zenpower. 12 * The information is not confirmed from chip datasheets, but experiments 13 * suggest that it provides reasonable temperature values. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/err.h> 18 #include <linux/hwmon.h> 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pci_ids.h> 23 #include <asm/amd_nb.h> 24 #include <asm/processor.h> 25 26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 28 MODULE_LICENSE("GPL"); 29 30 static bool force; 31 module_param(force, bool, 0444); 32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 33 34 /* Provide lock for writing to NB_SMU_IND_ADDR */ 35 static DEFINE_MUTEX(nb_smu_ind_mutex); 36 37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 39 #endif 40 41 /* CPUID function 0x80000001, ebx */ 42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28) 43 #define CPUID_PKGTYPE_F 0x00000000 44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 45 46 /* DRAM controller (PCI function 2) */ 47 #define REG_DCT0_CONFIG_HIGH 0x094 48 #define DDR3_MODE BIT(8) 49 50 /* miscellaneous (PCI function 3) */ 51 #define REG_HARDWARE_THERMAL_CONTROL 0x64 52 #define HTC_ENABLE BIT(0) 53 54 #define REG_REPORTED_TEMPERATURE 0xa4 55 56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 57 #define NB_CAP_HTC BIT(10) 58 59 /* 60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 61 * and REG_REPORTED_TEMPERATURE have been moved to 62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 64 */ 65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 67 68 /* Common for Zen CPU families (Family 17h and 18h and 19h) */ 69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 70 71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ 72 (offset) + ((x) * 4)) 73 #define ZEN_CCD_TEMP_VALID BIT(11) 74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) 75 76 #define ZEN_CUR_TEMP_SHIFT 21 77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) 78 79 #define ZEN_SVI_BASE 0x0005A000 80 81 /* F17h thermal registers through SMN */ 82 #define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc) 83 #define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) 84 #define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) 85 #define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) 86 87 #define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ 88 #define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */ 89 #define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */ 90 #define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ 91 92 /* F19h thermal registers through SMN */ 93 #define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) 94 #define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) 95 96 #define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ 97 #define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ 98 99 struct k10temp_data { 100 struct pci_dev *pdev; 101 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 102 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 103 int temp_offset; 104 u32 temp_adjust_mask; 105 u32 show_temp; 106 bool is_zen; 107 u32 ccd_offset; 108 }; 109 110 #define TCTL_BIT 0 111 #define TDIE_BIT 1 112 #define TCCD_BIT(x) ((x) + 2) 113 114 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) 115 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT) 116 117 struct tctl_offset { 118 u8 model; 119 char const *id; 120 int offset; 121 }; 122 123 static const struct tctl_offset tctl_offset_table[] = { 124 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 125 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 126 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 127 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 128 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ 129 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ 130 }; 131 132 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 133 { 134 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 135 } 136 137 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 138 { 139 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 140 } 141 142 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 143 unsigned int base, int offset, u32 *val) 144 { 145 mutex_lock(&nb_smu_ind_mutex); 146 pci_bus_write_config_dword(pdev->bus, devfn, 147 base, offset); 148 pci_bus_read_config_dword(pdev->bus, devfn, 149 base + 4, val); 150 mutex_unlock(&nb_smu_ind_mutex); 151 } 152 153 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 154 { 155 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 156 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 157 } 158 159 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 160 { 161 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 162 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 163 } 164 165 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) 166 { 167 amd_smn_read(amd_pci_dev_to_node_id(pdev), 168 ZEN_REPORTED_TEMP_CTRL_BASE, regval); 169 } 170 171 static long get_raw_temp(struct k10temp_data *data) 172 { 173 u32 regval; 174 long temp; 175 176 data->read_tempreg(data->pdev, ®val); 177 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; 178 if (regval & data->temp_adjust_mask) 179 temp -= 49000; 180 return temp; 181 } 182 183 static const char *k10temp_temp_label[] = { 184 "Tctl", 185 "Tdie", 186 "Tccd1", 187 "Tccd2", 188 "Tccd3", 189 "Tccd4", 190 "Tccd5", 191 "Tccd6", 192 "Tccd7", 193 "Tccd8", 194 }; 195 196 static int k10temp_read_labels(struct device *dev, 197 enum hwmon_sensor_types type, 198 u32 attr, int channel, const char **str) 199 { 200 switch (type) { 201 case hwmon_temp: 202 *str = k10temp_temp_label[channel]; 203 break; 204 default: 205 return -EOPNOTSUPP; 206 } 207 return 0; 208 } 209 210 static int k10temp_read_temp(struct device *dev, u32 attr, int channel, 211 long *val) 212 { 213 struct k10temp_data *data = dev_get_drvdata(dev); 214 u32 regval; 215 216 switch (attr) { 217 case hwmon_temp_input: 218 switch (channel) { 219 case 0: /* Tctl */ 220 *val = get_raw_temp(data); 221 if (*val < 0) 222 *val = 0; 223 break; 224 case 1: /* Tdie */ 225 *val = get_raw_temp(data) - data->temp_offset; 226 if (*val < 0) 227 *val = 0; 228 break; 229 case 2 ... 9: /* Tccd{1-8} */ 230 amd_smn_read(amd_pci_dev_to_node_id(data->pdev), 231 ZEN_CCD_TEMP(data->ccd_offset, channel - 2), 232 ®val); 233 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; 234 break; 235 default: 236 return -EOPNOTSUPP; 237 } 238 break; 239 case hwmon_temp_max: 240 *val = 70 * 1000; 241 break; 242 case hwmon_temp_crit: 243 data->read_htcreg(data->pdev, ®val); 244 *val = ((regval >> 16) & 0x7f) * 500 + 52000; 245 break; 246 case hwmon_temp_crit_hyst: 247 data->read_htcreg(data->pdev, ®val); 248 *val = (((regval >> 16) & 0x7f) 249 - ((regval >> 24) & 0xf)) * 500 + 52000; 250 break; 251 default: 252 return -EOPNOTSUPP; 253 } 254 return 0; 255 } 256 257 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, 258 u32 attr, int channel, long *val) 259 { 260 switch (type) { 261 case hwmon_temp: 262 return k10temp_read_temp(dev, attr, channel, val); 263 default: 264 return -EOPNOTSUPP; 265 } 266 } 267 268 static umode_t k10temp_is_visible(const void *_data, 269 enum hwmon_sensor_types type, 270 u32 attr, int channel) 271 { 272 const struct k10temp_data *data = _data; 273 struct pci_dev *pdev = data->pdev; 274 u32 reg; 275 276 switch (type) { 277 case hwmon_temp: 278 switch (attr) { 279 case hwmon_temp_input: 280 if (!HAVE_TEMP(data, channel)) 281 return 0; 282 break; 283 case hwmon_temp_max: 284 if (channel || data->is_zen) 285 return 0; 286 break; 287 case hwmon_temp_crit: 288 case hwmon_temp_crit_hyst: 289 if (channel || !data->read_htcreg) 290 return 0; 291 292 pci_read_config_dword(pdev, 293 REG_NORTHBRIDGE_CAPABILITIES, 294 ®); 295 if (!(reg & NB_CAP_HTC)) 296 return 0; 297 298 data->read_htcreg(data->pdev, ®); 299 if (!(reg & HTC_ENABLE)) 300 return 0; 301 break; 302 case hwmon_temp_label: 303 /* Show temperature labels only on Zen CPUs */ 304 if (!data->is_zen || !HAVE_TEMP(data, channel)) 305 return 0; 306 break; 307 default: 308 return 0; 309 } 310 break; 311 default: 312 return 0; 313 } 314 return 0444; 315 } 316 317 static bool has_erratum_319(struct pci_dev *pdev) 318 { 319 u32 pkg_type, reg_dram_cfg; 320 321 if (boot_cpu_data.x86 != 0x10) 322 return false; 323 324 /* 325 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 326 * may be unreliable. 327 */ 328 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 329 if (pkg_type == CPUID_PKGTYPE_F) 330 return true; 331 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 332 return false; 333 334 /* DDR3 memory implies socket AM3, which is good */ 335 pci_bus_read_config_dword(pdev->bus, 336 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 337 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 338 if (reg_dram_cfg & DDR3_MODE) 339 return false; 340 341 /* 342 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 343 * memory. We blacklist all the cores which do exist in socket AM2+ 344 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 345 * and AM3 formats, but that's the best we can do. 346 */ 347 return boot_cpu_data.x86_model < 4 || 348 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 349 } 350 351 static const struct hwmon_channel_info *k10temp_info[] = { 352 HWMON_CHANNEL_INFO(temp, 353 HWMON_T_INPUT | HWMON_T_MAX | 354 HWMON_T_CRIT | HWMON_T_CRIT_HYST | 355 HWMON_T_LABEL, 356 HWMON_T_INPUT | HWMON_T_LABEL, 357 HWMON_T_INPUT | HWMON_T_LABEL, 358 HWMON_T_INPUT | HWMON_T_LABEL, 359 HWMON_T_INPUT | HWMON_T_LABEL, 360 HWMON_T_INPUT | HWMON_T_LABEL, 361 HWMON_T_INPUT | HWMON_T_LABEL, 362 HWMON_T_INPUT | HWMON_T_LABEL, 363 HWMON_T_INPUT | HWMON_T_LABEL, 364 HWMON_T_INPUT | HWMON_T_LABEL), 365 HWMON_CHANNEL_INFO(in, 366 HWMON_I_INPUT | HWMON_I_LABEL, 367 HWMON_I_INPUT | HWMON_I_LABEL), 368 HWMON_CHANNEL_INFO(curr, 369 HWMON_C_INPUT | HWMON_C_LABEL, 370 HWMON_C_INPUT | HWMON_C_LABEL), 371 NULL 372 }; 373 374 static const struct hwmon_ops k10temp_hwmon_ops = { 375 .is_visible = k10temp_is_visible, 376 .read = k10temp_read, 377 .read_string = k10temp_read_labels, 378 }; 379 380 static const struct hwmon_chip_info k10temp_chip_info = { 381 .ops = &k10temp_hwmon_ops, 382 .info = k10temp_info, 383 }; 384 385 static void k10temp_get_ccd_support(struct pci_dev *pdev, 386 struct k10temp_data *data, int limit) 387 { 388 u32 regval; 389 int i; 390 391 for (i = 0; i < limit; i++) { 392 amd_smn_read(amd_pci_dev_to_node_id(pdev), 393 ZEN_CCD_TEMP(data->ccd_offset, i), ®val); 394 if (regval & ZEN_CCD_TEMP_VALID) 395 data->show_temp |= BIT(TCCD_BIT(i)); 396 } 397 } 398 399 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 400 { 401 int unreliable = has_erratum_319(pdev); 402 struct device *dev = &pdev->dev; 403 struct k10temp_data *data; 404 struct device *hwmon_dev; 405 int i; 406 407 if (unreliable) { 408 if (!force) { 409 dev_err(dev, 410 "unreliable CPU thermal sensor; monitoring disabled\n"); 411 return -ENODEV; 412 } 413 dev_warn(dev, 414 "unreliable CPU thermal sensor; check erratum 319\n"); 415 } 416 417 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 418 if (!data) 419 return -ENOMEM; 420 421 data->pdev = pdev; 422 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ 423 424 if (boot_cpu_data.x86 == 0x15 && 425 ((boot_cpu_data.x86_model & 0xf0) == 0x60 || 426 (boot_cpu_data.x86_model & 0xf0) == 0x70)) { 427 data->read_htcreg = read_htcreg_nb_f15; 428 data->read_tempreg = read_tempreg_nb_f15; 429 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { 430 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 431 data->read_tempreg = read_tempreg_nb_zen; 432 data->is_zen = true; 433 434 switch (boot_cpu_data.x86_model) { 435 case 0x1: /* Zen */ 436 case 0x8: /* Zen+ */ 437 case 0x11: /* Zen APU */ 438 case 0x18: /* Zen+ APU */ 439 data->ccd_offset = 0x154; 440 k10temp_get_ccd_support(pdev, data, 4); 441 break; 442 case 0x31: /* Zen2 Threadripper */ 443 case 0x60: /* Renoir */ 444 case 0x68: /* Lucienne */ 445 case 0x71: /* Zen2 */ 446 data->ccd_offset = 0x154; 447 k10temp_get_ccd_support(pdev, data, 8); 448 break; 449 } 450 } else if (boot_cpu_data.x86 == 0x19) { 451 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 452 data->read_tempreg = read_tempreg_nb_zen; 453 data->is_zen = true; 454 455 switch (boot_cpu_data.x86_model) { 456 case 0x0 ... 0x1: /* Zen3 SP3/TR */ 457 case 0x21: /* Zen3 Ryzen Desktop */ 458 case 0x50 ... 0x5f: /* Green Sardine */ 459 data->ccd_offset = 0x154; 460 k10temp_get_ccd_support(pdev, data, 8); 461 break; 462 case 0x40 ... 0x4f: /* Yellow Carp */ 463 data->ccd_offset = 0x300; 464 k10temp_get_ccd_support(pdev, data, 8); 465 break; 466 } 467 } else { 468 data->read_htcreg = read_htcreg_pci; 469 data->read_tempreg = read_tempreg_pci; 470 } 471 472 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 473 const struct tctl_offset *entry = &tctl_offset_table[i]; 474 475 if (boot_cpu_data.x86 == entry->model && 476 strstr(boot_cpu_data.x86_model_id, entry->id)) { 477 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ 478 data->temp_offset = entry->offset; 479 break; 480 } 481 } 482 483 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, 484 &k10temp_chip_info, 485 NULL); 486 return PTR_ERR_OR_ZERO(hwmon_dev); 487 } 488 489 static const struct pci_device_id k10temp_id_table[] = { 490 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 491 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 492 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 493 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 494 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 495 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 496 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 497 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, 498 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 499 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 500 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 501 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 502 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, 503 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, 504 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, 505 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, 506 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, 507 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, 508 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 509 {} 510 }; 511 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 512 513 static struct pci_driver k10temp_driver = { 514 .name = "k10temp", 515 .id_table = k10temp_id_table, 516 .probe = k10temp_probe, 517 }; 518 519 module_pci_driver(k10temp_driver); 520