1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h 4 * processor hardware monitoring 5 * 6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net> 8 * 9 * Implementation notes: 10 * - CCD register address information as well as the calculation to 11 * convert raw register values is from https://github.com/ocerman/zenpower. 12 * The information is not confirmed from chip datasheets, but experiments 13 * suggest that it provides reasonable temperature values. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/err.h> 18 #include <linux/hwmon.h> 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pci_ids.h> 23 #include <asm/amd/node.h> 24 #include <asm/processor.h> 25 26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 28 MODULE_LICENSE("GPL"); 29 30 static bool force; 31 module_param(force, bool, 0444); 32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 33 34 /* Provide lock for writing to NB_SMU_IND_ADDR */ 35 static DEFINE_MUTEX(nb_smu_ind_mutex); 36 37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 39 #endif 40 41 /* CPUID function 0x80000001, ebx */ 42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28) 43 #define CPUID_PKGTYPE_F 0x00000000 44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 45 46 /* DRAM controller (PCI function 2) */ 47 #define REG_DCT0_CONFIG_HIGH 0x094 48 #define DDR3_MODE BIT(8) 49 50 /* miscellaneous (PCI function 3) */ 51 #define REG_HARDWARE_THERMAL_CONTROL 0x64 52 #define HTC_ENABLE BIT(0) 53 54 #define REG_REPORTED_TEMPERATURE 0xa4 55 56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 57 #define NB_CAP_HTC BIT(10) 58 59 /* 60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 61 * and REG_REPORTED_TEMPERATURE have been moved to 62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 64 */ 65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 67 68 /* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */ 69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 70 71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ 72 (offset) + ((x) * 4)) 73 #define ZEN_CCD_TEMP_VALID BIT(11) 74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) 75 76 #define ZEN_CUR_TEMP_SHIFT 21 77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) 78 #define ZEN_CUR_TEMP_TJ_SEL_MASK GENMASK(17, 16) 79 80 /* 81 * AMD's Industrial processor 3255 supports temperature from -40 deg to 105 deg Celsius. 82 * Use the model name to identify 3255 CPUs and set a flag to display negative temperature. 83 * Do not round off to zero for negative Tctl or Tdie values if the flag is set 84 */ 85 #define AMD_I3255_STR "3255" 86 87 /* 88 * PCI Device IDs for AMD's Family 1Ah-based SOCs. 89 * Defining locally as IDs are not shared. 90 */ 91 #define PCI_DEVICE_ID_AMD_1AH_M50H_DF_F3 0x12cb 92 #define PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3 0x127b 93 94 struct k10temp_data { 95 struct pci_dev *pdev; 96 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 97 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 98 int temp_offset; 99 u32 temp_adjust_mask; 100 u32 show_temp; 101 bool is_zen; 102 u32 ccd_offset; 103 bool disp_negative; 104 }; 105 106 #define TCTL_BIT 0 107 #define TDIE_BIT 1 108 #define TCCD_BIT(x) ((x) + 2) 109 110 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) 111 112 struct tctl_offset { 113 u8 model; 114 char const *id; 115 int offset; 116 }; 117 118 static const struct tctl_offset tctl_offset_table[] = { 119 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 120 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 121 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 122 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 123 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ 124 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ 125 }; 126 127 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 128 { 129 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 130 } 131 132 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 133 { 134 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 135 } 136 137 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 138 unsigned int base, int offset, u32 *val) 139 { 140 mutex_lock(&nb_smu_ind_mutex); 141 pci_bus_write_config_dword(pdev->bus, devfn, 142 base, offset); 143 pci_bus_read_config_dword(pdev->bus, devfn, 144 base + 4, val); 145 mutex_unlock(&nb_smu_ind_mutex); 146 } 147 148 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 149 { 150 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 151 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 152 } 153 154 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 155 { 156 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 157 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 158 } 159 160 static u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) 161 { 162 return PCI_SLOT(pdev->devfn) - AMD_NODE0_PCI_SLOT; 163 } 164 165 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) 166 { 167 if (amd_smn_read(amd_pci_dev_to_node_id(pdev), 168 ZEN_REPORTED_TEMP_CTRL_BASE, regval)) 169 *regval = 0; 170 } 171 172 static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval) 173 { 174 u16 node_id = amd_pci_dev_to_node_id(data->pdev); 175 176 return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval); 177 } 178 179 static long get_raw_temp(struct k10temp_data *data) 180 { 181 u32 regval; 182 long temp; 183 184 data->read_tempreg(data->pdev, ®val); 185 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; 186 if ((regval & data->temp_adjust_mask) || 187 (regval & ZEN_CUR_TEMP_TJ_SEL_MASK) == ZEN_CUR_TEMP_TJ_SEL_MASK) 188 temp -= 49000; 189 return temp; 190 } 191 192 static const char *k10temp_temp_label[] = { 193 "Tctl", 194 "Tdie", 195 "Tccd1", 196 "Tccd2", 197 "Tccd3", 198 "Tccd4", 199 "Tccd5", 200 "Tccd6", 201 "Tccd7", 202 "Tccd8", 203 "Tccd9", 204 "Tccd10", 205 "Tccd11", 206 "Tccd12", 207 }; 208 209 static int k10temp_read_labels(struct device *dev, 210 enum hwmon_sensor_types type, 211 u32 attr, int channel, const char **str) 212 { 213 switch (type) { 214 case hwmon_temp: 215 *str = k10temp_temp_label[channel]; 216 break; 217 default: 218 return -EOPNOTSUPP; 219 } 220 return 0; 221 } 222 223 static int k10temp_read_temp(struct device *dev, u32 attr, int channel, 224 long *val) 225 { 226 struct k10temp_data *data = dev_get_drvdata(dev); 227 int ret = -EOPNOTSUPP; 228 u32 regval; 229 230 switch (attr) { 231 case hwmon_temp_input: 232 switch (channel) { 233 case 0: /* Tctl */ 234 *val = get_raw_temp(data); 235 if (*val < 0 && !data->disp_negative) 236 *val = 0; 237 break; 238 case 1: /* Tdie */ 239 *val = get_raw_temp(data) - data->temp_offset; 240 if (*val < 0 && !data->disp_negative) 241 *val = 0; 242 break; 243 case 2 ... 13: /* Tccd{1-12} */ 244 ret = read_ccd_temp_reg(data, channel - 2, ®val); 245 246 if (ret) 247 return ret; 248 249 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; 250 break; 251 default: 252 return ret; 253 } 254 break; 255 case hwmon_temp_max: 256 *val = 70 * 1000; 257 break; 258 case hwmon_temp_crit: 259 data->read_htcreg(data->pdev, ®val); 260 *val = ((regval >> 16) & 0x7f) * 500 + 52000; 261 break; 262 case hwmon_temp_crit_hyst: 263 data->read_htcreg(data->pdev, ®val); 264 *val = (((regval >> 16) & 0x7f) 265 - ((regval >> 24) & 0xf)) * 500 + 52000; 266 break; 267 default: 268 return ret; 269 } 270 return 0; 271 } 272 273 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, 274 u32 attr, int channel, long *val) 275 { 276 switch (type) { 277 case hwmon_temp: 278 return k10temp_read_temp(dev, attr, channel, val); 279 default: 280 return -EOPNOTSUPP; 281 } 282 } 283 284 static umode_t k10temp_is_visible(const void *drvdata, 285 enum hwmon_sensor_types type, 286 u32 attr, int channel) 287 { 288 const struct k10temp_data *data = drvdata; 289 struct pci_dev *pdev = data->pdev; 290 u32 reg; 291 292 switch (type) { 293 case hwmon_temp: 294 switch (attr) { 295 case hwmon_temp_input: 296 if (!HAVE_TEMP(data, channel)) 297 return 0; 298 break; 299 case hwmon_temp_max: 300 if (channel || data->is_zen) 301 return 0; 302 break; 303 case hwmon_temp_crit: 304 case hwmon_temp_crit_hyst: 305 if (channel || !data->read_htcreg) 306 return 0; 307 308 pci_read_config_dword(pdev, 309 REG_NORTHBRIDGE_CAPABILITIES, 310 ®); 311 if (!(reg & NB_CAP_HTC)) 312 return 0; 313 314 data->read_htcreg(data->pdev, ®); 315 if (!(reg & HTC_ENABLE)) 316 return 0; 317 break; 318 case hwmon_temp_label: 319 /* Show temperature labels only on Zen CPUs */ 320 if (!data->is_zen || !HAVE_TEMP(data, channel)) 321 return 0; 322 break; 323 default: 324 return 0; 325 } 326 break; 327 default: 328 return 0; 329 } 330 return 0444; 331 } 332 333 static bool has_erratum_319(struct pci_dev *pdev) 334 { 335 u32 pkg_type, reg_dram_cfg; 336 337 if (boot_cpu_data.x86 != 0x10) 338 return false; 339 340 /* 341 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 342 * may be unreliable. 343 */ 344 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 345 if (pkg_type == CPUID_PKGTYPE_F) 346 return true; 347 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 348 return false; 349 350 /* DDR3 memory implies socket AM3, which is good */ 351 pci_bus_read_config_dword(pdev->bus, 352 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 353 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 354 if (reg_dram_cfg & DDR3_MODE) 355 return false; 356 357 /* 358 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 359 * memory. We blacklist all the cores which do exist in socket AM2+ 360 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 361 * and AM3 formats, but that's the best we can do. 362 */ 363 return boot_cpu_data.x86_model < 4 || 364 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 365 } 366 367 static const struct hwmon_channel_info * const k10temp_info[] = { 368 HWMON_CHANNEL_INFO(temp, 369 HWMON_T_INPUT | HWMON_T_MAX | 370 HWMON_T_CRIT | HWMON_T_CRIT_HYST | 371 HWMON_T_LABEL, 372 HWMON_T_INPUT | HWMON_T_LABEL, 373 HWMON_T_INPUT | HWMON_T_LABEL, 374 HWMON_T_INPUT | HWMON_T_LABEL, 375 HWMON_T_INPUT | HWMON_T_LABEL, 376 HWMON_T_INPUT | HWMON_T_LABEL, 377 HWMON_T_INPUT | HWMON_T_LABEL, 378 HWMON_T_INPUT | HWMON_T_LABEL, 379 HWMON_T_INPUT | HWMON_T_LABEL, 380 HWMON_T_INPUT | HWMON_T_LABEL, 381 HWMON_T_INPUT | HWMON_T_LABEL, 382 HWMON_T_INPUT | HWMON_T_LABEL, 383 HWMON_T_INPUT | HWMON_T_LABEL, 384 HWMON_T_INPUT | HWMON_T_LABEL), 385 NULL 386 }; 387 388 static const struct hwmon_ops k10temp_hwmon_ops = { 389 .is_visible = k10temp_is_visible, 390 .read = k10temp_read, 391 .read_string = k10temp_read_labels, 392 }; 393 394 static const struct hwmon_chip_info k10temp_chip_info = { 395 .ops = &k10temp_hwmon_ops, 396 .info = k10temp_info, 397 }; 398 399 static void k10temp_get_ccd_support(struct k10temp_data *data, int limit) 400 { 401 u32 regval; 402 int i; 403 404 for (i = 0; i < limit; i++) { 405 /* 406 * Ignore inaccessible CCDs. 407 * 408 * Some systems will return a register value of 0, and the TEMP_VALID 409 * bit check below will naturally fail. 410 * 411 * Other systems will return a PCI_ERROR_RESPONSE (0xFFFFFFFF) for 412 * the register value. And this will incorrectly pass the TEMP_VALID 413 * bit check. 414 */ 415 if (read_ccd_temp_reg(data, i, ®val)) 416 continue; 417 418 if (regval & ZEN_CCD_TEMP_VALID) 419 data->show_temp |= BIT(TCCD_BIT(i)); 420 } 421 } 422 423 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 424 { 425 int unreliable = has_erratum_319(pdev); 426 struct device *dev = &pdev->dev; 427 struct k10temp_data *data; 428 struct device *hwmon_dev; 429 int i; 430 431 if (unreliable) { 432 if (!force) { 433 dev_err(dev, 434 "unreliable CPU thermal sensor; monitoring disabled\n"); 435 return -ENODEV; 436 } 437 dev_warn(dev, 438 "unreliable CPU thermal sensor; check erratum 319\n"); 439 } 440 441 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 442 if (!data) 443 return -ENOMEM; 444 445 data->pdev = pdev; 446 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ 447 448 if (boot_cpu_data.x86 == 0x17 && 449 strstr(boot_cpu_data.x86_model_id, AMD_I3255_STR)) { 450 data->disp_negative = true; 451 } 452 453 data->is_zen = cpu_feature_enabled(X86_FEATURE_ZEN); 454 if (data->is_zen) { 455 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 456 data->read_tempreg = read_tempreg_nb_zen; 457 } else if (boot_cpu_data.x86 == 0x15 && 458 ((boot_cpu_data.x86_model & 0xf0) == 0x60 || 459 (boot_cpu_data.x86_model & 0xf0) == 0x70)) { 460 data->read_htcreg = read_htcreg_nb_f15; 461 data->read_tempreg = read_tempreg_nb_f15; 462 } else { 463 data->read_htcreg = read_htcreg_pci; 464 data->read_tempreg = read_tempreg_pci; 465 } 466 467 if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { 468 switch (boot_cpu_data.x86_model) { 469 case 0x1: /* Zen */ 470 case 0x8: /* Zen+ */ 471 case 0x11: /* Zen APU */ 472 case 0x18: /* Zen+ APU */ 473 data->ccd_offset = 0x154; 474 k10temp_get_ccd_support(data, 4); 475 break; 476 case 0x31: /* Zen2 Threadripper */ 477 case 0x47: /* Cyan Skillfish */ 478 case 0x60: /* Renoir */ 479 case 0x68: /* Lucienne */ 480 case 0x71: /* Zen2 */ 481 data->ccd_offset = 0x154; 482 k10temp_get_ccd_support(data, 8); 483 break; 484 case 0xa0 ... 0xaf: 485 data->ccd_offset = 0x300; 486 k10temp_get_ccd_support(data, 8); 487 break; 488 } 489 } else if (boot_cpu_data.x86 == 0x19) { 490 switch (boot_cpu_data.x86_model) { 491 case 0x0 ... 0x1: /* Zen3 SP3/TR */ 492 case 0x8: /* Zen3 TR Chagall */ 493 case 0x21: /* Zen3 Ryzen Desktop */ 494 case 0x50 ... 0x5f: /* Green Sardine */ 495 data->ccd_offset = 0x154; 496 k10temp_get_ccd_support(data, 8); 497 break; 498 case 0x40 ... 0x4f: /* Yellow Carp */ 499 data->ccd_offset = 0x300; 500 k10temp_get_ccd_support(data, 8); 501 break; 502 case 0x60 ... 0x6f: 503 case 0x70 ... 0x7f: 504 data->ccd_offset = 0x308; 505 k10temp_get_ccd_support(data, 8); 506 break; 507 case 0x10 ... 0x1f: 508 case 0xa0 ... 0xaf: 509 data->ccd_offset = 0x300; 510 k10temp_get_ccd_support(data, 12); 511 break; 512 } 513 } else if (boot_cpu_data.x86 == 0x1a) { 514 switch (boot_cpu_data.x86_model) { 515 case 0x40 ... 0x4f: /* Zen5 Ryzen Desktop */ 516 data->ccd_offset = 0x308; 517 k10temp_get_ccd_support(data, 8); 518 break; 519 } 520 } 521 522 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 523 const struct tctl_offset *entry = &tctl_offset_table[i]; 524 525 if (boot_cpu_data.x86 == entry->model && 526 strstr(boot_cpu_data.x86_model_id, entry->id)) { 527 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ 528 data->temp_offset = entry->offset; 529 break; 530 } 531 } 532 533 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, 534 &k10temp_chip_info, 535 NULL); 536 return PTR_ERR_OR_ZERO(hwmon_dev); 537 } 538 539 static const struct pci_device_id k10temp_id_table[] = { 540 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 541 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 542 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 543 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 544 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 545 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 546 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 547 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, 548 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 549 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 550 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 551 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 552 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, 553 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M40H_DF_F3) }, 554 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, 555 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, 556 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) }, 557 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, 558 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) }, 559 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, 560 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, 561 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) }, 562 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) }, 563 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, 564 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, 565 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, 566 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M50H_DF_F3) }, 567 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) }, 568 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) }, 569 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M90H_DF_F3) }, 570 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 571 {} 572 }; 573 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 574 575 static struct pci_driver k10temp_driver = { 576 .name = "k10temp", 577 .id_table = k10temp_id_table, 578 .probe = k10temp_probe, 579 }; 580 581 module_pci_driver(k10temp_driver); 582