1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware 4 * monitoring. 5 * 6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a 7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in 8 * addition to an Environment Controller (Enhanced Hardware Monitor and 9 * Fan Controller) 10 * 11 * This driver supports only the Environment Controller in the IT8705F and 12 * similar parts. The other devices are supported by different drivers. 13 * 14 * Supports: IT8603E Super I/O chip w/LPC interface 15 * IT8620E Super I/O chip w/LPC interface 16 * IT8622E Super I/O chip w/LPC interface 17 * IT8623E Super I/O chip w/LPC interface 18 * IT8628E Super I/O chip w/LPC interface 19 * IT8705F Super I/O chip w/LPC interface 20 * IT8712F Super I/O chip w/LPC interface 21 * IT8716F Super I/O chip w/LPC interface 22 * IT8718F Super I/O chip w/LPC interface 23 * IT8720F Super I/O chip w/LPC interface 24 * IT8721F Super I/O chip w/LPC interface 25 * IT8726F Super I/O chip w/LPC interface 26 * IT8728F Super I/O chip w/LPC interface 27 * IT8732F Super I/O chip w/LPC interface 28 * IT8758E Super I/O chip w/LPC interface 29 * IT8771E Super I/O chip w/LPC interface 30 * IT8772E Super I/O chip w/LPC interface 31 * IT8781F Super I/O chip w/LPC interface 32 * IT8782F Super I/O chip w/LPC interface 33 * IT8783E/F Super I/O chip w/LPC interface 34 * IT8786E Super I/O chip w/LPC interface 35 * IT8790E Super I/O chip w/LPC interface 36 * IT8792E Super I/O chip w/LPC interface 37 * IT87952E Super I/O chip w/LPC interface 38 * Sis950 A clone of the IT8705F 39 * 40 * Copyright (C) 2001 Chris Gauthron 41 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> 42 */ 43 44 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 45 46 #include <linux/bitops.h> 47 #include <linux/module.h> 48 #include <linux/init.h> 49 #include <linux/slab.h> 50 #include <linux/jiffies.h> 51 #include <linux/platform_device.h> 52 #include <linux/hwmon.h> 53 #include <linux/hwmon-sysfs.h> 54 #include <linux/hwmon-vid.h> 55 #include <linux/err.h> 56 #include <linux/mutex.h> 57 #include <linux/sysfs.h> 58 #include <linux/string.h> 59 #include <linux/dmi.h> 60 #include <linux/acpi.h> 61 #include <linux/io.h> 62 63 #define DRVNAME "it87" 64 65 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, 66 it8771, it8772, it8781, it8782, it8783, it8786, it8790, 67 it8792, it8603, it8620, it8622, it8628, it87952 }; 68 69 static struct platform_device *it87_pdev[2]; 70 71 #define REG_2E 0x2e /* The register to read/write */ 72 #define REG_4E 0x4e /* Secondary register to read/write */ 73 74 #define DEV 0x07 /* Register: Logical device select */ 75 #define PME 0x04 /* The device with the fan registers in it */ 76 77 /* The device with the IT8718F/IT8720F VID value in it */ 78 #define GPIO 0x07 79 80 #define DEVID 0x20 /* Register: Device ID */ 81 #define DEVREV 0x22 /* Register: Device Revision */ 82 83 static inline void __superio_enter(int ioreg) 84 { 85 outb(0x87, ioreg); 86 outb(0x01, ioreg); 87 outb(0x55, ioreg); 88 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); 89 } 90 91 static inline int superio_inb(int ioreg, int reg) 92 { 93 outb(reg, ioreg); 94 return inb(ioreg + 1); 95 } 96 97 static inline void superio_outb(int ioreg, int reg, int val) 98 { 99 outb(reg, ioreg); 100 outb(val, ioreg + 1); 101 } 102 103 static int superio_inw(int ioreg, int reg) 104 { 105 int val; 106 107 outb(reg++, ioreg); 108 val = inb(ioreg + 1) << 8; 109 outb(reg, ioreg); 110 val |= inb(ioreg + 1); 111 return val; 112 } 113 114 static inline void superio_select(int ioreg, int ldn) 115 { 116 outb(DEV, ioreg); 117 outb(ldn, ioreg + 1); 118 } 119 120 static inline int superio_enter(int ioreg) 121 { 122 /* 123 * Try to reserve ioreg and ioreg + 1 for exclusive access. 124 */ 125 if (!request_muxed_region(ioreg, 2, DRVNAME)) 126 return -EBUSY; 127 128 __superio_enter(ioreg); 129 return 0; 130 } 131 132 static inline void superio_exit(int ioreg, bool noexit) 133 { 134 if (!noexit) { 135 outb(0x02, ioreg); 136 outb(0x02, ioreg + 1); 137 } 138 release_region(ioreg, 2); 139 } 140 141 /* Logical device 4 registers */ 142 #define IT8712F_DEVID 0x8712 143 #define IT8705F_DEVID 0x8705 144 #define IT8716F_DEVID 0x8716 145 #define IT8718F_DEVID 0x8718 146 #define IT8720F_DEVID 0x8720 147 #define IT8721F_DEVID 0x8721 148 #define IT8726F_DEVID 0x8726 149 #define IT8728F_DEVID 0x8728 150 #define IT8732F_DEVID 0x8732 151 #define IT8792E_DEVID 0x8733 152 #define IT8771E_DEVID 0x8771 153 #define IT8772E_DEVID 0x8772 154 #define IT8781F_DEVID 0x8781 155 #define IT8782F_DEVID 0x8782 156 #define IT8783E_DEVID 0x8783 157 #define IT8786E_DEVID 0x8786 158 #define IT8790E_DEVID 0x8790 159 #define IT8603E_DEVID 0x8603 160 #define IT8620E_DEVID 0x8620 161 #define IT8622E_DEVID 0x8622 162 #define IT8623E_DEVID 0x8623 163 #define IT8628E_DEVID 0x8628 164 #define IT87952E_DEVID 0x8695 165 #define IT87_ACT_REG 0x30 166 #define IT87_BASE_REG 0x60 167 168 /* Logical device 7 registers (IT8712F and later) */ 169 #define IT87_SIO_GPIO1_REG 0x25 170 #define IT87_SIO_GPIO2_REG 0x26 171 #define IT87_SIO_GPIO3_REG 0x27 172 #define IT87_SIO_GPIO4_REG 0x28 173 #define IT87_SIO_GPIO5_REG 0x29 174 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ 175 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ 176 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ 177 #define IT87_SIO_VID_REG 0xfc /* VID value */ 178 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ 179 180 /* Force chip IDs to specified values. Should only be used for testing */ 181 static unsigned short force_id[2]; 182 static unsigned int force_id_cnt; 183 184 /* ACPI resource conflicts are ignored if this parameter is set to 1 */ 185 static bool ignore_resource_conflict; 186 187 /* Update battery voltage after every reading if true */ 188 static bool update_vbat; 189 190 /* Not all BIOSes properly configure the PWM registers */ 191 static bool fix_pwm_polarity; 192 193 /* Many IT87 constants specified below */ 194 195 /* Length of ISA address segment */ 196 #define IT87_EXTENT 8 197 198 /* Length of ISA address segment for Environmental Controller */ 199 #define IT87_EC_EXTENT 2 200 201 /* Offset of EC registers from ISA base address */ 202 #define IT87_EC_OFFSET 5 203 204 /* Where are the ISA address/data registers relative to the EC base address */ 205 #define IT87_ADDR_REG_OFFSET 0 206 #define IT87_DATA_REG_OFFSET 1 207 208 /*----- The IT87 registers -----*/ 209 210 #define IT87_REG_CONFIG 0x00 211 212 #define IT87_REG_ALARM1 0x01 213 #define IT87_REG_ALARM2 0x02 214 #define IT87_REG_ALARM3 0x03 215 216 /* 217 * The IT8718F and IT8720F have the VID value in a different register, in 218 * Super-I/O configuration space. 219 */ 220 #define IT87_REG_VID 0x0a 221 /* 222 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b 223 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer 224 * mode. 225 */ 226 #define IT87_REG_FAN_DIV 0x0b 227 #define IT87_REG_FAN_16BIT 0x0c 228 229 /* 230 * Monitors: 231 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) 232 * - up to 6 temp (1 to 6) 233 * - up to 6 fan (1 to 6) 234 */ 235 236 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; 237 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; 238 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; 239 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; 240 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; 241 242 #define IT87_REG_FAN_MAIN_CTRL 0x13 243 #define IT87_REG_FAN_CTL 0x14 244 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; 245 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; 246 247 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 248 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; 249 250 #define IT87_REG_TEMP(nr) (0x29 + (nr)) 251 252 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) 253 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) 254 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) 255 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) 256 257 #define IT87_REG_VIN_ENABLE 0x50 258 #define IT87_REG_TEMP_ENABLE 0x51 259 #define IT87_REG_TEMP_EXTRA 0x55 260 #define IT87_REG_BEEP_ENABLE 0x5c 261 262 #define IT87_REG_CHIPID 0x58 263 264 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; 265 266 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) 267 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) 268 269 #define IT87_REG_TEMP456_ENABLE 0x77 270 271 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) 272 #define NUM_VIN_LIMIT 8 273 #define NUM_TEMP 6 274 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) 275 #define NUM_TEMP_LIMIT 3 276 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) 277 #define NUM_FAN_DIV 3 278 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) 279 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) 280 281 struct it87_devices { 282 const char *name; 283 const char * const model; 284 u32 features; 285 u8 peci_mask; 286 u8 old_peci_mask; 287 }; 288 289 #define FEAT_12MV_ADC BIT(0) 290 #define FEAT_NEWER_AUTOPWM BIT(1) 291 #define FEAT_OLD_AUTOPWM BIT(2) 292 #define FEAT_16BIT_FANS BIT(3) 293 #define FEAT_TEMP_OFFSET BIT(4) 294 #define FEAT_TEMP_PECI BIT(5) 295 #define FEAT_TEMP_OLD_PECI BIT(6) 296 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ 297 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ 298 #define FEAT_VID BIT(9) /* Set if chip supports VID */ 299 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ 300 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ 301 #define FEAT_10_9MV_ADC BIT(12) 302 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ 303 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ 304 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ 305 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ 306 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ 307 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ 308 /* 309 * Disabling configuration mode on some chips can result in system 310 * hang-ups and access failures to the Super-IO chip at the 311 * second SIO address. Never exit configuration mode on these 312 * chips to avoid the problem. 313 */ 314 #define FEAT_CONF_NOEXIT BIT(19) /* Chip should not exit conf mode */ 315 316 static const struct it87_devices it87_devices[] = { 317 [it87] = { 318 .name = "it87", 319 .model = "IT87F", 320 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */ 321 }, 322 [it8712] = { 323 .name = "it8712", 324 .model = "IT8712F", 325 .features = FEAT_OLD_AUTOPWM | FEAT_VID, 326 /* may need to overwrite */ 327 }, 328 [it8716] = { 329 .name = "it8716", 330 .model = "IT8716F", 331 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 332 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2, 333 }, 334 [it8718] = { 335 .name = "it8718", 336 .model = "IT8718F", 337 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 338 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 339 | FEAT_PWM_FREQ2, 340 .old_peci_mask = 0x4, 341 }, 342 [it8720] = { 343 .name = "it8720", 344 .model = "IT8720F", 345 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 346 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 347 | FEAT_PWM_FREQ2, 348 .old_peci_mask = 0x4, 349 }, 350 [it8721] = { 351 .name = "it8721", 352 .model = "IT8721F", 353 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 354 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 355 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL 356 | FEAT_PWM_FREQ2, 357 .peci_mask = 0x05, 358 .old_peci_mask = 0x02, /* Actually reports PCH */ 359 }, 360 [it8728] = { 361 .name = "it8728", 362 .model = "IT8728F", 363 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 364 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 365 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2, 366 .peci_mask = 0x07, 367 }, 368 [it8732] = { 369 .name = "it8732", 370 .model = "IT8732F", 371 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 372 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 373 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL, 374 .peci_mask = 0x07, 375 .old_peci_mask = 0x02, /* Actually reports PCH */ 376 }, 377 [it8771] = { 378 .name = "it8771", 379 .model = "IT8771E", 380 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 381 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 382 | FEAT_PWM_FREQ2, 383 /* PECI: guesswork */ 384 /* 12mV ADC (OHM) */ 385 /* 16 bit fans (OHM) */ 386 /* three fans, always 16 bit (guesswork) */ 387 .peci_mask = 0x07, 388 }, 389 [it8772] = { 390 .name = "it8772", 391 .model = "IT8772E", 392 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 393 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 394 | FEAT_PWM_FREQ2, 395 /* PECI (coreboot) */ 396 /* 12mV ADC (HWSensors4, OHM) */ 397 /* 16 bit fans (HWSensors4, OHM) */ 398 /* three fans, always 16 bit (datasheet) */ 399 .peci_mask = 0x07, 400 }, 401 [it8781] = { 402 .name = "it8781", 403 .model = "IT8781F", 404 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 405 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, 406 .old_peci_mask = 0x4, 407 }, 408 [it8782] = { 409 .name = "it8782", 410 .model = "IT8782F", 411 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 412 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, 413 .old_peci_mask = 0x4, 414 }, 415 [it8783] = { 416 .name = "it8783", 417 .model = "IT8783E/F", 418 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 419 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, 420 .old_peci_mask = 0x4, 421 }, 422 [it8786] = { 423 .name = "it8786", 424 .model = "IT8786E", 425 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 426 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 427 | FEAT_PWM_FREQ2, 428 .peci_mask = 0x07, 429 }, 430 [it8790] = { 431 .name = "it8790", 432 .model = "IT8790E", 433 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 434 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 435 | FEAT_PWM_FREQ2 | FEAT_CONF_NOEXIT, 436 .peci_mask = 0x07, 437 }, 438 [it8792] = { 439 .name = "it8792", 440 .model = "IT8792E/IT8795E", 441 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 442 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 443 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_CONF_NOEXIT, 444 .peci_mask = 0x07, 445 .old_peci_mask = 0x02, /* Actually reports PCH */ 446 }, 447 [it8603] = { 448 .name = "it8603", 449 .model = "IT8603E", 450 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 451 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 452 | FEAT_AVCC3 | FEAT_PWM_FREQ2, 453 .peci_mask = 0x07, 454 }, 455 [it8620] = { 456 .name = "it8620", 457 .model = "IT8620E", 458 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 459 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 460 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 461 | FEAT_SIX_TEMP | FEAT_VIN3_5V, 462 .peci_mask = 0x07, 463 }, 464 [it8622] = { 465 .name = "it8622", 466 .model = "IT8622E", 467 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 468 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 469 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 470 | FEAT_AVCC3 | FEAT_VIN3_5V, 471 .peci_mask = 0x07, 472 }, 473 [it8628] = { 474 .name = "it8628", 475 .model = "IT8628E", 476 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 477 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 478 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 479 | FEAT_SIX_TEMP | FEAT_VIN3_5V, 480 .peci_mask = 0x07, 481 }, 482 [it87952] = { 483 .name = "it87952", 484 .model = "IT87952E", 485 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 486 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 487 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_CONF_NOEXIT, 488 .peci_mask = 0x07, 489 .old_peci_mask = 0x02, /* Actually reports PCH */ 490 }, 491 }; 492 493 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) 494 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) 495 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) 496 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) 497 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) 498 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) 499 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ 500 ((data)->peci_mask & BIT(nr))) 501 #define has_temp_old_peci(data, nr) \ 502 (((data)->features & FEAT_TEMP_OLD_PECI) && \ 503 ((data)->old_peci_mask & BIT(nr))) 504 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) 505 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ 506 FEAT_SIX_FANS)) 507 #define has_vid(data) ((data)->features & FEAT_VID) 508 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) 509 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) 510 #define has_avcc3(data) ((data)->features & FEAT_AVCC3) 511 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \ 512 | FEAT_SIX_PWM)) 513 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) 514 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) 515 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) 516 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) 517 #define has_conf_noexit(data) ((data)->features & FEAT_CONF_NOEXIT) 518 519 struct it87_sio_data { 520 int sioaddr; 521 enum chips type; 522 /* Values read from Super-I/O config space */ 523 u8 revision; 524 u8 vid_value; 525 u8 beep_pin; 526 u8 internal; /* Internal sensors can be labeled */ 527 bool need_in7_reroute; 528 /* Features skipped based on config or DMI */ 529 u16 skip_in; 530 u8 skip_vid; 531 u8 skip_fan; 532 u8 skip_pwm; 533 u8 skip_temp; 534 }; 535 536 /* 537 * For each registered chip, we need to keep some data in memory. 538 * The structure is dynamically allocated. 539 */ 540 struct it87_data { 541 const struct attribute_group *groups[7]; 542 int sioaddr; 543 enum chips type; 544 u32 features; 545 u8 peci_mask; 546 u8 old_peci_mask; 547 548 unsigned short addr; 549 const char *name; 550 struct mutex update_lock; 551 bool valid; /* true if following fields are valid */ 552 unsigned long last_updated; /* In jiffies */ 553 554 u16 in_scaled; /* Internal voltage sensors are scaled */ 555 u16 in_internal; /* Bitfield, internal sensors (for labels) */ 556 u16 has_in; /* Bitfield, voltage sensors enabled */ 557 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ 558 bool need_in7_reroute; 559 u8 has_fan; /* Bitfield, fans enabled */ 560 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ 561 u8 has_temp; /* Bitfield, temp sensors enabled */ 562 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ 563 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ 564 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ 565 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ 566 bool has_vid; /* True if VID supported */ 567 u8 vid; /* Register encoding, combined */ 568 u8 vrm; 569 u32 alarms; /* Register encoding, combined */ 570 bool has_beep; /* true if beep supported */ 571 u8 beeps; /* Register encoding */ 572 u8 fan_main_ctrl; /* Register value */ 573 u8 fan_ctl; /* Register value */ 574 575 /* 576 * The following 3 arrays correspond to the same registers up to 577 * the IT8720F. The meaning of bits 6-0 depends on the value of bit 578 * 7, and we want to preserve settings on mode changes, so we have 579 * to track all values separately. 580 * Starting with the IT8721F, the manual PWM duty cycles are stored 581 * in separate registers (8-bit values), so the separate tracking 582 * is no longer needed, but it is still done to keep the driver 583 * simple. 584 */ 585 u8 has_pwm; /* Bitfield, pwm control enabled */ 586 u8 pwm_ctrl[NUM_PWM]; /* Register value */ 587 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ 588 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ 589 590 /* Automatic fan speed control registers */ 591 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ 592 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ 593 }; 594 595 /* Board specific settings from DMI matching */ 596 struct it87_dmi_data { 597 u8 skip_pwm; /* pwm channels to skip for this board */ 598 }; 599 600 /* Global for results from DMI matching, if needed */ 601 static struct it87_dmi_data *dmi_data; 602 603 static int adc_lsb(const struct it87_data *data, int nr) 604 { 605 int lsb; 606 607 if (has_12mv_adc(data)) 608 lsb = 120; 609 else if (has_10_9mv_adc(data)) 610 lsb = 109; 611 else 612 lsb = 160; 613 if (data->in_scaled & BIT(nr)) 614 lsb <<= 1; 615 return lsb; 616 } 617 618 static u8 in_to_reg(const struct it87_data *data, int nr, long val) 619 { 620 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); 621 return clamp_val(val, 0, 255); 622 } 623 624 static int in_from_reg(const struct it87_data *data, int nr, int val) 625 { 626 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); 627 } 628 629 static inline u8 FAN_TO_REG(long rpm, int div) 630 { 631 if (rpm == 0) 632 return 255; 633 rpm = clamp_val(rpm, 1, 1000000); 634 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); 635 } 636 637 static inline u16 FAN16_TO_REG(long rpm) 638 { 639 if (rpm == 0) 640 return 0xffff; 641 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); 642 } 643 644 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ 645 1350000 / ((val) * (div))) 646 /* The divider is fixed to 2 in 16-bit mode */ 647 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ 648 1350000 / ((val) * 2)) 649 650 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ 651 ((val) + 500) / 1000), -128, 127)) 652 #define TEMP_FROM_REG(val) ((val) * 1000) 653 654 static u8 pwm_to_reg(const struct it87_data *data, long val) 655 { 656 if (has_newer_autopwm(data)) 657 return val; 658 else 659 return val >> 1; 660 } 661 662 static int pwm_from_reg(const struct it87_data *data, u8 reg) 663 { 664 if (has_newer_autopwm(data)) 665 return reg; 666 else 667 return (reg & 0x7f) << 1; 668 } 669 670 static int DIV_TO_REG(int val) 671 { 672 int answer = 0; 673 674 while (answer < 7 && (val >>= 1)) 675 answer++; 676 return answer; 677 } 678 679 #define DIV_FROM_REG(val) BIT(val) 680 681 /* 682 * PWM base frequencies. The frequency has to be divided by either 128 or 256, 683 * depending on the chip type, to calculate the actual PWM frequency. 684 * 685 * Some of the chip datasheets suggest a base frequency of 51 kHz instead 686 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency 687 * of 200 Hz. Sometimes both PWM frequency select registers are affected, 688 * sometimes just one. It is unknown if this is a datasheet error or real, 689 * so this is ignored for now. 690 */ 691 static const unsigned int pwm_freq[8] = { 692 48000000, 693 24000000, 694 12000000, 695 8000000, 696 6000000, 697 3000000, 698 1500000, 699 750000, 700 }; 701 702 /* 703 * Must be called with data->update_lock held, except during initialization. 704 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 705 * would slow down the IT87 access and should not be necessary. 706 */ 707 static int it87_read_value(struct it87_data *data, u8 reg) 708 { 709 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 710 return inb_p(data->addr + IT87_DATA_REG_OFFSET); 711 } 712 713 /* 714 * Must be called with data->update_lock held, except during initialization. 715 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 716 * would slow down the IT87 access and should not be necessary. 717 */ 718 static void it87_write_value(struct it87_data *data, u8 reg, u8 value) 719 { 720 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 721 outb_p(value, data->addr + IT87_DATA_REG_OFFSET); 722 } 723 724 static void it87_update_pwm_ctrl(struct it87_data *data, int nr) 725 { 726 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); 727 if (has_newer_autopwm(data)) { 728 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 729 data->pwm_duty[nr] = it87_read_value(data, 730 IT87_REG_PWM_DUTY[nr]); 731 } else { 732 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ 733 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 734 else /* Manual mode */ 735 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; 736 } 737 738 if (has_old_autopwm(data)) { 739 int i; 740 741 for (i = 0; i < 5 ; i++) 742 data->auto_temp[nr][i] = it87_read_value(data, 743 IT87_REG_AUTO_TEMP(nr, i)); 744 for (i = 0; i < 3 ; i++) 745 data->auto_pwm[nr][i] = it87_read_value(data, 746 IT87_REG_AUTO_PWM(nr, i)); 747 } else if (has_newer_autopwm(data)) { 748 int i; 749 750 /* 751 * 0: temperature hysteresis (base + 5) 752 * 1: fan off temperature (base + 0) 753 * 2: fan start temperature (base + 1) 754 * 3: fan max temperature (base + 2) 755 */ 756 data->auto_temp[nr][0] = 757 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); 758 759 for (i = 0; i < 3 ; i++) 760 data->auto_temp[nr][i + 1] = 761 it87_read_value(data, 762 IT87_REG_AUTO_TEMP(nr, i)); 763 /* 764 * 0: start pwm value (base + 3) 765 * 1: pwm slope (base + 4, 1/8th pwm) 766 */ 767 data->auto_pwm[nr][0] = 768 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); 769 data->auto_pwm[nr][1] = 770 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); 771 } 772 } 773 774 static struct it87_data *it87_update_device(struct device *dev) 775 { 776 struct it87_data *data = dev_get_drvdata(dev); 777 int i; 778 779 mutex_lock(&data->update_lock); 780 781 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || 782 !data->valid) { 783 if (update_vbat) { 784 /* 785 * Cleared after each update, so reenable. Value 786 * returned by this read will be previous value 787 */ 788 it87_write_value(data, IT87_REG_CONFIG, 789 it87_read_value(data, IT87_REG_CONFIG) | 0x40); 790 } 791 for (i = 0; i < NUM_VIN; i++) { 792 if (!(data->has_in & BIT(i))) 793 continue; 794 795 data->in[i][0] = 796 it87_read_value(data, IT87_REG_VIN[i]); 797 798 /* VBAT and AVCC don't have limit registers */ 799 if (i >= NUM_VIN_LIMIT) 800 continue; 801 802 data->in[i][1] = 803 it87_read_value(data, IT87_REG_VIN_MIN(i)); 804 data->in[i][2] = 805 it87_read_value(data, IT87_REG_VIN_MAX(i)); 806 } 807 808 for (i = 0; i < NUM_FAN; i++) { 809 /* Skip disabled fans */ 810 if (!(data->has_fan & BIT(i))) 811 continue; 812 813 data->fan[i][1] = 814 it87_read_value(data, IT87_REG_FAN_MIN[i]); 815 data->fan[i][0] = it87_read_value(data, 816 IT87_REG_FAN[i]); 817 /* Add high byte if in 16-bit mode */ 818 if (has_16bit_fans(data)) { 819 data->fan[i][0] |= it87_read_value(data, 820 IT87_REG_FANX[i]) << 8; 821 data->fan[i][1] |= it87_read_value(data, 822 IT87_REG_FANX_MIN[i]) << 8; 823 } 824 } 825 for (i = 0; i < NUM_TEMP; i++) { 826 if (!(data->has_temp & BIT(i))) 827 continue; 828 data->temp[i][0] = 829 it87_read_value(data, IT87_REG_TEMP(i)); 830 831 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) 832 data->temp[i][3] = 833 it87_read_value(data, 834 IT87_REG_TEMP_OFFSET[i]); 835 836 if (i >= NUM_TEMP_LIMIT) 837 continue; 838 839 data->temp[i][1] = 840 it87_read_value(data, IT87_REG_TEMP_LOW(i)); 841 data->temp[i][2] = 842 it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 843 } 844 845 /* Newer chips don't have clock dividers */ 846 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { 847 i = it87_read_value(data, IT87_REG_FAN_DIV); 848 data->fan_div[0] = i & 0x07; 849 data->fan_div[1] = (i >> 3) & 0x07; 850 data->fan_div[2] = (i & 0x40) ? 3 : 1; 851 } 852 853 data->alarms = 854 it87_read_value(data, IT87_REG_ALARM1) | 855 (it87_read_value(data, IT87_REG_ALARM2) << 8) | 856 (it87_read_value(data, IT87_REG_ALARM3) << 16); 857 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 858 859 data->fan_main_ctrl = it87_read_value(data, 860 IT87_REG_FAN_MAIN_CTRL); 861 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); 862 for (i = 0; i < NUM_PWM; i++) { 863 if (!(data->has_pwm & BIT(i))) 864 continue; 865 it87_update_pwm_ctrl(data, i); 866 } 867 868 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); 869 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 870 /* 871 * The IT8705F does not have VID capability. 872 * The IT8718F and later don't use IT87_REG_VID for the 873 * same purpose. 874 */ 875 if (data->type == it8712 || data->type == it8716) { 876 data->vid = it87_read_value(data, IT87_REG_VID); 877 /* 878 * The older IT8712F revisions had only 5 VID pins, 879 * but we assume it is always safe to read 6 bits. 880 */ 881 data->vid &= 0x3f; 882 } 883 data->last_updated = jiffies; 884 data->valid = true; 885 } 886 887 mutex_unlock(&data->update_lock); 888 889 return data; 890 } 891 892 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 893 char *buf) 894 { 895 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 896 struct it87_data *data = it87_update_device(dev); 897 int index = sattr->index; 898 int nr = sattr->nr; 899 900 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); 901 } 902 903 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 904 const char *buf, size_t count) 905 { 906 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 907 struct it87_data *data = dev_get_drvdata(dev); 908 int index = sattr->index; 909 int nr = sattr->nr; 910 unsigned long val; 911 912 if (kstrtoul(buf, 10, &val) < 0) 913 return -EINVAL; 914 915 mutex_lock(&data->update_lock); 916 data->in[nr][index] = in_to_reg(data, nr, val); 917 it87_write_value(data, 918 index == 1 ? IT87_REG_VIN_MIN(nr) 919 : IT87_REG_VIN_MAX(nr), 920 data->in[nr][index]); 921 mutex_unlock(&data->update_lock); 922 return count; 923 } 924 925 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); 926 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, 927 0, 1); 928 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, 929 0, 2); 930 931 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); 932 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, 933 1, 1); 934 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, 935 1, 2); 936 937 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); 938 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, 939 2, 1); 940 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, 941 2, 2); 942 943 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); 944 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, 945 3, 1); 946 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, 947 3, 2); 948 949 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); 950 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, 951 4, 1); 952 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, 953 4, 2); 954 955 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); 956 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, 957 5, 1); 958 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, 959 5, 2); 960 961 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); 962 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, 963 6, 1); 964 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, 965 6, 2); 966 967 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); 968 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, 969 7, 1); 970 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, 971 7, 2); 972 973 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); 974 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); 975 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); 976 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); 977 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); 978 979 /* Up to 6 temperatures */ 980 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 981 char *buf) 982 { 983 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 984 int nr = sattr->nr; 985 int index = sattr->index; 986 struct it87_data *data = it87_update_device(dev); 987 988 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); 989 } 990 991 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 992 const char *buf, size_t count) 993 { 994 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 995 int nr = sattr->nr; 996 int index = sattr->index; 997 struct it87_data *data = dev_get_drvdata(dev); 998 long val; 999 u8 reg, regval; 1000 1001 if (kstrtol(buf, 10, &val) < 0) 1002 return -EINVAL; 1003 1004 mutex_lock(&data->update_lock); 1005 1006 switch (index) { 1007 default: 1008 case 1: 1009 reg = IT87_REG_TEMP_LOW(nr); 1010 break; 1011 case 2: 1012 reg = IT87_REG_TEMP_HIGH(nr); 1013 break; 1014 case 3: 1015 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); 1016 if (!(regval & 0x80)) { 1017 regval |= 0x80; 1018 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); 1019 } 1020 data->valid = false; 1021 reg = IT87_REG_TEMP_OFFSET[nr]; 1022 break; 1023 } 1024 1025 data->temp[nr][index] = TEMP_TO_REG(val); 1026 it87_write_value(data, reg, data->temp[nr][index]); 1027 mutex_unlock(&data->update_lock); 1028 return count; 1029 } 1030 1031 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); 1032 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1033 0, 1); 1034 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1035 0, 2); 1036 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, 1037 set_temp, 0, 3); 1038 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); 1039 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1040 1, 1); 1041 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1042 1, 2); 1043 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, 1044 set_temp, 1, 3); 1045 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); 1046 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1047 2, 1); 1048 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1049 2, 2); 1050 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, 1051 set_temp, 2, 3); 1052 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); 1053 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); 1054 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); 1055 1056 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, 1057 char *buf) 1058 { 1059 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1060 int nr = sensor_attr->index; 1061 struct it87_data *data = it87_update_device(dev); 1062 u8 reg = data->sensor; /* In case value is updated while used */ 1063 u8 extra = data->extra; 1064 1065 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || 1066 (has_temp_old_peci(data, nr) && (extra & 0x80))) 1067 return sprintf(buf, "6\n"); /* Intel PECI */ 1068 if (reg & (1 << nr)) 1069 return sprintf(buf, "3\n"); /* thermal diode */ 1070 if (reg & (8 << nr)) 1071 return sprintf(buf, "4\n"); /* thermistor */ 1072 return sprintf(buf, "0\n"); /* disabled */ 1073 } 1074 1075 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, 1076 const char *buf, size_t count) 1077 { 1078 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1079 int nr = sensor_attr->index; 1080 1081 struct it87_data *data = dev_get_drvdata(dev); 1082 long val; 1083 u8 reg, extra; 1084 1085 if (kstrtol(buf, 10, &val) < 0) 1086 return -EINVAL; 1087 1088 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1089 reg &= ~(1 << nr); 1090 reg &= ~(8 << nr); 1091 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) 1092 reg &= 0x3f; 1093 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1094 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) 1095 extra &= 0x7f; 1096 if (val == 2) { /* backwards compatibility */ 1097 dev_warn(dev, 1098 "Sensor type 2 is deprecated, please use 4 instead\n"); 1099 val = 4; 1100 } 1101 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ 1102 if (val == 3) 1103 reg |= 1 << nr; 1104 else if (val == 4) 1105 reg |= 8 << nr; 1106 else if (has_temp_peci(data, nr) && val == 6) 1107 reg |= (nr + 1) << 6; 1108 else if (has_temp_old_peci(data, nr) && val == 6) 1109 extra |= 0x80; 1110 else if (val != 0) 1111 return -EINVAL; 1112 1113 mutex_lock(&data->update_lock); 1114 data->sensor = reg; 1115 data->extra = extra; 1116 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); 1117 if (has_temp_old_peci(data, nr)) 1118 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1119 data->valid = false; /* Force cache refresh */ 1120 mutex_unlock(&data->update_lock); 1121 return count; 1122 } 1123 1124 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, 1125 set_temp_type, 0); 1126 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, 1127 set_temp_type, 1); 1128 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, 1129 set_temp_type, 2); 1130 1131 /* 6 Fans */ 1132 1133 static int pwm_mode(const struct it87_data *data, int nr) 1134 { 1135 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr))) 1136 return 0; /* Full speed */ 1137 if (data->pwm_ctrl[nr] & 0x80) 1138 return 2; /* Automatic mode */ 1139 if ((data->type == it8603 || nr >= 3) && 1140 data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) 1141 return 0; /* Full speed */ 1142 1143 return 1; /* Manual mode */ 1144 } 1145 1146 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1147 char *buf) 1148 { 1149 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1150 int nr = sattr->nr; 1151 int index = sattr->index; 1152 int speed; 1153 struct it87_data *data = it87_update_device(dev); 1154 1155 speed = has_16bit_fans(data) ? 1156 FAN16_FROM_REG(data->fan[nr][index]) : 1157 FAN_FROM_REG(data->fan[nr][index], 1158 DIV_FROM_REG(data->fan_div[nr])); 1159 return sprintf(buf, "%d\n", speed); 1160 } 1161 1162 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, 1163 char *buf) 1164 { 1165 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1166 struct it87_data *data = it87_update_device(dev); 1167 int nr = sensor_attr->index; 1168 1169 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); 1170 } 1171 1172 static ssize_t show_pwm_enable(struct device *dev, 1173 struct device_attribute *attr, char *buf) 1174 { 1175 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1176 struct it87_data *data = it87_update_device(dev); 1177 int nr = sensor_attr->index; 1178 1179 return sprintf(buf, "%d\n", pwm_mode(data, nr)); 1180 } 1181 1182 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1183 char *buf) 1184 { 1185 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1186 struct it87_data *data = it87_update_device(dev); 1187 int nr = sensor_attr->index; 1188 1189 return sprintf(buf, "%d\n", 1190 pwm_from_reg(data, data->pwm_duty[nr])); 1191 } 1192 1193 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, 1194 char *buf) 1195 { 1196 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1197 struct it87_data *data = it87_update_device(dev); 1198 int nr = sensor_attr->index; 1199 unsigned int freq; 1200 int index; 1201 1202 if (has_pwm_freq2(data) && nr == 1) 1203 index = (data->extra >> 4) & 0x07; 1204 else 1205 index = (data->fan_ctl >> 4) & 0x07; 1206 1207 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); 1208 1209 return sprintf(buf, "%u\n", freq); 1210 } 1211 1212 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1213 const char *buf, size_t count) 1214 { 1215 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1216 int nr = sattr->nr; 1217 int index = sattr->index; 1218 1219 struct it87_data *data = dev_get_drvdata(dev); 1220 long val; 1221 u8 reg; 1222 1223 if (kstrtol(buf, 10, &val) < 0) 1224 return -EINVAL; 1225 1226 mutex_lock(&data->update_lock); 1227 1228 if (has_16bit_fans(data)) { 1229 data->fan[nr][index] = FAN16_TO_REG(val); 1230 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1231 data->fan[nr][index] & 0xff); 1232 it87_write_value(data, IT87_REG_FANX_MIN[nr], 1233 data->fan[nr][index] >> 8); 1234 } else { 1235 reg = it87_read_value(data, IT87_REG_FAN_DIV); 1236 switch (nr) { 1237 case 0: 1238 data->fan_div[nr] = reg & 0x07; 1239 break; 1240 case 1: 1241 data->fan_div[nr] = (reg >> 3) & 0x07; 1242 break; 1243 case 2: 1244 data->fan_div[nr] = (reg & 0x40) ? 3 : 1; 1245 break; 1246 } 1247 data->fan[nr][index] = 1248 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); 1249 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1250 data->fan[nr][index]); 1251 } 1252 1253 mutex_unlock(&data->update_lock); 1254 return count; 1255 } 1256 1257 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, 1258 const char *buf, size_t count) 1259 { 1260 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1261 struct it87_data *data = dev_get_drvdata(dev); 1262 int nr = sensor_attr->index; 1263 unsigned long val; 1264 int min; 1265 u8 old; 1266 1267 if (kstrtoul(buf, 10, &val) < 0) 1268 return -EINVAL; 1269 1270 mutex_lock(&data->update_lock); 1271 old = it87_read_value(data, IT87_REG_FAN_DIV); 1272 1273 /* Save fan min limit */ 1274 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); 1275 1276 switch (nr) { 1277 case 0: 1278 case 1: 1279 data->fan_div[nr] = DIV_TO_REG(val); 1280 break; 1281 case 2: 1282 if (val < 8) 1283 data->fan_div[nr] = 1; 1284 else 1285 data->fan_div[nr] = 3; 1286 } 1287 val = old & 0x80; 1288 val |= (data->fan_div[0] & 0x07); 1289 val |= (data->fan_div[1] & 0x07) << 3; 1290 if (data->fan_div[2] == 3) 1291 val |= 0x1 << 6; 1292 it87_write_value(data, IT87_REG_FAN_DIV, val); 1293 1294 /* Restore fan min limit */ 1295 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); 1296 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); 1297 1298 mutex_unlock(&data->update_lock); 1299 return count; 1300 } 1301 1302 /* Returns 0 if OK, -EINVAL otherwise */ 1303 static int check_trip_points(struct device *dev, int nr) 1304 { 1305 const struct it87_data *data = dev_get_drvdata(dev); 1306 int i, err = 0; 1307 1308 if (has_old_autopwm(data)) { 1309 for (i = 0; i < 3; i++) { 1310 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1311 err = -EINVAL; 1312 } 1313 for (i = 0; i < 2; i++) { 1314 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) 1315 err = -EINVAL; 1316 } 1317 } else if (has_newer_autopwm(data)) { 1318 for (i = 1; i < 3; i++) { 1319 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1320 err = -EINVAL; 1321 } 1322 } 1323 1324 if (err) { 1325 dev_err(dev, 1326 "Inconsistent trip points, not switching to automatic mode\n"); 1327 dev_err(dev, "Adjust the trip points and try again\n"); 1328 } 1329 return err; 1330 } 1331 1332 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, 1333 const char *buf, size_t count) 1334 { 1335 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1336 struct it87_data *data = dev_get_drvdata(dev); 1337 int nr = sensor_attr->index; 1338 long val; 1339 1340 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) 1341 return -EINVAL; 1342 1343 /* Check trip points before switching to automatic mode */ 1344 if (val == 2) { 1345 if (check_trip_points(dev, nr) < 0) 1346 return -EINVAL; 1347 } 1348 1349 mutex_lock(&data->update_lock); 1350 1351 if (val == 0) { 1352 if (nr < 3 && data->type != it8603) { 1353 int tmp; 1354 /* make sure the fan is on when in on/off mode */ 1355 tmp = it87_read_value(data, IT87_REG_FAN_CTL); 1356 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); 1357 /* set on/off mode */ 1358 data->fan_main_ctrl &= ~BIT(nr); 1359 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1360 data->fan_main_ctrl); 1361 } else { 1362 u8 ctrl; 1363 1364 /* No on/off mode, set maximum pwm value */ 1365 data->pwm_duty[nr] = pwm_to_reg(data, 0xff); 1366 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1367 data->pwm_duty[nr]); 1368 /* and set manual mode */ 1369 if (has_newer_autopwm(data)) { 1370 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1371 data->pwm_temp_map[nr]; 1372 } else { 1373 ctrl = data->pwm_duty[nr]; 1374 } 1375 data->pwm_ctrl[nr] = ctrl; 1376 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1377 } 1378 } else { 1379 u8 ctrl; 1380 1381 if (has_newer_autopwm(data)) { 1382 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1383 data->pwm_temp_map[nr]; 1384 if (val != 1) 1385 ctrl |= 0x80; 1386 } else { 1387 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); 1388 } 1389 data->pwm_ctrl[nr] = ctrl; 1390 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1391 1392 if (data->type != it8603 && nr < 3) { 1393 /* set SmartGuardian mode */ 1394 data->fan_main_ctrl |= BIT(nr); 1395 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1396 data->fan_main_ctrl); 1397 } 1398 } 1399 1400 mutex_unlock(&data->update_lock); 1401 return count; 1402 } 1403 1404 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1405 const char *buf, size_t count) 1406 { 1407 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1408 struct it87_data *data = dev_get_drvdata(dev); 1409 int nr = sensor_attr->index; 1410 long val; 1411 1412 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1413 return -EINVAL; 1414 1415 mutex_lock(&data->update_lock); 1416 it87_update_pwm_ctrl(data, nr); 1417 if (has_newer_autopwm(data)) { 1418 /* 1419 * If we are in automatic mode, the PWM duty cycle register 1420 * is read-only so we can't write the value. 1421 */ 1422 if (data->pwm_ctrl[nr] & 0x80) { 1423 mutex_unlock(&data->update_lock); 1424 return -EBUSY; 1425 } 1426 data->pwm_duty[nr] = pwm_to_reg(data, val); 1427 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1428 data->pwm_duty[nr]); 1429 } else { 1430 data->pwm_duty[nr] = pwm_to_reg(data, val); 1431 /* 1432 * If we are in manual mode, write the duty cycle immediately; 1433 * otherwise, just store it for later use. 1434 */ 1435 if (!(data->pwm_ctrl[nr] & 0x80)) { 1436 data->pwm_ctrl[nr] = data->pwm_duty[nr]; 1437 it87_write_value(data, IT87_REG_PWM[nr], 1438 data->pwm_ctrl[nr]); 1439 } 1440 } 1441 mutex_unlock(&data->update_lock); 1442 return count; 1443 } 1444 1445 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, 1446 const char *buf, size_t count) 1447 { 1448 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1449 struct it87_data *data = dev_get_drvdata(dev); 1450 int nr = sensor_attr->index; 1451 unsigned long val; 1452 int i; 1453 1454 if (kstrtoul(buf, 10, &val) < 0) 1455 return -EINVAL; 1456 1457 val = clamp_val(val, 0, 1000000); 1458 val *= has_newer_autopwm(data) ? 256 : 128; 1459 1460 /* Search for the nearest available frequency */ 1461 for (i = 0; i < 7; i++) { 1462 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) 1463 break; 1464 } 1465 1466 mutex_lock(&data->update_lock); 1467 if (nr == 0) { 1468 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; 1469 data->fan_ctl |= i << 4; 1470 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); 1471 } else { 1472 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; 1473 data->extra |= i << 4; 1474 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1475 } 1476 mutex_unlock(&data->update_lock); 1477 1478 return count; 1479 } 1480 1481 static ssize_t show_pwm_temp_map(struct device *dev, 1482 struct device_attribute *attr, char *buf) 1483 { 1484 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1485 struct it87_data *data = it87_update_device(dev); 1486 int nr = sensor_attr->index; 1487 int map; 1488 1489 map = data->pwm_temp_map[nr]; 1490 if (map >= 3) 1491 map = 0; /* Should never happen */ 1492 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ 1493 map += 3; 1494 1495 return sprintf(buf, "%d\n", (int)BIT(map)); 1496 } 1497 1498 static ssize_t set_pwm_temp_map(struct device *dev, 1499 struct device_attribute *attr, const char *buf, 1500 size_t count) 1501 { 1502 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1503 struct it87_data *data = dev_get_drvdata(dev); 1504 int nr = sensor_attr->index; 1505 long val; 1506 u8 reg; 1507 1508 if (kstrtol(buf, 10, &val) < 0) 1509 return -EINVAL; 1510 1511 if (nr >= 3) 1512 val -= 3; 1513 1514 switch (val) { 1515 case BIT(0): 1516 reg = 0x00; 1517 break; 1518 case BIT(1): 1519 reg = 0x01; 1520 break; 1521 case BIT(2): 1522 reg = 0x02; 1523 break; 1524 default: 1525 return -EINVAL; 1526 } 1527 1528 mutex_lock(&data->update_lock); 1529 it87_update_pwm_ctrl(data, nr); 1530 data->pwm_temp_map[nr] = reg; 1531 /* 1532 * If we are in automatic mode, write the temp mapping immediately; 1533 * otherwise, just store it for later use. 1534 */ 1535 if (data->pwm_ctrl[nr] & 0x80) { 1536 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | 1537 data->pwm_temp_map[nr]; 1538 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); 1539 } 1540 mutex_unlock(&data->update_lock); 1541 return count; 1542 } 1543 1544 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, 1545 char *buf) 1546 { 1547 struct it87_data *data = it87_update_device(dev); 1548 struct sensor_device_attribute_2 *sensor_attr = 1549 to_sensor_dev_attr_2(attr); 1550 int nr = sensor_attr->nr; 1551 int point = sensor_attr->index; 1552 1553 return sprintf(buf, "%d\n", 1554 pwm_from_reg(data, data->auto_pwm[nr][point])); 1555 } 1556 1557 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, 1558 const char *buf, size_t count) 1559 { 1560 struct it87_data *data = dev_get_drvdata(dev); 1561 struct sensor_device_attribute_2 *sensor_attr = 1562 to_sensor_dev_attr_2(attr); 1563 int nr = sensor_attr->nr; 1564 int point = sensor_attr->index; 1565 int regaddr; 1566 long val; 1567 1568 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1569 return -EINVAL; 1570 1571 mutex_lock(&data->update_lock); 1572 data->auto_pwm[nr][point] = pwm_to_reg(data, val); 1573 if (has_newer_autopwm(data)) 1574 regaddr = IT87_REG_AUTO_TEMP(nr, 3); 1575 else 1576 regaddr = IT87_REG_AUTO_PWM(nr, point); 1577 it87_write_value(data, regaddr, data->auto_pwm[nr][point]); 1578 mutex_unlock(&data->update_lock); 1579 return count; 1580 } 1581 1582 static ssize_t show_auto_pwm_slope(struct device *dev, 1583 struct device_attribute *attr, char *buf) 1584 { 1585 struct it87_data *data = it87_update_device(dev); 1586 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1587 int nr = sensor_attr->index; 1588 1589 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); 1590 } 1591 1592 static ssize_t set_auto_pwm_slope(struct device *dev, 1593 struct device_attribute *attr, 1594 const char *buf, size_t count) 1595 { 1596 struct it87_data *data = dev_get_drvdata(dev); 1597 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1598 int nr = sensor_attr->index; 1599 unsigned long val; 1600 1601 if (kstrtoul(buf, 10, &val) < 0 || val > 127) 1602 return -EINVAL; 1603 1604 mutex_lock(&data->update_lock); 1605 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; 1606 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), 1607 data->auto_pwm[nr][1]); 1608 mutex_unlock(&data->update_lock); 1609 return count; 1610 } 1611 1612 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, 1613 char *buf) 1614 { 1615 struct it87_data *data = it87_update_device(dev); 1616 struct sensor_device_attribute_2 *sensor_attr = 1617 to_sensor_dev_attr_2(attr); 1618 int nr = sensor_attr->nr; 1619 int point = sensor_attr->index; 1620 int reg; 1621 1622 if (has_old_autopwm(data) || point) 1623 reg = data->auto_temp[nr][point]; 1624 else 1625 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); 1626 1627 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); 1628 } 1629 1630 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, 1631 const char *buf, size_t count) 1632 { 1633 struct it87_data *data = dev_get_drvdata(dev); 1634 struct sensor_device_attribute_2 *sensor_attr = 1635 to_sensor_dev_attr_2(attr); 1636 int nr = sensor_attr->nr; 1637 int point = sensor_attr->index; 1638 long val; 1639 int reg; 1640 1641 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) 1642 return -EINVAL; 1643 1644 mutex_lock(&data->update_lock); 1645 if (has_newer_autopwm(data) && !point) { 1646 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); 1647 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); 1648 data->auto_temp[nr][0] = reg; 1649 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); 1650 } else { 1651 reg = TEMP_TO_REG(val); 1652 data->auto_temp[nr][point] = reg; 1653 if (has_newer_autopwm(data)) 1654 point--; 1655 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); 1656 } 1657 mutex_unlock(&data->update_lock); 1658 return count; 1659 } 1660 1661 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); 1662 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1663 0, 1); 1664 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, 1665 set_fan_div, 0); 1666 1667 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); 1668 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1669 1, 1); 1670 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, 1671 set_fan_div, 1); 1672 1673 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); 1674 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1675 2, 1); 1676 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, 1677 set_fan_div, 2); 1678 1679 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); 1680 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1681 3, 1); 1682 1683 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); 1684 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1685 4, 1); 1686 1687 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); 1688 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1689 5, 1); 1690 1691 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, 1692 show_pwm_enable, set_pwm_enable, 0); 1693 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); 1694 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, 1695 set_pwm_freq, 0); 1696 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, 1697 show_pwm_temp_map, set_pwm_temp_map, 0); 1698 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, 1699 show_auto_pwm, set_auto_pwm, 0, 0); 1700 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, 1701 show_auto_pwm, set_auto_pwm, 0, 1); 1702 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, 1703 show_auto_pwm, set_auto_pwm, 0, 2); 1704 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, 1705 show_auto_pwm, NULL, 0, 3); 1706 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, 1707 show_auto_temp, set_auto_temp, 0, 1); 1708 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1709 show_auto_temp, set_auto_temp, 0, 0); 1710 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, 1711 show_auto_temp, set_auto_temp, 0, 2); 1712 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, 1713 show_auto_temp, set_auto_temp, 0, 3); 1714 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, 1715 show_auto_temp, set_auto_temp, 0, 4); 1716 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, 1717 show_auto_pwm, set_auto_pwm, 0, 0); 1718 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, 1719 show_auto_pwm_slope, set_auto_pwm_slope, 0); 1720 1721 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, 1722 show_pwm_enable, set_pwm_enable, 1); 1723 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); 1724 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); 1725 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, 1726 show_pwm_temp_map, set_pwm_temp_map, 1); 1727 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, 1728 show_auto_pwm, set_auto_pwm, 1, 0); 1729 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, 1730 show_auto_pwm, set_auto_pwm, 1, 1); 1731 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, 1732 show_auto_pwm, set_auto_pwm, 1, 2); 1733 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, 1734 show_auto_pwm, NULL, 1, 3); 1735 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, 1736 show_auto_temp, set_auto_temp, 1, 1); 1737 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1738 show_auto_temp, set_auto_temp, 1, 0); 1739 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, 1740 show_auto_temp, set_auto_temp, 1, 2); 1741 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, 1742 show_auto_temp, set_auto_temp, 1, 3); 1743 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, 1744 show_auto_temp, set_auto_temp, 1, 4); 1745 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, 1746 show_auto_pwm, set_auto_pwm, 1, 0); 1747 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, 1748 show_auto_pwm_slope, set_auto_pwm_slope, 1); 1749 1750 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, 1751 show_pwm_enable, set_pwm_enable, 2); 1752 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); 1753 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); 1754 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, 1755 show_pwm_temp_map, set_pwm_temp_map, 2); 1756 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, 1757 show_auto_pwm, set_auto_pwm, 2, 0); 1758 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, 1759 show_auto_pwm, set_auto_pwm, 2, 1); 1760 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, 1761 show_auto_pwm, set_auto_pwm, 2, 2); 1762 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, 1763 show_auto_pwm, NULL, 2, 3); 1764 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, 1765 show_auto_temp, set_auto_temp, 2, 1); 1766 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1767 show_auto_temp, set_auto_temp, 2, 0); 1768 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, 1769 show_auto_temp, set_auto_temp, 2, 2); 1770 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, 1771 show_auto_temp, set_auto_temp, 2, 3); 1772 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, 1773 show_auto_temp, set_auto_temp, 2, 4); 1774 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, 1775 show_auto_pwm, set_auto_pwm, 2, 0); 1776 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, 1777 show_auto_pwm_slope, set_auto_pwm_slope, 2); 1778 1779 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, 1780 show_pwm_enable, set_pwm_enable, 3); 1781 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); 1782 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); 1783 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, 1784 show_pwm_temp_map, set_pwm_temp_map, 3); 1785 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, 1786 show_auto_temp, set_auto_temp, 2, 1); 1787 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1788 show_auto_temp, set_auto_temp, 2, 0); 1789 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, 1790 show_auto_temp, set_auto_temp, 2, 2); 1791 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, 1792 show_auto_temp, set_auto_temp, 2, 3); 1793 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, 1794 show_auto_pwm, set_auto_pwm, 3, 0); 1795 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, 1796 show_auto_pwm_slope, set_auto_pwm_slope, 3); 1797 1798 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, 1799 show_pwm_enable, set_pwm_enable, 4); 1800 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); 1801 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); 1802 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, 1803 show_pwm_temp_map, set_pwm_temp_map, 4); 1804 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, 1805 show_auto_temp, set_auto_temp, 2, 1); 1806 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1807 show_auto_temp, set_auto_temp, 2, 0); 1808 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, 1809 show_auto_temp, set_auto_temp, 2, 2); 1810 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, 1811 show_auto_temp, set_auto_temp, 2, 3); 1812 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, 1813 show_auto_pwm, set_auto_pwm, 4, 0); 1814 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, 1815 show_auto_pwm_slope, set_auto_pwm_slope, 4); 1816 1817 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, 1818 show_pwm_enable, set_pwm_enable, 5); 1819 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); 1820 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); 1821 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, 1822 show_pwm_temp_map, set_pwm_temp_map, 5); 1823 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, 1824 show_auto_temp, set_auto_temp, 2, 1); 1825 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1826 show_auto_temp, set_auto_temp, 2, 0); 1827 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, 1828 show_auto_temp, set_auto_temp, 2, 2); 1829 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, 1830 show_auto_temp, set_auto_temp, 2, 3); 1831 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, 1832 show_auto_pwm, set_auto_pwm, 5, 0); 1833 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, 1834 show_auto_pwm_slope, set_auto_pwm_slope, 5); 1835 1836 /* Alarms */ 1837 static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, 1838 char *buf) 1839 { 1840 struct it87_data *data = it87_update_device(dev); 1841 1842 return sprintf(buf, "%u\n", data->alarms); 1843 } 1844 static DEVICE_ATTR_RO(alarms); 1845 1846 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, 1847 char *buf) 1848 { 1849 struct it87_data *data = it87_update_device(dev); 1850 int bitnr = to_sensor_dev_attr(attr)->index; 1851 1852 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); 1853 } 1854 1855 static ssize_t clear_intrusion(struct device *dev, 1856 struct device_attribute *attr, const char *buf, 1857 size_t count) 1858 { 1859 struct it87_data *data = dev_get_drvdata(dev); 1860 int config; 1861 long val; 1862 1863 if (kstrtol(buf, 10, &val) < 0 || val != 0) 1864 return -EINVAL; 1865 1866 mutex_lock(&data->update_lock); 1867 config = it87_read_value(data, IT87_REG_CONFIG); 1868 if (config < 0) { 1869 count = config; 1870 } else { 1871 config |= BIT(5); 1872 it87_write_value(data, IT87_REG_CONFIG, config); 1873 /* Invalidate cache to force re-read */ 1874 data->valid = false; 1875 } 1876 mutex_unlock(&data->update_lock); 1877 1878 return count; 1879 } 1880 1881 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); 1882 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); 1883 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); 1884 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); 1885 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); 1886 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); 1887 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); 1888 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); 1889 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); 1890 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); 1891 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); 1892 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); 1893 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); 1894 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); 1895 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); 1896 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); 1897 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); 1898 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, 1899 show_alarm, clear_intrusion, 4); 1900 1901 static ssize_t show_beep(struct device *dev, struct device_attribute *attr, 1902 char *buf) 1903 { 1904 struct it87_data *data = it87_update_device(dev); 1905 int bitnr = to_sensor_dev_attr(attr)->index; 1906 1907 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); 1908 } 1909 1910 static ssize_t set_beep(struct device *dev, struct device_attribute *attr, 1911 const char *buf, size_t count) 1912 { 1913 int bitnr = to_sensor_dev_attr(attr)->index; 1914 struct it87_data *data = dev_get_drvdata(dev); 1915 long val; 1916 1917 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) 1918 return -EINVAL; 1919 1920 mutex_lock(&data->update_lock); 1921 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 1922 if (val) 1923 data->beeps |= BIT(bitnr); 1924 else 1925 data->beeps &= ~BIT(bitnr); 1926 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); 1927 mutex_unlock(&data->update_lock); 1928 return count; 1929 } 1930 1931 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, 1932 show_beep, set_beep, 1); 1933 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); 1934 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); 1935 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); 1936 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); 1937 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); 1938 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); 1939 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); 1940 /* fanX_beep writability is set later */ 1941 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); 1942 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); 1943 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); 1944 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); 1945 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); 1946 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); 1947 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, 1948 show_beep, set_beep, 2); 1949 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); 1950 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); 1951 1952 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, 1953 char *buf) 1954 { 1955 struct it87_data *data = dev_get_drvdata(dev); 1956 1957 return sprintf(buf, "%u\n", data->vrm); 1958 } 1959 1960 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, 1961 const char *buf, size_t count) 1962 { 1963 struct it87_data *data = dev_get_drvdata(dev); 1964 unsigned long val; 1965 1966 if (kstrtoul(buf, 10, &val) < 0) 1967 return -EINVAL; 1968 1969 data->vrm = val; 1970 1971 return count; 1972 } 1973 static DEVICE_ATTR_RW(vrm); 1974 1975 static ssize_t cpu0_vid_show(struct device *dev, 1976 struct device_attribute *attr, char *buf) 1977 { 1978 struct it87_data *data = it87_update_device(dev); 1979 1980 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); 1981 } 1982 static DEVICE_ATTR_RO(cpu0_vid); 1983 1984 static ssize_t show_label(struct device *dev, struct device_attribute *attr, 1985 char *buf) 1986 { 1987 static const char * const labels[] = { 1988 "+5V", 1989 "5VSB", 1990 "Vbat", 1991 "AVCC", 1992 }; 1993 static const char * const labels_it8721[] = { 1994 "+3.3V", 1995 "3VSB", 1996 "Vbat", 1997 "+3.3V", 1998 }; 1999 struct it87_data *data = dev_get_drvdata(dev); 2000 int nr = to_sensor_dev_attr(attr)->index; 2001 const char *label; 2002 2003 if (has_vin3_5v(data) && nr == 0) 2004 label = labels[0]; 2005 else if (has_12mv_adc(data) || has_10_9mv_adc(data)) 2006 label = labels_it8721[nr]; 2007 else 2008 label = labels[nr]; 2009 2010 return sprintf(buf, "%s\n", label); 2011 } 2012 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); 2013 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); 2014 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); 2015 /* AVCC3 */ 2016 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); 2017 2018 static umode_t it87_in_is_visible(struct kobject *kobj, 2019 struct attribute *attr, int index) 2020 { 2021 struct device *dev = kobj_to_dev(kobj); 2022 struct it87_data *data = dev_get_drvdata(dev); 2023 int i = index / 5; /* voltage index */ 2024 int a = index % 5; /* attribute index */ 2025 2026 if (index >= 40) { /* in8 and higher only have input attributes */ 2027 i = index - 40 + 8; 2028 a = 0; 2029 } 2030 2031 if (!(data->has_in & BIT(i))) 2032 return 0; 2033 2034 if (a == 4 && !data->has_beep) 2035 return 0; 2036 2037 return attr->mode; 2038 } 2039 2040 static struct attribute *it87_attributes_in[] = { 2041 &sensor_dev_attr_in0_input.dev_attr.attr, 2042 &sensor_dev_attr_in0_min.dev_attr.attr, 2043 &sensor_dev_attr_in0_max.dev_attr.attr, 2044 &sensor_dev_attr_in0_alarm.dev_attr.attr, 2045 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ 2046 2047 &sensor_dev_attr_in1_input.dev_attr.attr, 2048 &sensor_dev_attr_in1_min.dev_attr.attr, 2049 &sensor_dev_attr_in1_max.dev_attr.attr, 2050 &sensor_dev_attr_in1_alarm.dev_attr.attr, 2051 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ 2052 2053 &sensor_dev_attr_in2_input.dev_attr.attr, 2054 &sensor_dev_attr_in2_min.dev_attr.attr, 2055 &sensor_dev_attr_in2_max.dev_attr.attr, 2056 &sensor_dev_attr_in2_alarm.dev_attr.attr, 2057 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ 2058 2059 &sensor_dev_attr_in3_input.dev_attr.attr, 2060 &sensor_dev_attr_in3_min.dev_attr.attr, 2061 &sensor_dev_attr_in3_max.dev_attr.attr, 2062 &sensor_dev_attr_in3_alarm.dev_attr.attr, 2063 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ 2064 2065 &sensor_dev_attr_in4_input.dev_attr.attr, 2066 &sensor_dev_attr_in4_min.dev_attr.attr, 2067 &sensor_dev_attr_in4_max.dev_attr.attr, 2068 &sensor_dev_attr_in4_alarm.dev_attr.attr, 2069 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ 2070 2071 &sensor_dev_attr_in5_input.dev_attr.attr, 2072 &sensor_dev_attr_in5_min.dev_attr.attr, 2073 &sensor_dev_attr_in5_max.dev_attr.attr, 2074 &sensor_dev_attr_in5_alarm.dev_attr.attr, 2075 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ 2076 2077 &sensor_dev_attr_in6_input.dev_attr.attr, 2078 &sensor_dev_attr_in6_min.dev_attr.attr, 2079 &sensor_dev_attr_in6_max.dev_attr.attr, 2080 &sensor_dev_attr_in6_alarm.dev_attr.attr, 2081 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ 2082 2083 &sensor_dev_attr_in7_input.dev_attr.attr, 2084 &sensor_dev_attr_in7_min.dev_attr.attr, 2085 &sensor_dev_attr_in7_max.dev_attr.attr, 2086 &sensor_dev_attr_in7_alarm.dev_attr.attr, 2087 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ 2088 2089 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ 2090 &sensor_dev_attr_in9_input.dev_attr.attr, 2091 &sensor_dev_attr_in10_input.dev_attr.attr, 2092 &sensor_dev_attr_in11_input.dev_attr.attr, 2093 &sensor_dev_attr_in12_input.dev_attr.attr, 2094 NULL 2095 }; 2096 2097 static const struct attribute_group it87_group_in = { 2098 .attrs = it87_attributes_in, 2099 .is_visible = it87_in_is_visible, 2100 }; 2101 2102 static umode_t it87_temp_is_visible(struct kobject *kobj, 2103 struct attribute *attr, int index) 2104 { 2105 struct device *dev = kobj_to_dev(kobj); 2106 struct it87_data *data = dev_get_drvdata(dev); 2107 int i = index / 7; /* temperature index */ 2108 int a = index % 7; /* attribute index */ 2109 2110 if (index >= 21) { 2111 i = index - 21 + 3; 2112 a = 0; 2113 } 2114 2115 if (!(data->has_temp & BIT(i))) 2116 return 0; 2117 2118 if (a == 5 && !has_temp_offset(data)) 2119 return 0; 2120 2121 if (a == 6 && !data->has_beep) 2122 return 0; 2123 2124 return attr->mode; 2125 } 2126 2127 static struct attribute *it87_attributes_temp[] = { 2128 &sensor_dev_attr_temp1_input.dev_attr.attr, 2129 &sensor_dev_attr_temp1_max.dev_attr.attr, 2130 &sensor_dev_attr_temp1_min.dev_attr.attr, 2131 &sensor_dev_attr_temp1_type.dev_attr.attr, 2132 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 2133 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ 2134 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ 2135 2136 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ 2137 &sensor_dev_attr_temp2_max.dev_attr.attr, 2138 &sensor_dev_attr_temp2_min.dev_attr.attr, 2139 &sensor_dev_attr_temp2_type.dev_attr.attr, 2140 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 2141 &sensor_dev_attr_temp2_offset.dev_attr.attr, 2142 &sensor_dev_attr_temp2_beep.dev_attr.attr, 2143 2144 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ 2145 &sensor_dev_attr_temp3_max.dev_attr.attr, 2146 &sensor_dev_attr_temp3_min.dev_attr.attr, 2147 &sensor_dev_attr_temp3_type.dev_attr.attr, 2148 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 2149 &sensor_dev_attr_temp3_offset.dev_attr.attr, 2150 &sensor_dev_attr_temp3_beep.dev_attr.attr, 2151 2152 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ 2153 &sensor_dev_attr_temp5_input.dev_attr.attr, 2154 &sensor_dev_attr_temp6_input.dev_attr.attr, 2155 NULL 2156 }; 2157 2158 static const struct attribute_group it87_group_temp = { 2159 .attrs = it87_attributes_temp, 2160 .is_visible = it87_temp_is_visible, 2161 }; 2162 2163 static umode_t it87_is_visible(struct kobject *kobj, 2164 struct attribute *attr, int index) 2165 { 2166 struct device *dev = kobj_to_dev(kobj); 2167 struct it87_data *data = dev_get_drvdata(dev); 2168 2169 if ((index == 2 || index == 3) && !data->has_vid) 2170 return 0; 2171 2172 if (index > 3 && !(data->in_internal & BIT(index - 4))) 2173 return 0; 2174 2175 return attr->mode; 2176 } 2177 2178 static struct attribute *it87_attributes[] = { 2179 &dev_attr_alarms.attr, 2180 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, 2181 &dev_attr_vrm.attr, /* 2 */ 2182 &dev_attr_cpu0_vid.attr, /* 3 */ 2183 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ 2184 &sensor_dev_attr_in7_label.dev_attr.attr, 2185 &sensor_dev_attr_in8_label.dev_attr.attr, 2186 &sensor_dev_attr_in9_label.dev_attr.attr, 2187 NULL 2188 }; 2189 2190 static const struct attribute_group it87_group = { 2191 .attrs = it87_attributes, 2192 .is_visible = it87_is_visible, 2193 }; 2194 2195 static umode_t it87_fan_is_visible(struct kobject *kobj, 2196 struct attribute *attr, int index) 2197 { 2198 struct device *dev = kobj_to_dev(kobj); 2199 struct it87_data *data = dev_get_drvdata(dev); 2200 int i = index / 5; /* fan index */ 2201 int a = index % 5; /* attribute index */ 2202 2203 if (index >= 15) { /* fan 4..6 don't have divisor attributes */ 2204 i = (index - 15) / 4 + 3; 2205 a = (index - 15) % 4; 2206 } 2207 2208 if (!(data->has_fan & BIT(i))) 2209 return 0; 2210 2211 if (a == 3) { /* beep */ 2212 if (!data->has_beep) 2213 return 0; 2214 /* first fan beep attribute is writable */ 2215 if (i == __ffs(data->has_fan)) 2216 return attr->mode | S_IWUSR; 2217 } 2218 2219 if (a == 4 && has_16bit_fans(data)) /* divisor */ 2220 return 0; 2221 2222 return attr->mode; 2223 } 2224 2225 static struct attribute *it87_attributes_fan[] = { 2226 &sensor_dev_attr_fan1_input.dev_attr.attr, 2227 &sensor_dev_attr_fan1_min.dev_attr.attr, 2228 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 2229 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ 2230 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ 2231 2232 &sensor_dev_attr_fan2_input.dev_attr.attr, 2233 &sensor_dev_attr_fan2_min.dev_attr.attr, 2234 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 2235 &sensor_dev_attr_fan2_beep.dev_attr.attr, 2236 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ 2237 2238 &sensor_dev_attr_fan3_input.dev_attr.attr, 2239 &sensor_dev_attr_fan3_min.dev_attr.attr, 2240 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 2241 &sensor_dev_attr_fan3_beep.dev_attr.attr, 2242 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ 2243 2244 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ 2245 &sensor_dev_attr_fan4_min.dev_attr.attr, 2246 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 2247 &sensor_dev_attr_fan4_beep.dev_attr.attr, 2248 2249 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ 2250 &sensor_dev_attr_fan5_min.dev_attr.attr, 2251 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 2252 &sensor_dev_attr_fan5_beep.dev_attr.attr, 2253 2254 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ 2255 &sensor_dev_attr_fan6_min.dev_attr.attr, 2256 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 2257 &sensor_dev_attr_fan6_beep.dev_attr.attr, 2258 NULL 2259 }; 2260 2261 static const struct attribute_group it87_group_fan = { 2262 .attrs = it87_attributes_fan, 2263 .is_visible = it87_fan_is_visible, 2264 }; 2265 2266 static umode_t it87_pwm_is_visible(struct kobject *kobj, 2267 struct attribute *attr, int index) 2268 { 2269 struct device *dev = kobj_to_dev(kobj); 2270 struct it87_data *data = dev_get_drvdata(dev); 2271 int i = index / 4; /* pwm index */ 2272 int a = index % 4; /* attribute index */ 2273 2274 if (!(data->has_pwm & BIT(i))) 2275 return 0; 2276 2277 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ 2278 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) 2279 return attr->mode | S_IWUSR; 2280 2281 /* pwm2_freq is writable if there are two pwm frequency selects */ 2282 if (has_pwm_freq2(data) && i == 1 && a == 2) 2283 return attr->mode | S_IWUSR; 2284 2285 return attr->mode; 2286 } 2287 2288 static struct attribute *it87_attributes_pwm[] = { 2289 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 2290 &sensor_dev_attr_pwm1.dev_attr.attr, 2291 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 2292 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, 2293 2294 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 2295 &sensor_dev_attr_pwm2.dev_attr.attr, 2296 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 2297 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, 2298 2299 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 2300 &sensor_dev_attr_pwm3.dev_attr.attr, 2301 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 2302 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, 2303 2304 &sensor_dev_attr_pwm4_enable.dev_attr.attr, 2305 &sensor_dev_attr_pwm4.dev_attr.attr, 2306 &sensor_dev_attr_pwm4_freq.dev_attr.attr, 2307 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, 2308 2309 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 2310 &sensor_dev_attr_pwm5.dev_attr.attr, 2311 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 2312 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, 2313 2314 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 2315 &sensor_dev_attr_pwm6.dev_attr.attr, 2316 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 2317 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, 2318 2319 NULL 2320 }; 2321 2322 static const struct attribute_group it87_group_pwm = { 2323 .attrs = it87_attributes_pwm, 2324 .is_visible = it87_pwm_is_visible, 2325 }; 2326 2327 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, 2328 struct attribute *attr, int index) 2329 { 2330 struct device *dev = kobj_to_dev(kobj); 2331 struct it87_data *data = dev_get_drvdata(dev); 2332 int i = index / 11; /* pwm index */ 2333 int a = index % 11; /* attribute index */ 2334 2335 if (index >= 33) { /* pwm 4..6 */ 2336 i = (index - 33) / 6 + 3; 2337 a = (index - 33) % 6 + 4; 2338 } 2339 2340 if (!(data->has_pwm & BIT(i))) 2341 return 0; 2342 2343 if (has_newer_autopwm(data)) { 2344 if (a < 4) /* no auto point pwm */ 2345 return 0; 2346 if (a == 8) /* no auto_point4 */ 2347 return 0; 2348 } 2349 if (has_old_autopwm(data)) { 2350 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ 2351 return 0; 2352 } 2353 2354 return attr->mode; 2355 } 2356 2357 static struct attribute *it87_attributes_auto_pwm[] = { 2358 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 2359 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 2360 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, 2361 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, 2362 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, 2363 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, 2364 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, 2365 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, 2366 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, 2367 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, 2368 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, 2369 2370 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ 2371 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 2372 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, 2373 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, 2374 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, 2375 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, 2376 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, 2377 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, 2378 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, 2379 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, 2380 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, 2381 2382 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ 2383 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 2384 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, 2385 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, 2386 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, 2387 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, 2388 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, 2389 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, 2390 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, 2391 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, 2392 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, 2393 2394 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ 2395 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, 2396 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, 2397 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, 2398 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, 2399 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, 2400 2401 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, 2402 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, 2403 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, 2404 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, 2405 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, 2406 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, 2407 2408 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, 2409 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, 2410 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, 2411 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, 2412 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, 2413 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, 2414 2415 NULL, 2416 }; 2417 2418 static const struct attribute_group it87_group_auto_pwm = { 2419 .attrs = it87_attributes_auto_pwm, 2420 .is_visible = it87_auto_pwm_is_visible, 2421 }; 2422 2423 /* SuperIO detection - will change isa_address if a chip is found */ 2424 static int __init it87_find(int sioaddr, unsigned short *address, 2425 struct it87_sio_data *sio_data, int chip_cnt) 2426 { 2427 int err; 2428 u16 chip_type; 2429 const struct it87_devices *config = NULL; 2430 2431 err = superio_enter(sioaddr); 2432 if (err) 2433 return err; 2434 2435 err = -ENODEV; 2436 chip_type = superio_inw(sioaddr, DEVID); 2437 /* check first for a valid chip before forcing chip id */ 2438 if (chip_type == 0xffff) 2439 goto exit; 2440 2441 if (force_id_cnt == 1) { 2442 /* If only one value given use for all chips */ 2443 if (force_id[0]) 2444 chip_type = force_id[0]; 2445 } else if (force_id[chip_cnt]) 2446 chip_type = force_id[chip_cnt]; 2447 2448 switch (chip_type) { 2449 case IT8705F_DEVID: 2450 sio_data->type = it87; 2451 break; 2452 case IT8712F_DEVID: 2453 sio_data->type = it8712; 2454 break; 2455 case IT8716F_DEVID: 2456 case IT8726F_DEVID: 2457 sio_data->type = it8716; 2458 break; 2459 case IT8718F_DEVID: 2460 sio_data->type = it8718; 2461 break; 2462 case IT8720F_DEVID: 2463 sio_data->type = it8720; 2464 break; 2465 case IT8721F_DEVID: 2466 sio_data->type = it8721; 2467 break; 2468 case IT8728F_DEVID: 2469 sio_data->type = it8728; 2470 break; 2471 case IT8732F_DEVID: 2472 sio_data->type = it8732; 2473 break; 2474 case IT8792E_DEVID: 2475 sio_data->type = it8792; 2476 break; 2477 case IT8771E_DEVID: 2478 sio_data->type = it8771; 2479 break; 2480 case IT8772E_DEVID: 2481 sio_data->type = it8772; 2482 break; 2483 case IT8781F_DEVID: 2484 sio_data->type = it8781; 2485 break; 2486 case IT8782F_DEVID: 2487 sio_data->type = it8782; 2488 break; 2489 case IT8783E_DEVID: 2490 sio_data->type = it8783; 2491 break; 2492 case IT8786E_DEVID: 2493 sio_data->type = it8786; 2494 break; 2495 case IT8790E_DEVID: 2496 sio_data->type = it8790; 2497 break; 2498 case IT8603E_DEVID: 2499 case IT8623E_DEVID: 2500 sio_data->type = it8603; 2501 break; 2502 case IT8620E_DEVID: 2503 sio_data->type = it8620; 2504 break; 2505 case IT8622E_DEVID: 2506 sio_data->type = it8622; 2507 break; 2508 case IT8628E_DEVID: 2509 sio_data->type = it8628; 2510 break; 2511 case IT87952E_DEVID: 2512 sio_data->type = it87952; 2513 break; 2514 case 0xffff: /* No device at all */ 2515 goto exit; 2516 default: 2517 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); 2518 goto exit; 2519 } 2520 2521 config = &it87_devices[sio_data->type]; 2522 2523 superio_select(sioaddr, PME); 2524 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { 2525 pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n", 2526 config->model, sioaddr); 2527 goto exit; 2528 } 2529 2530 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); 2531 if (*address == 0) { 2532 pr_info("Base address not set (chip %s ioreg 0x%x), skipping\n", 2533 config->model, sioaddr); 2534 goto exit; 2535 } 2536 2537 err = 0; 2538 sio_data->sioaddr = sioaddr; 2539 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; 2540 pr_info("Found %s chip at 0x%x, revision %d\n", 2541 it87_devices[sio_data->type].model, 2542 *address, sio_data->revision); 2543 2544 /* in7 (VSB or VCCH5V) is always internal on some chips */ 2545 if (has_in7_internal(config)) 2546 sio_data->internal |= BIT(1); 2547 2548 /* in8 (Vbat) is always internal */ 2549 sio_data->internal |= BIT(2); 2550 2551 /* in9 (AVCC3), always internal if supported */ 2552 if (has_avcc3(config)) 2553 sio_data->internal |= BIT(3); /* in9 is AVCC */ 2554 else 2555 sio_data->skip_in |= BIT(9); 2556 2557 if (!has_five_pwm(config)) 2558 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); 2559 else if (!has_six_pwm(config)) 2560 sio_data->skip_pwm |= BIT(5); 2561 2562 if (!has_vid(config)) 2563 sio_data->skip_vid = 1; 2564 2565 /* Read GPIO config and VID value from LDN 7 (GPIO) */ 2566 if (sio_data->type == it87) { 2567 /* The IT8705F has a different LD number for GPIO */ 2568 superio_select(sioaddr, 5); 2569 sio_data->beep_pin = superio_inb(sioaddr, 2570 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2571 } else if (sio_data->type == it8783) { 2572 int reg25, reg27, reg2a, reg2c, regef; 2573 2574 superio_select(sioaddr, GPIO); 2575 2576 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2577 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2578 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); 2579 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2580 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); 2581 2582 /* Check if fan3 is there or not */ 2583 if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) 2584 sio_data->skip_fan |= BIT(2); 2585 if ((reg25 & BIT(4)) || 2586 (!(reg2a & BIT(1)) && (regef & BIT(0)))) 2587 sio_data->skip_pwm |= BIT(2); 2588 2589 /* Check if fan2 is there or not */ 2590 if (reg27 & BIT(7)) 2591 sio_data->skip_fan |= BIT(1); 2592 if (reg27 & BIT(3)) 2593 sio_data->skip_pwm |= BIT(1); 2594 2595 /* VIN5 */ 2596 if ((reg27 & BIT(0)) || (reg2c & BIT(2))) 2597 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2598 2599 /* VIN6 */ 2600 if (reg27 & BIT(1)) 2601 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2602 2603 /* 2604 * VIN7 2605 * Does not depend on bit 2 of Reg2C, contrary to datasheet. 2606 */ 2607 if (reg27 & BIT(2)) { 2608 /* 2609 * The data sheet is a bit unclear regarding the 2610 * internal voltage divider for VCCH5V. It says 2611 * "This bit enables and switches VIN7 (pin 91) to the 2612 * internal voltage divider for VCCH5V". 2613 * This is different to other chips, where the internal 2614 * voltage divider would connect VIN7 to an internal 2615 * voltage source. Maybe that is the case here as well. 2616 * 2617 * Since we don't know for sure, re-route it if that is 2618 * not the case, and ask the user to report if the 2619 * resulting voltage is sane. 2620 */ 2621 if (!(reg2c & BIT(1))) { 2622 reg2c |= BIT(1); 2623 superio_outb(sioaddr, IT87_SIO_PINX2_REG, 2624 reg2c); 2625 sio_data->need_in7_reroute = true; 2626 pr_notice("Routing internal VCCH5V to in7.\n"); 2627 } 2628 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); 2629 pr_notice("Please report if it displays a reasonable voltage.\n"); 2630 } 2631 2632 if (reg2c & BIT(0)) 2633 sio_data->internal |= BIT(0); 2634 if (reg2c & BIT(1)) 2635 sio_data->internal |= BIT(1); 2636 2637 sio_data->beep_pin = superio_inb(sioaddr, 2638 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2639 } else if (sio_data->type == it8603) { 2640 int reg27, reg29; 2641 2642 superio_select(sioaddr, GPIO); 2643 2644 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2645 2646 /* Check if fan3 is there or not */ 2647 if (reg27 & BIT(6)) 2648 sio_data->skip_pwm |= BIT(2); 2649 if (reg27 & BIT(7)) 2650 sio_data->skip_fan |= BIT(2); 2651 2652 /* Check if fan2 is there or not */ 2653 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2654 if (reg29 & BIT(1)) 2655 sio_data->skip_pwm |= BIT(1); 2656 if (reg29 & BIT(2)) 2657 sio_data->skip_fan |= BIT(1); 2658 2659 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2660 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2661 2662 sio_data->beep_pin = superio_inb(sioaddr, 2663 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2664 } else if (sio_data->type == it8620 || sio_data->type == it8628) { 2665 int reg; 2666 2667 superio_select(sioaddr, GPIO); 2668 2669 /* Check for pwm5 */ 2670 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2671 if (reg & BIT(6)) 2672 sio_data->skip_pwm |= BIT(4); 2673 2674 /* Check for fan4, fan5 */ 2675 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2676 if (!(reg & BIT(5))) 2677 sio_data->skip_fan |= BIT(3); 2678 if (!(reg & BIT(4))) 2679 sio_data->skip_fan |= BIT(4); 2680 2681 /* Check for pwm3, fan3 */ 2682 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2683 if (reg & BIT(6)) 2684 sio_data->skip_pwm |= BIT(2); 2685 if (reg & BIT(7)) 2686 sio_data->skip_fan |= BIT(2); 2687 2688 /* Check for pwm4 */ 2689 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 2690 if (reg & BIT(2)) 2691 sio_data->skip_pwm |= BIT(3); 2692 2693 /* Check for pwm2, fan2 */ 2694 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2695 if (reg & BIT(1)) 2696 sio_data->skip_pwm |= BIT(1); 2697 if (reg & BIT(2)) 2698 sio_data->skip_fan |= BIT(1); 2699 /* Check for pwm6, fan6 */ 2700 if (!(reg & BIT(7))) { 2701 sio_data->skip_pwm |= BIT(5); 2702 sio_data->skip_fan |= BIT(5); 2703 } 2704 2705 /* Check if AVCC is on VIN3 */ 2706 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2707 if (reg & BIT(0)) 2708 sio_data->internal |= BIT(0); 2709 else 2710 sio_data->skip_in |= BIT(9); 2711 2712 sio_data->beep_pin = superio_inb(sioaddr, 2713 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2714 } else if (sio_data->type == it8622) { 2715 int reg; 2716 2717 superio_select(sioaddr, GPIO); 2718 2719 /* Check for pwm4, fan4 */ 2720 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2721 if (reg & BIT(6)) 2722 sio_data->skip_fan |= BIT(3); 2723 if (reg & BIT(5)) 2724 sio_data->skip_pwm |= BIT(3); 2725 2726 /* Check for pwm3, fan3, pwm5, fan5 */ 2727 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2728 if (reg & BIT(6)) 2729 sio_data->skip_pwm |= BIT(2); 2730 if (reg & BIT(7)) 2731 sio_data->skip_fan |= BIT(2); 2732 if (reg & BIT(3)) 2733 sio_data->skip_pwm |= BIT(4); 2734 if (reg & BIT(1)) 2735 sio_data->skip_fan |= BIT(4); 2736 2737 /* Check for pwm2, fan2 */ 2738 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2739 if (reg & BIT(1)) 2740 sio_data->skip_pwm |= BIT(1); 2741 if (reg & BIT(2)) 2742 sio_data->skip_fan |= BIT(1); 2743 2744 /* Check for AVCC */ 2745 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2746 if (!(reg & BIT(0))) 2747 sio_data->skip_in |= BIT(9); 2748 2749 sio_data->beep_pin = superio_inb(sioaddr, 2750 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2751 } else { 2752 int reg; 2753 bool uart6; 2754 2755 superio_select(sioaddr, GPIO); 2756 2757 /* Check for fan4, fan5 */ 2758 if (has_five_fans(config)) { 2759 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2760 switch (sio_data->type) { 2761 case it8718: 2762 if (reg & BIT(5)) 2763 sio_data->skip_fan |= BIT(3); 2764 if (reg & BIT(4)) 2765 sio_data->skip_fan |= BIT(4); 2766 break; 2767 case it8720: 2768 case it8721: 2769 case it8728: 2770 if (!(reg & BIT(5))) 2771 sio_data->skip_fan |= BIT(3); 2772 if (!(reg & BIT(4))) 2773 sio_data->skip_fan |= BIT(4); 2774 break; 2775 default: 2776 break; 2777 } 2778 } 2779 2780 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2781 if (!sio_data->skip_vid) { 2782 /* We need at least 4 VID pins */ 2783 if (reg & 0x0f) { 2784 pr_info("VID is disabled (pins used for GPIO)\n"); 2785 sio_data->skip_vid = 1; 2786 } 2787 } 2788 2789 /* Check if fan3 is there or not */ 2790 if (reg & BIT(6)) 2791 sio_data->skip_pwm |= BIT(2); 2792 if (reg & BIT(7)) 2793 sio_data->skip_fan |= BIT(2); 2794 2795 /* Check if fan2 is there or not */ 2796 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2797 if (reg & BIT(1)) 2798 sio_data->skip_pwm |= BIT(1); 2799 if (reg & BIT(2)) 2800 sio_data->skip_fan |= BIT(1); 2801 2802 if ((sio_data->type == it8718 || sio_data->type == it8720) && 2803 !(sio_data->skip_vid)) 2804 sio_data->vid_value = superio_inb(sioaddr, 2805 IT87_SIO_VID_REG); 2806 2807 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2808 2809 uart6 = sio_data->type == it8782 && (reg & BIT(2)); 2810 2811 /* 2812 * The IT8720F has no VIN7 pin, so VCCH5V should always be 2813 * routed internally to VIN7 with an internal divider. 2814 * Curiously, there still is a configuration bit to control 2815 * this, which means it can be set incorrectly. And even 2816 * more curiously, many boards out there are improperly 2817 * configured, even though the IT8720F datasheet claims 2818 * that the internal routing of VCCH5V to VIN7 is the default 2819 * setting. So we force the internal routing in this case. 2820 * 2821 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. 2822 * If UART6 is enabled, re-route VIN7 to the internal divider 2823 * if that is not already the case. 2824 */ 2825 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { 2826 reg |= BIT(1); 2827 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); 2828 sio_data->need_in7_reroute = true; 2829 pr_notice("Routing internal VCCH5V to in7\n"); 2830 } 2831 if (reg & BIT(0)) 2832 sio_data->internal |= BIT(0); 2833 if (reg & BIT(1)) 2834 sio_data->internal |= BIT(1); 2835 2836 /* 2837 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. 2838 * While VIN7 can be routed to the internal voltage divider, 2839 * VIN5 and VIN6 are not available if UART6 is enabled. 2840 * 2841 * Also, temp3 is not available if UART6 is enabled and TEMPIN3 2842 * is the temperature source. Since we can not read the 2843 * temperature source here, skip_temp is preliminary. 2844 */ 2845 if (uart6) { 2846 sio_data->skip_in |= BIT(5) | BIT(6); 2847 sio_data->skip_temp |= BIT(2); 2848 } 2849 2850 sio_data->beep_pin = superio_inb(sioaddr, 2851 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2852 } 2853 if (sio_data->beep_pin) 2854 pr_info("Beeping is supported\n"); 2855 2856 /* Set values based on DMI matches */ 2857 if (dmi_data) 2858 sio_data->skip_pwm |= dmi_data->skip_pwm; 2859 2860 exit: 2861 superio_exit(sioaddr, config ? has_conf_noexit(config) : false); 2862 return err; 2863 } 2864 2865 /* 2866 * Some chips seem to have default value 0xff for all limit 2867 * registers. For low voltage limits it makes no sense and triggers 2868 * alarms, so change to 0 instead. For high temperature limits, it 2869 * means -1 degree C, which surprisingly doesn't trigger an alarm, 2870 * but is still confusing, so change to 127 degrees C. 2871 */ 2872 static void it87_check_limit_regs(struct it87_data *data) 2873 { 2874 int i, reg; 2875 2876 for (i = 0; i < NUM_VIN_LIMIT; i++) { 2877 reg = it87_read_value(data, IT87_REG_VIN_MIN(i)); 2878 if (reg == 0xff) 2879 it87_write_value(data, IT87_REG_VIN_MIN(i), 0); 2880 } 2881 for (i = 0; i < NUM_TEMP_LIMIT; i++) { 2882 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 2883 if (reg == 0xff) 2884 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); 2885 } 2886 } 2887 2888 /* Check if voltage monitors are reset manually or by some reason */ 2889 static void it87_check_voltage_monitors_reset(struct it87_data *data) 2890 { 2891 int reg; 2892 2893 reg = it87_read_value(data, IT87_REG_VIN_ENABLE); 2894 if ((reg & 0xff) == 0) { 2895 /* Enable all voltage monitors */ 2896 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); 2897 } 2898 } 2899 2900 /* Check if tachometers are reset manually or by some reason */ 2901 static void it87_check_tachometers_reset(struct platform_device *pdev) 2902 { 2903 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 2904 struct it87_data *data = platform_get_drvdata(pdev); 2905 u8 mask, fan_main_ctrl; 2906 2907 mask = 0x70 & ~(sio_data->skip_fan << 4); 2908 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 2909 if ((fan_main_ctrl & mask) == 0) { 2910 /* Enable all fan tachometers */ 2911 fan_main_ctrl |= mask; 2912 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 2913 fan_main_ctrl); 2914 } 2915 } 2916 2917 /* Set tachometers to 16-bit mode if needed */ 2918 static void it87_check_tachometers_16bit_mode(struct platform_device *pdev) 2919 { 2920 struct it87_data *data = platform_get_drvdata(pdev); 2921 int reg; 2922 2923 if (!has_fan16_config(data)) 2924 return; 2925 2926 reg = it87_read_value(data, IT87_REG_FAN_16BIT); 2927 if (~reg & 0x07 & data->has_fan) { 2928 dev_dbg(&pdev->dev, 2929 "Setting fan1-3 to 16-bit mode\n"); 2930 it87_write_value(data, IT87_REG_FAN_16BIT, 2931 reg | 0x07); 2932 } 2933 } 2934 2935 static void it87_start_monitoring(struct it87_data *data) 2936 { 2937 it87_write_value(data, IT87_REG_CONFIG, 2938 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) 2939 | (update_vbat ? 0x41 : 0x01)); 2940 } 2941 2942 /* Called when we have found a new IT87. */ 2943 static void it87_init_device(struct platform_device *pdev) 2944 { 2945 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 2946 struct it87_data *data = platform_get_drvdata(pdev); 2947 int tmp, i; 2948 2949 /* 2950 * For each PWM channel: 2951 * - If it is in automatic mode, setting to manual mode should set 2952 * the fan to full speed by default. 2953 * - If it is in manual mode, we need a mapping to temperature 2954 * channels to use when later setting to automatic mode later. 2955 * Use a 1:1 mapping by default (we are clueless.) 2956 * In both cases, the value can (and should) be changed by the user 2957 * prior to switching to a different mode. 2958 * Note that this is no longer needed for the IT8721F and later, as 2959 * these have separate registers for the temperature mapping and the 2960 * manual duty cycle. 2961 */ 2962 for (i = 0; i < NUM_AUTO_PWM; i++) { 2963 data->pwm_temp_map[i] = i; 2964 data->pwm_duty[i] = 0x7f; /* Full speed */ 2965 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ 2966 } 2967 2968 it87_check_limit_regs(data); 2969 2970 /* 2971 * Temperature channels are not forcibly enabled, as they can be 2972 * set to two different sensor types and we can't guess which one 2973 * is correct for a given system. These channels can be enabled at 2974 * run-time through the temp{1-3}_type sysfs accessors if needed. 2975 */ 2976 2977 it87_check_voltage_monitors_reset(data); 2978 2979 it87_check_tachometers_reset(pdev); 2980 2981 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 2982 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; 2983 2984 it87_check_tachometers_16bit_mode(pdev); 2985 2986 /* Check for additional fans */ 2987 if (has_five_fans(data)) { 2988 tmp = it87_read_value(data, IT87_REG_FAN_16BIT); 2989 2990 if (tmp & BIT(4)) 2991 data->has_fan |= BIT(3); /* fan4 enabled */ 2992 if (tmp & BIT(5)) 2993 data->has_fan |= BIT(4); /* fan5 enabled */ 2994 if (has_six_fans(data) && (tmp & BIT(2))) 2995 data->has_fan |= BIT(5); /* fan6 enabled */ 2996 } 2997 2998 /* Fan input pins may be used for alternative functions */ 2999 data->has_fan &= ~sio_data->skip_fan; 3000 3001 /* Check if pwm5, pwm6 are enabled */ 3002 if (has_six_pwm(data)) { 3003 /* The following code may be IT8620E specific */ 3004 tmp = it87_read_value(data, IT87_REG_FAN_DIV); 3005 if ((tmp & 0xc0) == 0xc0) 3006 sio_data->skip_pwm |= BIT(4); 3007 if (!(tmp & BIT(3))) 3008 sio_data->skip_pwm |= BIT(5); 3009 } 3010 3011 it87_start_monitoring(data); 3012 } 3013 3014 /* Return 1 if and only if the PWM interface is safe to use */ 3015 static int it87_check_pwm(struct device *dev) 3016 { 3017 struct it87_data *data = dev_get_drvdata(dev); 3018 /* 3019 * Some BIOSes fail to correctly configure the IT87 fans. All fans off 3020 * and polarity set to active low is sign that this is the case so we 3021 * disable pwm control to protect the user. 3022 */ 3023 int tmp = it87_read_value(data, IT87_REG_FAN_CTL); 3024 3025 if ((tmp & 0x87) == 0) { 3026 if (fix_pwm_polarity) { 3027 /* 3028 * The user asks us to attempt a chip reconfiguration. 3029 * This means switching to active high polarity and 3030 * inverting all fan speed values. 3031 */ 3032 int i; 3033 u8 pwm[3]; 3034 3035 for (i = 0; i < ARRAY_SIZE(pwm); i++) 3036 pwm[i] = it87_read_value(data, 3037 IT87_REG_PWM[i]); 3038 3039 /* 3040 * If any fan is in automatic pwm mode, the polarity 3041 * might be correct, as suspicious as it seems, so we 3042 * better don't change anything (but still disable the 3043 * PWM interface). 3044 */ 3045 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { 3046 dev_info(dev, 3047 "Reconfiguring PWM to active high polarity\n"); 3048 it87_write_value(data, IT87_REG_FAN_CTL, 3049 tmp | 0x87); 3050 for (i = 0; i < 3; i++) 3051 it87_write_value(data, 3052 IT87_REG_PWM[i], 3053 0x7f & ~pwm[i]); 3054 return 1; 3055 } 3056 3057 dev_info(dev, 3058 "PWM configuration is too broken to be fixed\n"); 3059 } 3060 3061 return 0; 3062 } else if (fix_pwm_polarity) { 3063 dev_info(dev, 3064 "PWM configuration looks sane, won't touch\n"); 3065 } 3066 3067 return 1; 3068 } 3069 3070 static int it87_probe(struct platform_device *pdev) 3071 { 3072 struct it87_data *data; 3073 struct resource *res; 3074 struct device *dev = &pdev->dev; 3075 struct it87_sio_data *sio_data = dev_get_platdata(dev); 3076 int enable_pwm_interface; 3077 struct device *hwmon_dev; 3078 3079 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 3080 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, 3081 DRVNAME)) { 3082 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", 3083 (unsigned long)res->start, 3084 (unsigned long)(res->start + IT87_EC_EXTENT - 1)); 3085 return -EBUSY; 3086 } 3087 3088 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); 3089 if (!data) 3090 return -ENOMEM; 3091 3092 data->addr = res->start; 3093 data->sioaddr = sio_data->sioaddr; 3094 data->type = sio_data->type; 3095 data->features = it87_devices[sio_data->type].features; 3096 data->peci_mask = it87_devices[sio_data->type].peci_mask; 3097 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; 3098 /* 3099 * IT8705F Datasheet 0.4.1, 3h == Version G. 3100 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. 3101 * These are the first revisions with 16-bit tachometer support. 3102 */ 3103 switch (data->type) { 3104 case it87: 3105 if (sio_data->revision >= 0x03) { 3106 data->features &= ~FEAT_OLD_AUTOPWM; 3107 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; 3108 } 3109 break; 3110 case it8712: 3111 if (sio_data->revision >= 0x08) { 3112 data->features &= ~FEAT_OLD_AUTOPWM; 3113 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | 3114 FEAT_FIVE_FANS; 3115 } 3116 break; 3117 default: 3118 break; 3119 } 3120 3121 /* Now, we do the remaining detection. */ 3122 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || 3123 it87_read_value(data, IT87_REG_CHIPID) != 0x90) 3124 return -ENODEV; 3125 3126 platform_set_drvdata(pdev, data); 3127 3128 mutex_init(&data->update_lock); 3129 3130 /* Check PWM configuration */ 3131 enable_pwm_interface = it87_check_pwm(dev); 3132 if (!enable_pwm_interface) 3133 dev_info(dev, 3134 "Detected broken BIOS defaults, disabling PWM interface\n"); 3135 3136 /* Starting with IT8721F, we handle scaling of internal voltages */ 3137 if (has_12mv_adc(data)) { 3138 if (sio_data->internal & BIT(0)) 3139 data->in_scaled |= BIT(3); /* in3 is AVCC */ 3140 if (sio_data->internal & BIT(1)) 3141 data->in_scaled |= BIT(7); /* in7 is VSB */ 3142 if (sio_data->internal & BIT(2)) 3143 data->in_scaled |= BIT(8); /* in8 is Vbat */ 3144 if (sio_data->internal & BIT(3)) 3145 data->in_scaled |= BIT(9); /* in9 is AVCC */ 3146 } else if (sio_data->type == it8781 || sio_data->type == it8782 || 3147 sio_data->type == it8783) { 3148 if (sio_data->internal & BIT(0)) 3149 data->in_scaled |= BIT(3); /* in3 is VCC5V */ 3150 if (sio_data->internal & BIT(1)) 3151 data->in_scaled |= BIT(7); /* in7 is VCCH5V */ 3152 } 3153 3154 data->has_temp = 0x07; 3155 if (sio_data->skip_temp & BIT(2)) { 3156 if (sio_data->type == it8782 && 3157 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) 3158 data->has_temp &= ~BIT(2); 3159 } 3160 3161 data->in_internal = sio_data->internal; 3162 data->need_in7_reroute = sio_data->need_in7_reroute; 3163 data->has_in = 0x3ff & ~sio_data->skip_in; 3164 3165 if (has_six_temp(data)) { 3166 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); 3167 3168 /* Check for additional temperature sensors */ 3169 if ((reg & 0x03) >= 0x02) 3170 data->has_temp |= BIT(3); 3171 if (((reg >> 2) & 0x03) >= 0x02) 3172 data->has_temp |= BIT(4); 3173 if (((reg >> 4) & 0x03) >= 0x02) 3174 data->has_temp |= BIT(5); 3175 3176 /* Check for additional voltage sensors */ 3177 if ((reg & 0x03) == 0x01) 3178 data->has_in |= BIT(10); 3179 if (((reg >> 2) & 0x03) == 0x01) 3180 data->has_in |= BIT(11); 3181 if (((reg >> 4) & 0x03) == 0x01) 3182 data->has_in |= BIT(12); 3183 } 3184 3185 data->has_beep = !!sio_data->beep_pin; 3186 3187 /* Initialize the IT87 chip */ 3188 it87_init_device(pdev); 3189 3190 if (!sio_data->skip_vid) { 3191 data->has_vid = true; 3192 data->vrm = vid_which_vrm(); 3193 /* VID reading from Super-I/O config space if available */ 3194 data->vid = sio_data->vid_value; 3195 } 3196 3197 /* Prepare for sysfs hooks */ 3198 data->groups[0] = &it87_group; 3199 data->groups[1] = &it87_group_in; 3200 data->groups[2] = &it87_group_temp; 3201 data->groups[3] = &it87_group_fan; 3202 3203 if (enable_pwm_interface) { 3204 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; 3205 data->has_pwm &= ~sio_data->skip_pwm; 3206 3207 data->groups[4] = &it87_group_pwm; 3208 if (has_old_autopwm(data) || has_newer_autopwm(data)) 3209 data->groups[5] = &it87_group_auto_pwm; 3210 } 3211 3212 hwmon_dev = devm_hwmon_device_register_with_groups(dev, 3213 it87_devices[sio_data->type].name, 3214 data, data->groups); 3215 return PTR_ERR_OR_ZERO(hwmon_dev); 3216 } 3217 3218 static void it87_resume_sio(struct platform_device *pdev) 3219 { 3220 struct it87_data *data = dev_get_drvdata(&pdev->dev); 3221 int err; 3222 int reg2c; 3223 3224 if (!data->need_in7_reroute) 3225 return; 3226 3227 err = superio_enter(data->sioaddr); 3228 if (err) { 3229 dev_warn(&pdev->dev, 3230 "Unable to enter Super I/O to reroute in7 (%d)", 3231 err); 3232 return; 3233 } 3234 3235 superio_select(data->sioaddr, GPIO); 3236 3237 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG); 3238 if (!(reg2c & BIT(1))) { 3239 dev_dbg(&pdev->dev, 3240 "Routing internal VCCH5V to in7 again"); 3241 3242 reg2c |= BIT(1); 3243 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG, 3244 reg2c); 3245 } 3246 3247 superio_exit(data->sioaddr, has_conf_noexit(data)); 3248 } 3249 3250 static int it87_resume(struct device *dev) 3251 { 3252 struct platform_device *pdev = to_platform_device(dev); 3253 struct it87_data *data = dev_get_drvdata(dev); 3254 3255 it87_resume_sio(pdev); 3256 3257 mutex_lock(&data->update_lock); 3258 3259 it87_check_pwm(dev); 3260 it87_check_limit_regs(data); 3261 it87_check_voltage_monitors_reset(data); 3262 it87_check_tachometers_reset(pdev); 3263 it87_check_tachometers_16bit_mode(pdev); 3264 3265 it87_start_monitoring(data); 3266 3267 /* force update */ 3268 data->valid = false; 3269 3270 mutex_unlock(&data->update_lock); 3271 3272 it87_update_device(dev); 3273 3274 return 0; 3275 } 3276 3277 static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume); 3278 3279 static struct platform_driver it87_driver = { 3280 .driver = { 3281 .name = DRVNAME, 3282 .pm = pm_sleep_ptr(&it87_dev_pm_ops), 3283 }, 3284 .probe = it87_probe, 3285 }; 3286 3287 static int __init it87_device_add(int index, unsigned short address, 3288 const struct it87_sio_data *sio_data) 3289 { 3290 struct platform_device *pdev; 3291 struct resource res = { 3292 .start = address + IT87_EC_OFFSET, 3293 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, 3294 .name = DRVNAME, 3295 .flags = IORESOURCE_IO, 3296 }; 3297 int err; 3298 3299 err = acpi_check_resource_conflict(&res); 3300 if (err) { 3301 if (!ignore_resource_conflict) 3302 return err; 3303 } 3304 3305 pdev = platform_device_alloc(DRVNAME, address); 3306 if (!pdev) 3307 return -ENOMEM; 3308 3309 err = platform_device_add_resources(pdev, &res, 1); 3310 if (err) { 3311 pr_err("Device resource addition failed (%d)\n", err); 3312 goto exit_device_put; 3313 } 3314 3315 err = platform_device_add_data(pdev, sio_data, 3316 sizeof(struct it87_sio_data)); 3317 if (err) { 3318 pr_err("Platform data allocation failed\n"); 3319 goto exit_device_put; 3320 } 3321 3322 err = platform_device_add(pdev); 3323 if (err) { 3324 pr_err("Device addition failed (%d)\n", err); 3325 goto exit_device_put; 3326 } 3327 3328 it87_pdev[index] = pdev; 3329 return 0; 3330 3331 exit_device_put: 3332 platform_device_put(pdev); 3333 return err; 3334 } 3335 3336 /* callback function for DMI */ 3337 static int it87_dmi_cb(const struct dmi_system_id *dmi_entry) 3338 { 3339 dmi_data = dmi_entry->driver_data; 3340 3341 if (dmi_data && dmi_data->skip_pwm) 3342 pr_info("Disabling pwm2 due to hardware constraints\n"); 3343 3344 return 1; 3345 } 3346 3347 /* 3348 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip 3349 * (IT8792E) needs to be in configuration mode before accessing the first 3350 * due to a bug in IT8792E which otherwise results in LPC bus access errors. 3351 * This needs to be done before accessing the first Super-IO chip since 3352 * the second chip may have been accessed prior to loading this driver. 3353 * 3354 * The problem is also reported to affect IT8795E, which is used on X299 boards 3355 * and has the same chip ID as IT8792E (0x8733). It also appears to affect 3356 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as 3357 * Z87X-OC. 3358 * DMI entries for those systems will be added as they become available and 3359 * as the problem is confirmed to affect those boards. 3360 */ 3361 static int it87_sio_force(const struct dmi_system_id *dmi_entry) 3362 { 3363 __superio_enter(REG_4E); 3364 3365 return it87_dmi_cb(dmi_entry); 3366 }; 3367 3368 /* 3369 * On the Shuttle SN68PT, FAN_CTL2 is apparently not 3370 * connected to a fan, but to something else. One user 3371 * has reported instant system power-off when changing 3372 * the PWM2 duty cycle, so we disable it. 3373 * I use the board name string as the trigger in case 3374 * the same board is ever used in other systems. 3375 */ 3376 static struct it87_dmi_data nvidia_fn68pt = { 3377 .skip_pwm = BIT(1), 3378 }; 3379 3380 #define IT87_DMI_MATCH_VND(vendor, name, cb, data) \ 3381 { \ 3382 .callback = cb, \ 3383 .matches = { \ 3384 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \ 3385 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ 3386 }, \ 3387 .driver_data = data, \ 3388 } 3389 3390 #define IT87_DMI_MATCH_GBT(name, cb, data) \ 3391 IT87_DMI_MATCH_VND("Gigabyte Technology Co., Ltd.", name, cb, data) 3392 3393 static const struct dmi_system_id it87_dmi_table[] __initconst = { 3394 IT87_DMI_MATCH_GBT("AB350", it87_sio_force, NULL), 3395 /* ? + IT8792E/IT8795E */ 3396 IT87_DMI_MATCH_GBT("AX370", it87_sio_force, NULL), 3397 /* ? + IT8792E/IT8795E */ 3398 IT87_DMI_MATCH_GBT("Z97X-Gaming G1", it87_sio_force, NULL), 3399 /* ? + IT8790E */ 3400 IT87_DMI_MATCH_GBT("TRX40 AORUS XTREME", it87_sio_force, NULL), 3401 /* IT8688E + IT8792E/IT8795E */ 3402 IT87_DMI_MATCH_GBT("Z390 AORUS ULTRA-CF", it87_sio_force, NULL), 3403 /* IT8688E + IT8792E/IT8795E */ 3404 IT87_DMI_MATCH_GBT("B550 AORUS PRO AC", it87_sio_force, NULL), 3405 /* IT8688E + IT8792E/IT8795E */ 3406 IT87_DMI_MATCH_GBT("X570 AORUS MASTER", it87_sio_force, NULL), 3407 /* IT8688E + IT8792E/IT8795E */ 3408 IT87_DMI_MATCH_GBT("X570 AORUS PRO", it87_sio_force, NULL), 3409 /* IT8688E + IT8792E/IT8795E */ 3410 IT87_DMI_MATCH_GBT("X570 AORUS PRO WIFI", it87_sio_force, NULL), 3411 /* IT8688E + IT8792E/IT8795E */ 3412 IT87_DMI_MATCH_GBT("X570S AERO G", it87_sio_force, NULL), 3413 /* IT8689E + IT87952E */ 3414 IT87_DMI_MATCH_GBT("Z690 AORUS PRO DDR4", it87_sio_force, NULL), 3415 /* IT8689E + IT87952E */ 3416 IT87_DMI_MATCH_GBT("Z690 AORUS PRO", it87_sio_force, NULL), 3417 /* IT8689E + IT87952E */ 3418 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt), 3419 { } 3420 3421 }; 3422 MODULE_DEVICE_TABLE(dmi, it87_dmi_table); 3423 3424 static int __init sm_it87_init(void) 3425 { 3426 int sioaddr[2] = { REG_2E, REG_4E }; 3427 struct it87_sio_data sio_data; 3428 unsigned short isa_address[2]; 3429 bool found = false; 3430 int i, err; 3431 3432 err = platform_driver_register(&it87_driver); 3433 if (err) 3434 return err; 3435 3436 dmi_check_system(it87_dmi_table); 3437 3438 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { 3439 memset(&sio_data, 0, sizeof(struct it87_sio_data)); 3440 isa_address[i] = 0; 3441 err = it87_find(sioaddr[i], &isa_address[i], &sio_data, i); 3442 if (err || isa_address[i] == 0) 3443 continue; 3444 /* 3445 * Don't register second chip if its ISA address matches 3446 * the first chip's ISA address. 3447 */ 3448 if (i && isa_address[i] == isa_address[0]) 3449 break; 3450 3451 err = it87_device_add(i, isa_address[i], &sio_data); 3452 if (err) 3453 goto exit_dev_unregister; 3454 3455 found = true; 3456 3457 /* 3458 * IT8705F may respond on both SIO addresses. 3459 * Stop probing after finding one. 3460 */ 3461 if (sio_data.type == it87) 3462 break; 3463 } 3464 3465 if (!found) { 3466 err = -ENODEV; 3467 goto exit_unregister; 3468 } 3469 return 0; 3470 3471 exit_dev_unregister: 3472 /* NULL check handled by platform_device_unregister */ 3473 platform_device_unregister(it87_pdev[0]); 3474 exit_unregister: 3475 platform_driver_unregister(&it87_driver); 3476 return err; 3477 } 3478 3479 static void __exit sm_it87_exit(void) 3480 { 3481 /* NULL check handled by platform_device_unregister */ 3482 platform_device_unregister(it87_pdev[1]); 3483 platform_device_unregister(it87_pdev[0]); 3484 platform_driver_unregister(&it87_driver); 3485 } 3486 3487 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); 3488 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); 3489 3490 module_param_array(force_id, ushort, &force_id_cnt, 0); 3491 MODULE_PARM_DESC(force_id, "Override one or more detected device ID(s)"); 3492 3493 module_param(ignore_resource_conflict, bool, 0); 3494 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict"); 3495 3496 module_param(update_vbat, bool, 0); 3497 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); 3498 3499 module_param(fix_pwm_polarity, bool, 0); 3500 MODULE_PARM_DESC(fix_pwm_polarity, 3501 "Force PWM polarity to active high (DANGEROUS)"); 3502 3503 MODULE_LICENSE("GPL"); 3504 3505 module_init(sm_it87_init); 3506 module_exit(sm_it87_exit); 3507