1 /* 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027, 3 * and SCH5127 Super-I/O chips integrated hardware monitoring 4 * features. 5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com> 6 * 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very 10 * similar hardware monitoring capabilities but differ in the way they can be 11 * accessed. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/module.h> 31 #include <linux/init.h> 32 #include <linux/slab.h> 33 #include <linux/jiffies.h> 34 #include <linux/i2c.h> 35 #include <linux/platform_device.h> 36 #include <linux/hwmon.h> 37 #include <linux/hwmon-sysfs.h> 38 #include <linux/hwmon-vid.h> 39 #include <linux/err.h> 40 #include <linux/mutex.h> 41 #include <linux/acpi.h> 42 #include <linux/io.h> 43 44 /* ISA device, if found */ 45 static struct platform_device *pdev; 46 47 /* Module load parameters */ 48 static bool force_start; 49 module_param(force_start, bool, 0); 50 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs"); 51 52 static unsigned short force_id; 53 module_param(force_id, ushort, 0); 54 MODULE_PARM_DESC(force_id, "Override the detected device ID"); 55 56 static bool probe_all_addr; 57 module_param(probe_all_addr, bool, 0); 58 MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC " 59 "addresses"); 60 61 /* Addresses to scan */ 62 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; 63 64 enum chips { dme1737, sch5027, sch311x, sch5127 }; 65 66 /* --------------------------------------------------------------------- 67 * Registers 68 * 69 * The sensors are defined as follows: 70 * 71 * Voltages Temperatures 72 * -------- ------------ 73 * in0 +5VTR (+5V stdby) temp1 Remote diode 1 74 * in1 Vccp (proc core) temp2 Internal temp 75 * in2 VCC (internal +3.3V) temp3 Remote diode 2 76 * in3 +5V 77 * in4 +12V 78 * in5 VTR (+3.3V stby) 79 * in6 Vbat 80 * in7 Vtrip (sch5127 only) 81 * 82 * --------------------------------------------------------------------- */ 83 84 /* Voltages (in) numbered 0-7 (ix) */ 85 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ 86 (ix) < 7 ? 0x94 + (ix) : \ 87 0x1f) 88 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ 89 : 0x91 + (ix) * 2) 90 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ 91 : 0x92 + (ix) * 2) 92 93 /* Temperatures (temp) numbered 0-2 (ix) */ 94 #define DME1737_REG_TEMP(ix) (0x25 + (ix)) 95 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) 96 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) 97 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ 98 : 0x1c + (ix)) 99 100 /* 101 * Voltage and temperature LSBs 102 * The LSBs (4 bits each) are stored in 5 registers with the following layouts: 103 * IN_TEMP_LSB(0) = [in5, in6] 104 * IN_TEMP_LSB(1) = [temp3, temp1] 105 * IN_TEMP_LSB(2) = [in4, temp2] 106 * IN_TEMP_LSB(3) = [in3, in0] 107 * IN_TEMP_LSB(4) = [in2, in1] 108 * IN_TEMP_LSB(5) = [res, in7] 109 */ 110 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix)) 111 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5}; 112 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4}; 113 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1}; 114 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0}; 115 116 /* Fans numbered 0-5 (ix) */ 117 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \ 118 : 0xa1 + (ix) * 2) 119 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \ 120 : 0xa5 + (ix) * 2) 121 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \ 122 : 0xb2 + (ix)) 123 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */ 124 125 /* PWMs numbered 0-2, 4-5 (ix) */ 126 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \ 127 : 0xa1 + (ix)) 128 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */ 129 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */ 130 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \ 131 : 0xa3 + (ix)) 132 /* 133 * The layout of the ramp rate registers is different from the other pwm 134 * registers. The bits for the 3 PWMs are stored in 2 registers: 135 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0] 136 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] 137 */ 138 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */ 139 140 /* Thermal zones 0-2 */ 141 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix)) 142 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix)) 143 /* 144 * The layout of the hysteresis registers is different from the other zone 145 * registers. The bits for the 3 zones are stored in 2 registers: 146 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 147 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] 148 */ 149 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix)) 150 151 /* 152 * Alarm registers and bit mapping 153 * The 3 8-bit alarm registers will be concatenated to a single 32-bit 154 * alarm value [0, ALARM3, ALARM2, ALARM1]. 155 */ 156 #define DME1737_REG_ALARM1 0x41 157 #define DME1737_REG_ALARM2 0x42 158 #define DME1737_REG_ALARM3 0x83 159 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18}; 160 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6}; 161 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; 162 163 /* Miscellaneous registers */ 164 #define DME1737_REG_DEVICE 0x3d 165 #define DME1737_REG_COMPANY 0x3e 166 #define DME1737_REG_VERSTEP 0x3f 167 #define DME1737_REG_CONFIG 0x40 168 #define DME1737_REG_CONFIG2 0x7f 169 #define DME1737_REG_VID 0x43 170 #define DME1737_REG_TACH_PWM 0x81 171 172 /* --------------------------------------------------------------------- 173 * Misc defines 174 * --------------------------------------------------------------------- */ 175 176 /* Chip identification */ 177 #define DME1737_COMPANY_SMSC 0x5c 178 #define DME1737_VERSTEP 0x88 179 #define DME1737_VERSTEP_MASK 0xf8 180 #define SCH311X_DEVICE 0x8c 181 #define SCH5027_VERSTEP 0x69 182 #define SCH5127_DEVICE 0x8e 183 184 /* Device ID values (global configuration register index 0x20) */ 185 #define DME1737_ID_1 0x77 186 #define DME1737_ID_2 0x78 187 #define SCH3112_ID 0x7c 188 #define SCH3114_ID 0x7d 189 #define SCH3116_ID 0x7f 190 #define SCH5027_ID 0x89 191 #define SCH5127_ID 0x86 192 193 /* Length of ISA address segment */ 194 #define DME1737_EXTENT 2 195 196 /* chip-dependent features */ 197 #define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */ 198 #define HAS_VID (1 << 1) /* bit 1 */ 199 #define HAS_ZONE3 (1 << 2) /* bit 2 */ 200 #define HAS_ZONE_HYST (1 << 3) /* bit 3 */ 201 #define HAS_PWM_MIN (1 << 4) /* bit 4 */ 202 #define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */ 203 #define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */ 204 #define HAS_IN7 (1 << 17) /* bit 17 */ 205 206 /* --------------------------------------------------------------------- 207 * Data structures and manipulation thereof 208 * --------------------------------------------------------------------- */ 209 210 struct dme1737_data { 211 struct i2c_client *client; /* for I2C devices only */ 212 struct device *hwmon_dev; 213 const char *name; 214 unsigned int addr; /* for ISA devices only */ 215 216 struct mutex update_lock; 217 int valid; /* !=0 if following fields are valid */ 218 unsigned long last_update; /* in jiffies */ 219 unsigned long last_vbat; /* in jiffies */ 220 enum chips type; 221 const int *in_nominal; /* pointer to IN_NOMINAL array */ 222 223 u8 vid; 224 u8 pwm_rr_en; 225 u32 has_features; 226 227 /* Register values */ 228 u16 in[8]; 229 u8 in_min[8]; 230 u8 in_max[8]; 231 s16 temp[3]; 232 s8 temp_min[3]; 233 s8 temp_max[3]; 234 s8 temp_offset[3]; 235 u8 config; 236 u8 config2; 237 u8 vrm; 238 u16 fan[6]; 239 u16 fan_min[6]; 240 u8 fan_max[2]; 241 u8 fan_opt[6]; 242 u8 pwm[6]; 243 u8 pwm_min[3]; 244 u8 pwm_config[3]; 245 u8 pwm_acz[3]; 246 u8 pwm_freq[6]; 247 u8 pwm_rr[2]; 248 u8 zone_low[3]; 249 u8 zone_abs[3]; 250 u8 zone_hyst[2]; 251 u32 alarms; 252 }; 253 254 /* Nominal voltage values */ 255 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, 256 3300}; 257 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, 258 3300}; 259 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, 260 3300}; 261 static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300, 262 3300, 1500}; 263 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ 264 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ 265 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \ 266 IN_NOMINAL_DME1737) 267 268 /* 269 * Voltage input 270 * Voltage inputs have 16 bits resolution, limit values have 8 bits 271 * resolution. 272 */ 273 static inline int IN_FROM_REG(int reg, int nominal, int res) 274 { 275 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); 276 } 277 278 static inline int IN_TO_REG(int val, int nominal) 279 { 280 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); 281 } 282 283 /* 284 * Temperature input 285 * The register values represent temperatures in 2's complement notation from 286 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit 287 * values have 8 bits resolution. 288 */ 289 static inline int TEMP_FROM_REG(int reg, int res) 290 { 291 return (reg * 1000) >> (res - 8); 292 } 293 294 static inline int TEMP_TO_REG(int val) 295 { 296 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000, 297 -128, 127); 298 } 299 300 /* Temperature range */ 301 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000, 302 10000, 13333, 16000, 20000, 26666, 32000, 303 40000, 53333, 80000}; 304 305 static inline int TEMP_RANGE_FROM_REG(int reg) 306 { 307 return TEMP_RANGE[(reg >> 4) & 0x0f]; 308 } 309 310 static int TEMP_RANGE_TO_REG(int val, int reg) 311 { 312 int i; 313 314 for (i = 15; i > 0; i--) { 315 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) 316 break; 317 } 318 319 return (reg & 0x0f) | (i << 4); 320 } 321 322 /* 323 * Temperature hysteresis 324 * Register layout: 325 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 326 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] 327 */ 328 static inline int TEMP_HYST_FROM_REG(int reg, int ix) 329 { 330 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; 331 } 332 333 static inline int TEMP_HYST_TO_REG(int val, int ix, int reg) 334 { 335 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15); 336 337 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4); 338 } 339 340 /* Fan input RPM */ 341 static inline int FAN_FROM_REG(int reg, int tpc) 342 { 343 if (tpc) 344 return tpc * reg; 345 else 346 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; 347 } 348 349 static inline int FAN_TO_REG(int val, int tpc) 350 { 351 if (tpc) { 352 return SENSORS_LIMIT(val / tpc, 0, 0xffff); 353 } else { 354 return (val <= 0) ? 0xffff : 355 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe); 356 } 357 } 358 359 /* 360 * Fan TPC (tach pulse count) 361 * Converts a register value to a TPC multiplier or returns 0 if the tachometer 362 * is configured in legacy (non-tpc) mode 363 */ 364 static inline int FAN_TPC_FROM_REG(int reg) 365 { 366 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); 367 } 368 369 /* 370 * Fan type 371 * The type of a fan is expressed in number of pulses-per-revolution that it 372 * emits 373 */ 374 static inline int FAN_TYPE_FROM_REG(int reg) 375 { 376 int edge = (reg >> 1) & 0x03; 377 378 return (edge > 0) ? 1 << (edge - 1) : 0; 379 } 380 381 static inline int FAN_TYPE_TO_REG(int val, int reg) 382 { 383 int edge = (val == 4) ? 3 : val; 384 385 return (reg & 0xf9) | (edge << 1); 386 } 387 388 /* Fan max RPM */ 389 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12, 390 0x11, 0x0f, 0x0e}; 391 392 static int FAN_MAX_FROM_REG(int reg) 393 { 394 int i; 395 396 for (i = 10; i > 0; i--) { 397 if (reg == FAN_MAX[i]) 398 break; 399 } 400 401 return 1000 + i * 500; 402 } 403 404 static int FAN_MAX_TO_REG(int val) 405 { 406 int i; 407 408 for (i = 10; i > 0; i--) { 409 if (val > (1000 + (i - 1) * 500)) 410 break; 411 } 412 413 return FAN_MAX[i]; 414 } 415 416 /* 417 * PWM enable 418 * Register to enable mapping: 419 * 000: 2 fan on zone 1 auto 420 * 001: 2 fan on zone 2 auto 421 * 010: 2 fan on zone 3 auto 422 * 011: 0 fan full on 423 * 100: -1 fan disabled 424 * 101: 2 fan on hottest of zones 2,3 auto 425 * 110: 2 fan on hottest of zones 1,2,3 auto 426 * 111: 1 fan in manual mode 427 */ 428 static inline int PWM_EN_FROM_REG(int reg) 429 { 430 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1}; 431 432 return en[(reg >> 5) & 0x07]; 433 } 434 435 static inline int PWM_EN_TO_REG(int val, int reg) 436 { 437 int en = (val == 1) ? 7 : 3; 438 439 return (reg & 0x1f) | ((en & 0x07) << 5); 440 } 441 442 /* 443 * PWM auto channels zone 444 * Register to auto channels zone mapping (ACZ is a bitfield with bit x 445 * corresponding to zone x+1): 446 * 000: 001 fan on zone 1 auto 447 * 001: 010 fan on zone 2 auto 448 * 010: 100 fan on zone 3 auto 449 * 011: 000 fan full on 450 * 100: 000 fan disabled 451 * 101: 110 fan on hottest of zones 2,3 auto 452 * 110: 111 fan on hottest of zones 1,2,3 auto 453 * 111: 000 fan in manual mode 454 */ 455 static inline int PWM_ACZ_FROM_REG(int reg) 456 { 457 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0}; 458 459 return acz[(reg >> 5) & 0x07]; 460 } 461 462 static inline int PWM_ACZ_TO_REG(int val, int reg) 463 { 464 int acz = (val == 4) ? 2 : val - 1; 465 466 return (reg & 0x1f) | ((acz & 0x07) << 5); 467 } 468 469 /* PWM frequency */ 470 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88, 471 15000, 20000, 30000, 25000, 0, 0, 0, 0}; 472 473 static inline int PWM_FREQ_FROM_REG(int reg) 474 { 475 return PWM_FREQ[reg & 0x0f]; 476 } 477 478 static int PWM_FREQ_TO_REG(int val, int reg) 479 { 480 int i; 481 482 /* the first two cases are special - stupid chip design! */ 483 if (val > 27500) { 484 i = 10; 485 } else if (val > 22500) { 486 i = 11; 487 } else { 488 for (i = 9; i > 0; i--) { 489 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) 490 break; 491 } 492 } 493 494 return (reg & 0xf0) | i; 495 } 496 497 /* 498 * PWM ramp rate 499 * Register layout: 500 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0] 501 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] 502 */ 503 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5}; 504 505 static inline int PWM_RR_FROM_REG(int reg, int ix) 506 { 507 int rr = (ix == 1) ? reg >> 4 : reg; 508 509 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0; 510 } 511 512 static int PWM_RR_TO_REG(int val, int ix, int reg) 513 { 514 int i; 515 516 for (i = 0; i < 7; i++) { 517 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) 518 break; 519 } 520 521 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; 522 } 523 524 /* PWM ramp rate enable */ 525 static inline int PWM_RR_EN_FROM_REG(int reg, int ix) 526 { 527 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0; 528 } 529 530 static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg) 531 { 532 int en = (ix == 1) ? 0x80 : 0x08; 533 534 return val ? reg | en : reg & ~en; 535 } 536 537 /* 538 * PWM min/off 539 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for 540 * the register layout). 541 */ 542 static inline int PWM_OFF_FROM_REG(int reg, int ix) 543 { 544 return (reg >> (ix + 5)) & 0x01; 545 } 546 547 static inline int PWM_OFF_TO_REG(int val, int ix, int reg) 548 { 549 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); 550 } 551 552 /* --------------------------------------------------------------------- 553 * Device I/O access 554 * 555 * ISA access is performed through an index/data register pair and needs to 556 * be protected by a mutex during runtime (not required for initialization). 557 * We use data->update_lock for this and need to ensure that we acquire it 558 * before calling dme1737_read or dme1737_write. 559 * --------------------------------------------------------------------- */ 560 561 static u8 dme1737_read(const struct dme1737_data *data, u8 reg) 562 { 563 struct i2c_client *client = data->client; 564 s32 val; 565 566 if (client) { /* I2C device */ 567 val = i2c_smbus_read_byte_data(client, reg); 568 569 if (val < 0) { 570 dev_warn(&client->dev, "Read from register " 571 "0x%02x failed! Please report to the driver " 572 "maintainer.\n", reg); 573 } 574 } else { /* ISA device */ 575 outb(reg, data->addr); 576 val = inb(data->addr + 1); 577 } 578 579 return val; 580 } 581 582 static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val) 583 { 584 struct i2c_client *client = data->client; 585 s32 res = 0; 586 587 if (client) { /* I2C device */ 588 res = i2c_smbus_write_byte_data(client, reg, val); 589 590 if (res < 0) { 591 dev_warn(&client->dev, "Write to register " 592 "0x%02x failed! Please report to the driver " 593 "maintainer.\n", reg); 594 } 595 } else { /* ISA device */ 596 outb(reg, data->addr); 597 outb(val, data->addr + 1); 598 } 599 600 return res; 601 } 602 603 static struct dme1737_data *dme1737_update_device(struct device *dev) 604 { 605 struct dme1737_data *data = dev_get_drvdata(dev); 606 int ix; 607 u8 lsb[6]; 608 609 mutex_lock(&data->update_lock); 610 611 /* Enable a Vbat monitoring cycle every 10 mins */ 612 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) { 613 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data, 614 DME1737_REG_CONFIG) | 0x10); 615 data->last_vbat = jiffies; 616 } 617 618 /* Sample register contents every 1 sec */ 619 if (time_after(jiffies, data->last_update + HZ) || !data->valid) { 620 if (data->has_features & HAS_VID) { 621 data->vid = dme1737_read(data, DME1737_REG_VID) & 622 0x3f; 623 } 624 625 /* In (voltage) registers */ 626 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 627 /* 628 * Voltage inputs are stored as 16 bit values even 629 * though they have only 12 bits resolution. This is 630 * to make it consistent with the temp inputs. 631 */ 632 if (ix == 7 && !(data->has_features & HAS_IN7)) 633 continue; 634 data->in[ix] = dme1737_read(data, 635 DME1737_REG_IN(ix)) << 8; 636 data->in_min[ix] = dme1737_read(data, 637 DME1737_REG_IN_MIN(ix)); 638 data->in_max[ix] = dme1737_read(data, 639 DME1737_REG_IN_MAX(ix)); 640 } 641 642 /* Temp registers */ 643 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 644 /* 645 * Temp inputs are stored as 16 bit values even 646 * though they have only 12 bits resolution. This is 647 * to take advantage of implicit conversions between 648 * register values (2's complement) and temp values 649 * (signed decimal). 650 */ 651 data->temp[ix] = dme1737_read(data, 652 DME1737_REG_TEMP(ix)) << 8; 653 data->temp_min[ix] = dme1737_read(data, 654 DME1737_REG_TEMP_MIN(ix)); 655 data->temp_max[ix] = dme1737_read(data, 656 DME1737_REG_TEMP_MAX(ix)); 657 if (data->has_features & HAS_TEMP_OFFSET) { 658 data->temp_offset[ix] = dme1737_read(data, 659 DME1737_REG_TEMP_OFFSET(ix)); 660 } 661 } 662 663 /* 664 * In and temp LSB registers 665 * The LSBs are latched when the MSBs are read, so the order in 666 * which the registers are read (MSB first, then LSB) is 667 * important! 668 */ 669 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { 670 if (ix == 5 && !(data->has_features & HAS_IN7)) 671 continue; 672 lsb[ix] = dme1737_read(data, 673 DME1737_REG_IN_TEMP_LSB(ix)); 674 } 675 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 676 if (ix == 7 && !(data->has_features & HAS_IN7)) 677 continue; 678 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] << 679 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0; 680 } 681 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 682 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] << 683 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0; 684 } 685 686 /* Fan registers */ 687 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { 688 /* 689 * Skip reading registers if optional fans are not 690 * present 691 */ 692 if (!(data->has_features & HAS_FAN(ix))) 693 continue; 694 data->fan[ix] = dme1737_read(data, 695 DME1737_REG_FAN(ix)); 696 data->fan[ix] |= dme1737_read(data, 697 DME1737_REG_FAN(ix) + 1) << 8; 698 data->fan_min[ix] = dme1737_read(data, 699 DME1737_REG_FAN_MIN(ix)); 700 data->fan_min[ix] |= dme1737_read(data, 701 DME1737_REG_FAN_MIN(ix) + 1) << 8; 702 data->fan_opt[ix] = dme1737_read(data, 703 DME1737_REG_FAN_OPT(ix)); 704 /* fan_max exists only for fan[5-6] */ 705 if (ix > 3) { 706 data->fan_max[ix - 4] = dme1737_read(data, 707 DME1737_REG_FAN_MAX(ix)); 708 } 709 } 710 711 /* PWM registers */ 712 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { 713 /* 714 * Skip reading registers if optional PWMs are not 715 * present 716 */ 717 if (!(data->has_features & HAS_PWM(ix))) 718 continue; 719 data->pwm[ix] = dme1737_read(data, 720 DME1737_REG_PWM(ix)); 721 data->pwm_freq[ix] = dme1737_read(data, 722 DME1737_REG_PWM_FREQ(ix)); 723 /* pwm_config and pwm_min exist only for pwm[1-3] */ 724 if (ix < 3) { 725 data->pwm_config[ix] = dme1737_read(data, 726 DME1737_REG_PWM_CONFIG(ix)); 727 data->pwm_min[ix] = dme1737_read(data, 728 DME1737_REG_PWM_MIN(ix)); 729 } 730 } 731 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) { 732 data->pwm_rr[ix] = dme1737_read(data, 733 DME1737_REG_PWM_RR(ix)); 734 } 735 736 /* Thermal zone registers */ 737 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) { 738 /* Skip reading registers if zone3 is not present */ 739 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) 740 continue; 741 /* sch5127 zone2 registers are special */ 742 if ((ix == 1) && (data->type == sch5127)) { 743 data->zone_low[1] = dme1737_read(data, 744 DME1737_REG_ZONE_LOW(2)); 745 data->zone_abs[1] = dme1737_read(data, 746 DME1737_REG_ZONE_ABS(2)); 747 } else { 748 data->zone_low[ix] = dme1737_read(data, 749 DME1737_REG_ZONE_LOW(ix)); 750 data->zone_abs[ix] = dme1737_read(data, 751 DME1737_REG_ZONE_ABS(ix)); 752 } 753 } 754 if (data->has_features & HAS_ZONE_HYST) { 755 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { 756 data->zone_hyst[ix] = dme1737_read(data, 757 DME1737_REG_ZONE_HYST(ix)); 758 } 759 } 760 761 /* Alarm registers */ 762 data->alarms = dme1737_read(data, 763 DME1737_REG_ALARM1); 764 /* 765 * Bit 7 tells us if the other alarm registers are non-zero and 766 * therefore also need to be read 767 */ 768 if (data->alarms & 0x80) { 769 data->alarms |= dme1737_read(data, 770 DME1737_REG_ALARM2) << 8; 771 data->alarms |= dme1737_read(data, 772 DME1737_REG_ALARM3) << 16; 773 } 774 775 /* 776 * The ISA chips require explicit clearing of alarm bits. 777 * Don't worry, an alarm will come back if the condition 778 * that causes it still exists 779 */ 780 if (!data->client) { 781 if (data->alarms & 0xff0000) 782 dme1737_write(data, DME1737_REG_ALARM3, 0xff); 783 if (data->alarms & 0xff00) 784 dme1737_write(data, DME1737_REG_ALARM2, 0xff); 785 if (data->alarms & 0xff) 786 dme1737_write(data, DME1737_REG_ALARM1, 0xff); 787 } 788 789 data->last_update = jiffies; 790 data->valid = 1; 791 } 792 793 mutex_unlock(&data->update_lock); 794 795 return data; 796 } 797 798 /* --------------------------------------------------------------------- 799 * Voltage sysfs attributes 800 * ix = [0-7] 801 * --------------------------------------------------------------------- */ 802 803 #define SYS_IN_INPUT 0 804 #define SYS_IN_MIN 1 805 #define SYS_IN_MAX 2 806 #define SYS_IN_ALARM 3 807 808 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 809 char *buf) 810 { 811 struct dme1737_data *data = dme1737_update_device(dev); 812 struct sensor_device_attribute_2 813 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 814 int ix = sensor_attr_2->index; 815 int fn = sensor_attr_2->nr; 816 int res; 817 818 switch (fn) { 819 case SYS_IN_INPUT: 820 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); 821 break; 822 case SYS_IN_MIN: 823 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); 824 break; 825 case SYS_IN_MAX: 826 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); 827 break; 828 case SYS_IN_ALARM: 829 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; 830 break; 831 default: 832 res = 0; 833 dev_dbg(dev, "Unknown function %d.\n", fn); 834 } 835 836 return sprintf(buf, "%d\n", res); 837 } 838 839 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 840 const char *buf, size_t count) 841 { 842 struct dme1737_data *data = dev_get_drvdata(dev); 843 struct sensor_device_attribute_2 844 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 845 int ix = sensor_attr_2->index; 846 int fn = sensor_attr_2->nr; 847 long val; 848 int err; 849 850 err = kstrtol(buf, 10, &val); 851 if (err) 852 return err; 853 854 mutex_lock(&data->update_lock); 855 switch (fn) { 856 case SYS_IN_MIN: 857 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); 858 dme1737_write(data, DME1737_REG_IN_MIN(ix), 859 data->in_min[ix]); 860 break; 861 case SYS_IN_MAX: 862 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); 863 dme1737_write(data, DME1737_REG_IN_MAX(ix), 864 data->in_max[ix]); 865 break; 866 default: 867 dev_dbg(dev, "Unknown function %d.\n", fn); 868 } 869 mutex_unlock(&data->update_lock); 870 871 return count; 872 } 873 874 /* --------------------------------------------------------------------- 875 * Temperature sysfs attributes 876 * ix = [0-2] 877 * --------------------------------------------------------------------- */ 878 879 #define SYS_TEMP_INPUT 0 880 #define SYS_TEMP_MIN 1 881 #define SYS_TEMP_MAX 2 882 #define SYS_TEMP_OFFSET 3 883 #define SYS_TEMP_ALARM 4 884 #define SYS_TEMP_FAULT 5 885 886 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 887 char *buf) 888 { 889 struct dme1737_data *data = dme1737_update_device(dev); 890 struct sensor_device_attribute_2 891 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 892 int ix = sensor_attr_2->index; 893 int fn = sensor_attr_2->nr; 894 int res; 895 896 switch (fn) { 897 case SYS_TEMP_INPUT: 898 res = TEMP_FROM_REG(data->temp[ix], 16); 899 break; 900 case SYS_TEMP_MIN: 901 res = TEMP_FROM_REG(data->temp_min[ix], 8); 902 break; 903 case SYS_TEMP_MAX: 904 res = TEMP_FROM_REG(data->temp_max[ix], 8); 905 break; 906 case SYS_TEMP_OFFSET: 907 res = TEMP_FROM_REG(data->temp_offset[ix], 8); 908 break; 909 case SYS_TEMP_ALARM: 910 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01; 911 break; 912 case SYS_TEMP_FAULT: 913 res = (((u16)data->temp[ix] & 0xff00) == 0x8000); 914 break; 915 default: 916 res = 0; 917 dev_dbg(dev, "Unknown function %d.\n", fn); 918 } 919 920 return sprintf(buf, "%d\n", res); 921 } 922 923 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 924 const char *buf, size_t count) 925 { 926 struct dme1737_data *data = dev_get_drvdata(dev); 927 struct sensor_device_attribute_2 928 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 929 int ix = sensor_attr_2->index; 930 int fn = sensor_attr_2->nr; 931 long val; 932 int err; 933 934 err = kstrtol(buf, 10, &val); 935 if (err) 936 return err; 937 938 mutex_lock(&data->update_lock); 939 switch (fn) { 940 case SYS_TEMP_MIN: 941 data->temp_min[ix] = TEMP_TO_REG(val); 942 dme1737_write(data, DME1737_REG_TEMP_MIN(ix), 943 data->temp_min[ix]); 944 break; 945 case SYS_TEMP_MAX: 946 data->temp_max[ix] = TEMP_TO_REG(val); 947 dme1737_write(data, DME1737_REG_TEMP_MAX(ix), 948 data->temp_max[ix]); 949 break; 950 case SYS_TEMP_OFFSET: 951 data->temp_offset[ix] = TEMP_TO_REG(val); 952 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix), 953 data->temp_offset[ix]); 954 break; 955 default: 956 dev_dbg(dev, "Unknown function %d.\n", fn); 957 } 958 mutex_unlock(&data->update_lock); 959 960 return count; 961 } 962 963 /* --------------------------------------------------------------------- 964 * Zone sysfs attributes 965 * ix = [0-2] 966 * --------------------------------------------------------------------- */ 967 968 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0 969 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1 970 #define SYS_ZONE_AUTO_POINT1_TEMP 2 971 #define SYS_ZONE_AUTO_POINT2_TEMP 3 972 #define SYS_ZONE_AUTO_POINT3_TEMP 4 973 974 static ssize_t show_zone(struct device *dev, struct device_attribute *attr, 975 char *buf) 976 { 977 struct dme1737_data *data = dme1737_update_device(dev); 978 struct sensor_device_attribute_2 979 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 980 int ix = sensor_attr_2->index; 981 int fn = sensor_attr_2->nr; 982 int res; 983 984 switch (fn) { 985 case SYS_ZONE_AUTO_CHANNELS_TEMP: 986 /* check config2 for non-standard temp-to-zone mapping */ 987 if ((ix == 1) && (data->config2 & 0x02)) 988 res = 4; 989 else 990 res = 1 << ix; 991 break; 992 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 993 res = TEMP_FROM_REG(data->zone_low[ix], 8) - 994 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix); 995 break; 996 case SYS_ZONE_AUTO_POINT1_TEMP: 997 res = TEMP_FROM_REG(data->zone_low[ix], 8); 998 break; 999 case SYS_ZONE_AUTO_POINT2_TEMP: 1000 /* pwm_freq holds the temp range bits in the upper nibble */ 1001 res = TEMP_FROM_REG(data->zone_low[ix], 8) + 1002 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]); 1003 break; 1004 case SYS_ZONE_AUTO_POINT3_TEMP: 1005 res = TEMP_FROM_REG(data->zone_abs[ix], 8); 1006 break; 1007 default: 1008 res = 0; 1009 dev_dbg(dev, "Unknown function %d.\n", fn); 1010 } 1011 1012 return sprintf(buf, "%d\n", res); 1013 } 1014 1015 static ssize_t set_zone(struct device *dev, struct device_attribute *attr, 1016 const char *buf, size_t count) 1017 { 1018 struct dme1737_data *data = dev_get_drvdata(dev); 1019 struct sensor_device_attribute_2 1020 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1021 int ix = sensor_attr_2->index; 1022 int fn = sensor_attr_2->nr; 1023 long val; 1024 int err; 1025 1026 err = kstrtol(buf, 10, &val); 1027 if (err) 1028 return err; 1029 1030 mutex_lock(&data->update_lock); 1031 switch (fn) { 1032 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 1033 /* Refresh the cache */ 1034 data->zone_low[ix] = dme1737_read(data, 1035 DME1737_REG_ZONE_LOW(ix)); 1036 /* Modify the temp hyst value */ 1037 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG( 1038 TEMP_FROM_REG(data->zone_low[ix], 8) - 1039 val, ix, dme1737_read(data, 1040 DME1737_REG_ZONE_HYST(ix == 2))); 1041 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2), 1042 data->zone_hyst[ix == 2]); 1043 break; 1044 case SYS_ZONE_AUTO_POINT1_TEMP: 1045 data->zone_low[ix] = TEMP_TO_REG(val); 1046 dme1737_write(data, DME1737_REG_ZONE_LOW(ix), 1047 data->zone_low[ix]); 1048 break; 1049 case SYS_ZONE_AUTO_POINT2_TEMP: 1050 /* Refresh the cache */ 1051 data->zone_low[ix] = dme1737_read(data, 1052 DME1737_REG_ZONE_LOW(ix)); 1053 /* 1054 * Modify the temp range value (which is stored in the upper 1055 * nibble of the pwm_freq register) 1056 */ 1057 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - 1058 TEMP_FROM_REG(data->zone_low[ix], 8), 1059 dme1737_read(data, 1060 DME1737_REG_PWM_FREQ(ix))); 1061 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1062 data->pwm_freq[ix]); 1063 break; 1064 case SYS_ZONE_AUTO_POINT3_TEMP: 1065 data->zone_abs[ix] = TEMP_TO_REG(val); 1066 dme1737_write(data, DME1737_REG_ZONE_ABS(ix), 1067 data->zone_abs[ix]); 1068 break; 1069 default: 1070 dev_dbg(dev, "Unknown function %d.\n", fn); 1071 } 1072 mutex_unlock(&data->update_lock); 1073 1074 return count; 1075 } 1076 1077 /* --------------------------------------------------------------------- 1078 * Fan sysfs attributes 1079 * ix = [0-5] 1080 * --------------------------------------------------------------------- */ 1081 1082 #define SYS_FAN_INPUT 0 1083 #define SYS_FAN_MIN 1 1084 #define SYS_FAN_MAX 2 1085 #define SYS_FAN_ALARM 3 1086 #define SYS_FAN_TYPE 4 1087 1088 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1089 char *buf) 1090 { 1091 struct dme1737_data *data = dme1737_update_device(dev); 1092 struct sensor_device_attribute_2 1093 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1094 int ix = sensor_attr_2->index; 1095 int fn = sensor_attr_2->nr; 1096 int res; 1097 1098 switch (fn) { 1099 case SYS_FAN_INPUT: 1100 res = FAN_FROM_REG(data->fan[ix], 1101 ix < 4 ? 0 : 1102 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1103 break; 1104 case SYS_FAN_MIN: 1105 res = FAN_FROM_REG(data->fan_min[ix], 1106 ix < 4 ? 0 : 1107 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1108 break; 1109 case SYS_FAN_MAX: 1110 /* only valid for fan[5-6] */ 1111 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]); 1112 break; 1113 case SYS_FAN_ALARM: 1114 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01; 1115 break; 1116 case SYS_FAN_TYPE: 1117 /* only valid for fan[1-4] */ 1118 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]); 1119 break; 1120 default: 1121 res = 0; 1122 dev_dbg(dev, "Unknown function %d.\n", fn); 1123 } 1124 1125 return sprintf(buf, "%d\n", res); 1126 } 1127 1128 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1129 const char *buf, size_t count) 1130 { 1131 struct dme1737_data *data = dev_get_drvdata(dev); 1132 struct sensor_device_attribute_2 1133 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1134 int ix = sensor_attr_2->index; 1135 int fn = sensor_attr_2->nr; 1136 long val; 1137 int err; 1138 1139 err = kstrtol(buf, 10, &val); 1140 if (err) 1141 return err; 1142 1143 mutex_lock(&data->update_lock); 1144 switch (fn) { 1145 case SYS_FAN_MIN: 1146 if (ix < 4) { 1147 data->fan_min[ix] = FAN_TO_REG(val, 0); 1148 } else { 1149 /* Refresh the cache */ 1150 data->fan_opt[ix] = dme1737_read(data, 1151 DME1737_REG_FAN_OPT(ix)); 1152 /* Modify the fan min value */ 1153 data->fan_min[ix] = FAN_TO_REG(val, 1154 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1155 } 1156 dme1737_write(data, DME1737_REG_FAN_MIN(ix), 1157 data->fan_min[ix] & 0xff); 1158 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1, 1159 data->fan_min[ix] >> 8); 1160 break; 1161 case SYS_FAN_MAX: 1162 /* Only valid for fan[5-6] */ 1163 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val); 1164 dme1737_write(data, DME1737_REG_FAN_MAX(ix), 1165 data->fan_max[ix - 4]); 1166 break; 1167 case SYS_FAN_TYPE: 1168 /* Only valid for fan[1-4] */ 1169 if (!(val == 1 || val == 2 || val == 4)) { 1170 count = -EINVAL; 1171 dev_warn(dev, "Fan type value %ld not " 1172 "supported. Choose one of 1, 2, or 4.\n", 1173 val); 1174 goto exit; 1175 } 1176 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data, 1177 DME1737_REG_FAN_OPT(ix))); 1178 dme1737_write(data, DME1737_REG_FAN_OPT(ix), 1179 data->fan_opt[ix]); 1180 break; 1181 default: 1182 dev_dbg(dev, "Unknown function %d.\n", fn); 1183 } 1184 exit: 1185 mutex_unlock(&data->update_lock); 1186 1187 return count; 1188 } 1189 1190 /* --------------------------------------------------------------------- 1191 * PWM sysfs attributes 1192 * ix = [0-4] 1193 * --------------------------------------------------------------------- */ 1194 1195 #define SYS_PWM 0 1196 #define SYS_PWM_FREQ 1 1197 #define SYS_PWM_ENABLE 2 1198 #define SYS_PWM_RAMP_RATE 3 1199 #define SYS_PWM_AUTO_CHANNELS_ZONE 4 1200 #define SYS_PWM_AUTO_PWM_MIN 5 1201 #define SYS_PWM_AUTO_POINT1_PWM 6 1202 #define SYS_PWM_AUTO_POINT2_PWM 7 1203 1204 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1205 char *buf) 1206 { 1207 struct dme1737_data *data = dme1737_update_device(dev); 1208 struct sensor_device_attribute_2 1209 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1210 int ix = sensor_attr_2->index; 1211 int fn = sensor_attr_2->nr; 1212 int res; 1213 1214 switch (fn) { 1215 case SYS_PWM: 1216 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) 1217 res = 255; 1218 else 1219 res = data->pwm[ix]; 1220 break; 1221 case SYS_PWM_FREQ: 1222 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]); 1223 break; 1224 case SYS_PWM_ENABLE: 1225 if (ix >= 3) 1226 res = 1; /* pwm[5-6] hard-wired to manual mode */ 1227 else 1228 res = PWM_EN_FROM_REG(data->pwm_config[ix]); 1229 break; 1230 case SYS_PWM_RAMP_RATE: 1231 /* Only valid for pwm[1-3] */ 1232 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix); 1233 break; 1234 case SYS_PWM_AUTO_CHANNELS_ZONE: 1235 /* Only valid for pwm[1-3] */ 1236 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) 1237 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]); 1238 else 1239 res = data->pwm_acz[ix]; 1240 break; 1241 case SYS_PWM_AUTO_PWM_MIN: 1242 /* Only valid for pwm[1-3] */ 1243 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) 1244 res = data->pwm_min[ix]; 1245 else 1246 res = 0; 1247 break; 1248 case SYS_PWM_AUTO_POINT1_PWM: 1249 /* Only valid for pwm[1-3] */ 1250 res = data->pwm_min[ix]; 1251 break; 1252 case SYS_PWM_AUTO_POINT2_PWM: 1253 /* Only valid for pwm[1-3] */ 1254 res = 255; /* hard-wired */ 1255 break; 1256 default: 1257 res = 0; 1258 dev_dbg(dev, "Unknown function %d.\n", fn); 1259 } 1260 1261 return sprintf(buf, "%d\n", res); 1262 } 1263 1264 static struct attribute *dme1737_pwm_chmod_attr[]; 1265 static void dme1737_chmod_file(struct device*, struct attribute*, umode_t); 1266 1267 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1268 const char *buf, size_t count) 1269 { 1270 struct dme1737_data *data = dev_get_drvdata(dev); 1271 struct sensor_device_attribute_2 1272 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1273 int ix = sensor_attr_2->index; 1274 int fn = sensor_attr_2->nr; 1275 long val; 1276 int err; 1277 1278 err = kstrtol(buf, 10, &val); 1279 if (err) 1280 return err; 1281 1282 mutex_lock(&data->update_lock); 1283 switch (fn) { 1284 case SYS_PWM: 1285 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255); 1286 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]); 1287 break; 1288 case SYS_PWM_FREQ: 1289 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data, 1290 DME1737_REG_PWM_FREQ(ix))); 1291 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1292 data->pwm_freq[ix]); 1293 break; 1294 case SYS_PWM_ENABLE: 1295 /* Only valid for pwm[1-3] */ 1296 if (val < 0 || val > 2) { 1297 count = -EINVAL; 1298 dev_warn(dev, "PWM enable %ld not " 1299 "supported. Choose one of 0, 1, or 2.\n", 1300 val); 1301 goto exit; 1302 } 1303 /* Refresh the cache */ 1304 data->pwm_config[ix] = dme1737_read(data, 1305 DME1737_REG_PWM_CONFIG(ix)); 1306 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) { 1307 /* Bail out if no change */ 1308 goto exit; 1309 } 1310 /* Do some housekeeping if we are currently in auto mode */ 1311 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1312 /* Save the current zone channel assignment */ 1313 data->pwm_acz[ix] = PWM_ACZ_FROM_REG( 1314 data->pwm_config[ix]); 1315 /* Save the current ramp rate state and disable it */ 1316 data->pwm_rr[ix > 0] = dme1737_read(data, 1317 DME1737_REG_PWM_RR(ix > 0)); 1318 data->pwm_rr_en &= ~(1 << ix); 1319 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) { 1320 data->pwm_rr_en |= (1 << ix); 1321 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix, 1322 data->pwm_rr[ix > 0]); 1323 dme1737_write(data, 1324 DME1737_REG_PWM_RR(ix > 0), 1325 data->pwm_rr[ix > 0]); 1326 } 1327 } 1328 /* Set the new PWM mode */ 1329 switch (val) { 1330 case 0: 1331 /* Change permissions of pwm[ix] to read-only */ 1332 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1333 S_IRUGO); 1334 /* Turn fan fully on */ 1335 data->pwm_config[ix] = PWM_EN_TO_REG(0, 1336 data->pwm_config[ix]); 1337 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1338 data->pwm_config[ix]); 1339 break; 1340 case 1: 1341 /* Turn on manual mode */ 1342 data->pwm_config[ix] = PWM_EN_TO_REG(1, 1343 data->pwm_config[ix]); 1344 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1345 data->pwm_config[ix]); 1346 /* Change permissions of pwm[ix] to read-writeable */ 1347 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1348 S_IRUGO | S_IWUSR); 1349 break; 1350 case 2: 1351 /* Change permissions of pwm[ix] to read-only */ 1352 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1353 S_IRUGO); 1354 /* 1355 * Turn on auto mode using the saved zone channel 1356 * assignment 1357 */ 1358 data->pwm_config[ix] = PWM_ACZ_TO_REG( 1359 data->pwm_acz[ix], 1360 data->pwm_config[ix]); 1361 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1362 data->pwm_config[ix]); 1363 /* Enable PWM ramp rate if previously enabled */ 1364 if (data->pwm_rr_en & (1 << ix)) { 1365 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix, 1366 dme1737_read(data, 1367 DME1737_REG_PWM_RR(ix > 0))); 1368 dme1737_write(data, 1369 DME1737_REG_PWM_RR(ix > 0), 1370 data->pwm_rr[ix > 0]); 1371 } 1372 break; 1373 } 1374 break; 1375 case SYS_PWM_RAMP_RATE: 1376 /* Only valid for pwm[1-3] */ 1377 /* Refresh the cache */ 1378 data->pwm_config[ix] = dme1737_read(data, 1379 DME1737_REG_PWM_CONFIG(ix)); 1380 data->pwm_rr[ix > 0] = dme1737_read(data, 1381 DME1737_REG_PWM_RR(ix > 0)); 1382 /* Set the ramp rate value */ 1383 if (val > 0) { 1384 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, 1385 data->pwm_rr[ix > 0]); 1386 } 1387 /* 1388 * Enable/disable the feature only if the associated PWM 1389 * output is in automatic mode. 1390 */ 1391 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1392 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, 1393 data->pwm_rr[ix > 0]); 1394 } 1395 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0), 1396 data->pwm_rr[ix > 0]); 1397 break; 1398 case SYS_PWM_AUTO_CHANNELS_ZONE: 1399 /* Only valid for pwm[1-3] */ 1400 if (!(val == 1 || val == 2 || val == 4 || 1401 val == 6 || val == 7)) { 1402 count = -EINVAL; 1403 dev_warn(dev, "PWM auto channels zone %ld " 1404 "not supported. Choose one of 1, 2, 4, 6, " 1405 "or 7.\n", val); 1406 goto exit; 1407 } 1408 /* Refresh the cache */ 1409 data->pwm_config[ix] = dme1737_read(data, 1410 DME1737_REG_PWM_CONFIG(ix)); 1411 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1412 /* 1413 * PWM is already in auto mode so update the temp 1414 * channel assignment 1415 */ 1416 data->pwm_config[ix] = PWM_ACZ_TO_REG(val, 1417 data->pwm_config[ix]); 1418 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1419 data->pwm_config[ix]); 1420 } else { 1421 /* 1422 * PWM is not in auto mode so we save the temp 1423 * channel assignment for later use 1424 */ 1425 data->pwm_acz[ix] = val; 1426 } 1427 break; 1428 case SYS_PWM_AUTO_PWM_MIN: 1429 /* Only valid for pwm[1-3] */ 1430 /* Refresh the cache */ 1431 data->pwm_min[ix] = dme1737_read(data, 1432 DME1737_REG_PWM_MIN(ix)); 1433 /* 1434 * There are only 2 values supported for the auto_pwm_min 1435 * value: 0 or auto_point1_pwm. So if the temperature drops 1436 * below the auto_point1_temp_hyst value, the fan either turns 1437 * off or runs at auto_point1_pwm duty-cycle. 1438 */ 1439 if (val > ((data->pwm_min[ix] + 1) / 2)) { 1440 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix, 1441 dme1737_read(data, 1442 DME1737_REG_PWM_RR(0))); 1443 } else { 1444 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix, 1445 dme1737_read(data, 1446 DME1737_REG_PWM_RR(0))); 1447 } 1448 dme1737_write(data, DME1737_REG_PWM_RR(0), 1449 data->pwm_rr[0]); 1450 break; 1451 case SYS_PWM_AUTO_POINT1_PWM: 1452 /* Only valid for pwm[1-3] */ 1453 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255); 1454 dme1737_write(data, DME1737_REG_PWM_MIN(ix), 1455 data->pwm_min[ix]); 1456 break; 1457 default: 1458 dev_dbg(dev, "Unknown function %d.\n", fn); 1459 } 1460 exit: 1461 mutex_unlock(&data->update_lock); 1462 1463 return count; 1464 } 1465 1466 /* --------------------------------------------------------------------- 1467 * Miscellaneous sysfs attributes 1468 * --------------------------------------------------------------------- */ 1469 1470 static ssize_t show_vrm(struct device *dev, struct device_attribute *attr, 1471 char *buf) 1472 { 1473 struct i2c_client *client = to_i2c_client(dev); 1474 struct dme1737_data *data = i2c_get_clientdata(client); 1475 1476 return sprintf(buf, "%d\n", data->vrm); 1477 } 1478 1479 static ssize_t set_vrm(struct device *dev, struct device_attribute *attr, 1480 const char *buf, size_t count) 1481 { 1482 struct dme1737_data *data = dev_get_drvdata(dev); 1483 long val; 1484 int err; 1485 1486 err = kstrtol(buf, 10, &val); 1487 if (err) 1488 return err; 1489 1490 data->vrm = val; 1491 return count; 1492 } 1493 1494 static ssize_t show_vid(struct device *dev, struct device_attribute *attr, 1495 char *buf) 1496 { 1497 struct dme1737_data *data = dme1737_update_device(dev); 1498 1499 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); 1500 } 1501 1502 static ssize_t show_name(struct device *dev, struct device_attribute *attr, 1503 char *buf) 1504 { 1505 struct dme1737_data *data = dev_get_drvdata(dev); 1506 1507 return sprintf(buf, "%s\n", data->name); 1508 } 1509 1510 /* --------------------------------------------------------------------- 1511 * Sysfs device attribute defines and structs 1512 * --------------------------------------------------------------------- */ 1513 1514 /* Voltages 0-7 */ 1515 1516 #define SENSOR_DEVICE_ATTR_IN(ix) \ 1517 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \ 1518 show_in, NULL, SYS_IN_INPUT, ix); \ 1519 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \ 1520 show_in, set_in, SYS_IN_MIN, ix); \ 1521 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \ 1522 show_in, set_in, SYS_IN_MAX, ix); \ 1523 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \ 1524 show_in, NULL, SYS_IN_ALARM, ix) 1525 1526 SENSOR_DEVICE_ATTR_IN(0); 1527 SENSOR_DEVICE_ATTR_IN(1); 1528 SENSOR_DEVICE_ATTR_IN(2); 1529 SENSOR_DEVICE_ATTR_IN(3); 1530 SENSOR_DEVICE_ATTR_IN(4); 1531 SENSOR_DEVICE_ATTR_IN(5); 1532 SENSOR_DEVICE_ATTR_IN(6); 1533 SENSOR_DEVICE_ATTR_IN(7); 1534 1535 /* Temperatures 1-3 */ 1536 1537 #define SENSOR_DEVICE_ATTR_TEMP(ix) \ 1538 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \ 1539 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \ 1540 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \ 1541 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \ 1542 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \ 1543 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \ 1544 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \ 1545 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \ 1546 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \ 1547 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \ 1548 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \ 1549 show_temp, NULL, SYS_TEMP_FAULT, ix-1) 1550 1551 SENSOR_DEVICE_ATTR_TEMP(1); 1552 SENSOR_DEVICE_ATTR_TEMP(2); 1553 SENSOR_DEVICE_ATTR_TEMP(3); 1554 1555 /* Zones 1-3 */ 1556 1557 #define SENSOR_DEVICE_ATTR_ZONE(ix) \ 1558 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \ 1559 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \ 1560 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \ 1561 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \ 1562 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \ 1563 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \ 1564 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \ 1565 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \ 1566 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \ 1567 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1) 1568 1569 SENSOR_DEVICE_ATTR_ZONE(1); 1570 SENSOR_DEVICE_ATTR_ZONE(2); 1571 SENSOR_DEVICE_ATTR_ZONE(3); 1572 1573 /* Fans 1-4 */ 1574 1575 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \ 1576 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1577 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1578 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1579 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1580 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1581 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1582 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \ 1583 show_fan, set_fan, SYS_FAN_TYPE, ix-1) 1584 1585 SENSOR_DEVICE_ATTR_FAN_1TO4(1); 1586 SENSOR_DEVICE_ATTR_FAN_1TO4(2); 1587 SENSOR_DEVICE_ATTR_FAN_1TO4(3); 1588 SENSOR_DEVICE_ATTR_FAN_1TO4(4); 1589 1590 /* Fans 5-6 */ 1591 1592 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \ 1593 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1594 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1595 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1596 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1597 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1598 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1599 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \ 1600 show_fan, set_fan, SYS_FAN_MAX, ix-1) 1601 1602 SENSOR_DEVICE_ATTR_FAN_5TO6(5); 1603 SENSOR_DEVICE_ATTR_FAN_5TO6(6); 1604 1605 /* PWMs 1-3 */ 1606 1607 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \ 1608 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1609 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1610 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1611 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1612 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1613 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \ 1614 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \ 1615 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \ 1616 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \ 1617 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \ 1618 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \ 1619 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \ 1620 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \ 1621 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \ 1622 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \ 1623 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1) 1624 1625 SENSOR_DEVICE_ATTR_PWM_1TO3(1); 1626 SENSOR_DEVICE_ATTR_PWM_1TO3(2); 1627 SENSOR_DEVICE_ATTR_PWM_1TO3(3); 1628 1629 /* PWMs 5-6 */ 1630 1631 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \ 1632 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1633 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1634 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1635 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1636 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1637 show_pwm, NULL, SYS_PWM_ENABLE, ix-1) 1638 1639 SENSOR_DEVICE_ATTR_PWM_5TO6(5); 1640 SENSOR_DEVICE_ATTR_PWM_5TO6(6); 1641 1642 /* Misc */ 1643 1644 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm); 1645 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); 1646 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */ 1647 1648 /* 1649 * This struct holds all the attributes that are always present and need to be 1650 * created unconditionally. The attributes that need modification of their 1651 * permissions are created read-only and write permissions are added or removed 1652 * on the fly when required 1653 */ 1654 static struct attribute *dme1737_attr[] = { 1655 /* Voltages */ 1656 &sensor_dev_attr_in0_input.dev_attr.attr, 1657 &sensor_dev_attr_in0_min.dev_attr.attr, 1658 &sensor_dev_attr_in0_max.dev_attr.attr, 1659 &sensor_dev_attr_in0_alarm.dev_attr.attr, 1660 &sensor_dev_attr_in1_input.dev_attr.attr, 1661 &sensor_dev_attr_in1_min.dev_attr.attr, 1662 &sensor_dev_attr_in1_max.dev_attr.attr, 1663 &sensor_dev_attr_in1_alarm.dev_attr.attr, 1664 &sensor_dev_attr_in2_input.dev_attr.attr, 1665 &sensor_dev_attr_in2_min.dev_attr.attr, 1666 &sensor_dev_attr_in2_max.dev_attr.attr, 1667 &sensor_dev_attr_in2_alarm.dev_attr.attr, 1668 &sensor_dev_attr_in3_input.dev_attr.attr, 1669 &sensor_dev_attr_in3_min.dev_attr.attr, 1670 &sensor_dev_attr_in3_max.dev_attr.attr, 1671 &sensor_dev_attr_in3_alarm.dev_attr.attr, 1672 &sensor_dev_attr_in4_input.dev_attr.attr, 1673 &sensor_dev_attr_in4_min.dev_attr.attr, 1674 &sensor_dev_attr_in4_max.dev_attr.attr, 1675 &sensor_dev_attr_in4_alarm.dev_attr.attr, 1676 &sensor_dev_attr_in5_input.dev_attr.attr, 1677 &sensor_dev_attr_in5_min.dev_attr.attr, 1678 &sensor_dev_attr_in5_max.dev_attr.attr, 1679 &sensor_dev_attr_in5_alarm.dev_attr.attr, 1680 &sensor_dev_attr_in6_input.dev_attr.attr, 1681 &sensor_dev_attr_in6_min.dev_attr.attr, 1682 &sensor_dev_attr_in6_max.dev_attr.attr, 1683 &sensor_dev_attr_in6_alarm.dev_attr.attr, 1684 /* Temperatures */ 1685 &sensor_dev_attr_temp1_input.dev_attr.attr, 1686 &sensor_dev_attr_temp1_min.dev_attr.attr, 1687 &sensor_dev_attr_temp1_max.dev_attr.attr, 1688 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 1689 &sensor_dev_attr_temp1_fault.dev_attr.attr, 1690 &sensor_dev_attr_temp2_input.dev_attr.attr, 1691 &sensor_dev_attr_temp2_min.dev_attr.attr, 1692 &sensor_dev_attr_temp2_max.dev_attr.attr, 1693 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 1694 &sensor_dev_attr_temp2_fault.dev_attr.attr, 1695 &sensor_dev_attr_temp3_input.dev_attr.attr, 1696 &sensor_dev_attr_temp3_min.dev_attr.attr, 1697 &sensor_dev_attr_temp3_max.dev_attr.attr, 1698 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 1699 &sensor_dev_attr_temp3_fault.dev_attr.attr, 1700 /* Zones */ 1701 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1702 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1703 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1704 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, 1705 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1706 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1707 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1708 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, 1709 NULL 1710 }; 1711 1712 static const struct attribute_group dme1737_group = { 1713 .attrs = dme1737_attr, 1714 }; 1715 1716 /* 1717 * The following struct holds temp offset attributes, which are not available 1718 * in all chips. The following chips support them: 1719 * DME1737, SCH311x 1720 */ 1721 static struct attribute *dme1737_temp_offset_attr[] = { 1722 &sensor_dev_attr_temp1_offset.dev_attr.attr, 1723 &sensor_dev_attr_temp2_offset.dev_attr.attr, 1724 &sensor_dev_attr_temp3_offset.dev_attr.attr, 1725 NULL 1726 }; 1727 1728 static const struct attribute_group dme1737_temp_offset_group = { 1729 .attrs = dme1737_temp_offset_attr, 1730 }; 1731 1732 /* 1733 * The following struct holds VID related attributes, which are not available 1734 * in all chips. The following chips support them: 1735 * DME1737 1736 */ 1737 static struct attribute *dme1737_vid_attr[] = { 1738 &dev_attr_vrm.attr, 1739 &dev_attr_cpu0_vid.attr, 1740 NULL 1741 }; 1742 1743 static const struct attribute_group dme1737_vid_group = { 1744 .attrs = dme1737_vid_attr, 1745 }; 1746 1747 /* 1748 * The following struct holds temp zone 3 related attributes, which are not 1749 * available in all chips. The following chips support them: 1750 * DME1737, SCH311x, SCH5027 1751 */ 1752 static struct attribute *dme1737_zone3_attr[] = { 1753 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1754 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1755 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1756 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, 1757 NULL 1758 }; 1759 1760 static const struct attribute_group dme1737_zone3_group = { 1761 .attrs = dme1737_zone3_attr, 1762 }; 1763 1764 1765 /* 1766 * The following struct holds temp zone hysteresis related attributes, which 1767 * are not available in all chips. The following chips support them: 1768 * DME1737, SCH311x 1769 */ 1770 static struct attribute *dme1737_zone_hyst_attr[] = { 1771 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, 1772 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, 1773 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, 1774 NULL 1775 }; 1776 1777 static const struct attribute_group dme1737_zone_hyst_group = { 1778 .attrs = dme1737_zone_hyst_attr, 1779 }; 1780 1781 /* 1782 * The following struct holds voltage in7 related attributes, which 1783 * are not available in all chips. The following chips support them: 1784 * SCH5127 1785 */ 1786 static struct attribute *dme1737_in7_attr[] = { 1787 &sensor_dev_attr_in7_input.dev_attr.attr, 1788 &sensor_dev_attr_in7_min.dev_attr.attr, 1789 &sensor_dev_attr_in7_max.dev_attr.attr, 1790 &sensor_dev_attr_in7_alarm.dev_attr.attr, 1791 NULL 1792 }; 1793 1794 static const struct attribute_group dme1737_in7_group = { 1795 .attrs = dme1737_in7_attr, 1796 }; 1797 1798 /* 1799 * The following structs hold the PWM attributes, some of which are optional. 1800 * Their creation depends on the chip configuration which is determined during 1801 * module load. 1802 */ 1803 static struct attribute *dme1737_pwm1_attr[] = { 1804 &sensor_dev_attr_pwm1.dev_attr.attr, 1805 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1806 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1807 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1808 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1809 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1810 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 1811 NULL 1812 }; 1813 static struct attribute *dme1737_pwm2_attr[] = { 1814 &sensor_dev_attr_pwm2.dev_attr.attr, 1815 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1816 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1817 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1818 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1819 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1820 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 1821 NULL 1822 }; 1823 static struct attribute *dme1737_pwm3_attr[] = { 1824 &sensor_dev_attr_pwm3.dev_attr.attr, 1825 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1826 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1827 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1828 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1829 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1830 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 1831 NULL 1832 }; 1833 static struct attribute *dme1737_pwm5_attr[] = { 1834 &sensor_dev_attr_pwm5.dev_attr.attr, 1835 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1836 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 1837 NULL 1838 }; 1839 static struct attribute *dme1737_pwm6_attr[] = { 1840 &sensor_dev_attr_pwm6.dev_attr.attr, 1841 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1842 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 1843 NULL 1844 }; 1845 1846 static const struct attribute_group dme1737_pwm_group[] = { 1847 { .attrs = dme1737_pwm1_attr }, 1848 { .attrs = dme1737_pwm2_attr }, 1849 { .attrs = dme1737_pwm3_attr }, 1850 { .attrs = NULL }, 1851 { .attrs = dme1737_pwm5_attr }, 1852 { .attrs = dme1737_pwm6_attr }, 1853 }; 1854 1855 /* 1856 * The following struct holds auto PWM min attributes, which are not available 1857 * in all chips. Their creation depends on the chip type which is determined 1858 * during module load. 1859 */ 1860 static struct attribute *dme1737_auto_pwm_min_attr[] = { 1861 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, 1862 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, 1863 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, 1864 }; 1865 1866 /* 1867 * The following structs hold the fan attributes, some of which are optional. 1868 * Their creation depends on the chip configuration which is determined during 1869 * module load. 1870 */ 1871 static struct attribute *dme1737_fan1_attr[] = { 1872 &sensor_dev_attr_fan1_input.dev_attr.attr, 1873 &sensor_dev_attr_fan1_min.dev_attr.attr, 1874 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 1875 &sensor_dev_attr_fan1_type.dev_attr.attr, 1876 NULL 1877 }; 1878 static struct attribute *dme1737_fan2_attr[] = { 1879 &sensor_dev_attr_fan2_input.dev_attr.attr, 1880 &sensor_dev_attr_fan2_min.dev_attr.attr, 1881 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 1882 &sensor_dev_attr_fan2_type.dev_attr.attr, 1883 NULL 1884 }; 1885 static struct attribute *dme1737_fan3_attr[] = { 1886 &sensor_dev_attr_fan3_input.dev_attr.attr, 1887 &sensor_dev_attr_fan3_min.dev_attr.attr, 1888 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 1889 &sensor_dev_attr_fan3_type.dev_attr.attr, 1890 NULL 1891 }; 1892 static struct attribute *dme1737_fan4_attr[] = { 1893 &sensor_dev_attr_fan4_input.dev_attr.attr, 1894 &sensor_dev_attr_fan4_min.dev_attr.attr, 1895 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 1896 &sensor_dev_attr_fan4_type.dev_attr.attr, 1897 NULL 1898 }; 1899 static struct attribute *dme1737_fan5_attr[] = { 1900 &sensor_dev_attr_fan5_input.dev_attr.attr, 1901 &sensor_dev_attr_fan5_min.dev_attr.attr, 1902 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 1903 &sensor_dev_attr_fan5_max.dev_attr.attr, 1904 NULL 1905 }; 1906 static struct attribute *dme1737_fan6_attr[] = { 1907 &sensor_dev_attr_fan6_input.dev_attr.attr, 1908 &sensor_dev_attr_fan6_min.dev_attr.attr, 1909 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 1910 &sensor_dev_attr_fan6_max.dev_attr.attr, 1911 NULL 1912 }; 1913 1914 static const struct attribute_group dme1737_fan_group[] = { 1915 { .attrs = dme1737_fan1_attr }, 1916 { .attrs = dme1737_fan2_attr }, 1917 { .attrs = dme1737_fan3_attr }, 1918 { .attrs = dme1737_fan4_attr }, 1919 { .attrs = dme1737_fan5_attr }, 1920 { .attrs = dme1737_fan6_attr }, 1921 }; 1922 1923 /* 1924 * The permissions of the following zone attributes are changed to read- 1925 * writeable if the chip is *not* locked. Otherwise they stay read-only. 1926 */ 1927 static struct attribute *dme1737_zone_chmod_attr[] = { 1928 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1929 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1930 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1931 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1932 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1933 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1934 NULL 1935 }; 1936 1937 static const struct attribute_group dme1737_zone_chmod_group = { 1938 .attrs = dme1737_zone_chmod_attr, 1939 }; 1940 1941 1942 /* 1943 * The permissions of the following zone 3 attributes are changed to read- 1944 * writeable if the chip is *not* locked. Otherwise they stay read-only. 1945 */ 1946 static struct attribute *dme1737_zone3_chmod_attr[] = { 1947 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1948 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1949 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1950 NULL 1951 }; 1952 1953 static const struct attribute_group dme1737_zone3_chmod_group = { 1954 .attrs = dme1737_zone3_chmod_attr, 1955 }; 1956 1957 /* 1958 * The permissions of the following PWM attributes are changed to read- 1959 * writeable if the chip is *not* locked and the respective PWM is available. 1960 * Otherwise they stay read-only. 1961 */ 1962 static struct attribute *dme1737_pwm1_chmod_attr[] = { 1963 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1964 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1965 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1966 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1967 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1968 NULL 1969 }; 1970 static struct attribute *dme1737_pwm2_chmod_attr[] = { 1971 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1972 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1973 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1974 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1975 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1976 NULL 1977 }; 1978 static struct attribute *dme1737_pwm3_chmod_attr[] = { 1979 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1980 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1981 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1982 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1983 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1984 NULL 1985 }; 1986 static struct attribute *dme1737_pwm5_chmod_attr[] = { 1987 &sensor_dev_attr_pwm5.dev_attr.attr, 1988 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1989 NULL 1990 }; 1991 static struct attribute *dme1737_pwm6_chmod_attr[] = { 1992 &sensor_dev_attr_pwm6.dev_attr.attr, 1993 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1994 NULL 1995 }; 1996 1997 static const struct attribute_group dme1737_pwm_chmod_group[] = { 1998 { .attrs = dme1737_pwm1_chmod_attr }, 1999 { .attrs = dme1737_pwm2_chmod_attr }, 2000 { .attrs = dme1737_pwm3_chmod_attr }, 2001 { .attrs = NULL }, 2002 { .attrs = dme1737_pwm5_chmod_attr }, 2003 { .attrs = dme1737_pwm6_chmod_attr }, 2004 }; 2005 2006 /* 2007 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the 2008 * chip is not locked. Otherwise they are read-only. 2009 */ 2010 static struct attribute *dme1737_pwm_chmod_attr[] = { 2011 &sensor_dev_attr_pwm1.dev_attr.attr, 2012 &sensor_dev_attr_pwm2.dev_attr.attr, 2013 &sensor_dev_attr_pwm3.dev_attr.attr, 2014 }; 2015 2016 /* --------------------------------------------------------------------- 2017 * Super-IO functions 2018 * --------------------------------------------------------------------- */ 2019 2020 static inline void dme1737_sio_enter(int sio_cip) 2021 { 2022 outb(0x55, sio_cip); 2023 } 2024 2025 static inline void dme1737_sio_exit(int sio_cip) 2026 { 2027 outb(0xaa, sio_cip); 2028 } 2029 2030 static inline int dme1737_sio_inb(int sio_cip, int reg) 2031 { 2032 outb(reg, sio_cip); 2033 return inb(sio_cip + 1); 2034 } 2035 2036 static inline void dme1737_sio_outb(int sio_cip, int reg, int val) 2037 { 2038 outb(reg, sio_cip); 2039 outb(val, sio_cip + 1); 2040 } 2041 2042 /* --------------------------------------------------------------------- 2043 * Device initialization 2044 * --------------------------------------------------------------------- */ 2045 2046 static int dme1737_i2c_get_features(int, struct dme1737_data*); 2047 2048 static void dme1737_chmod_file(struct device *dev, 2049 struct attribute *attr, umode_t mode) 2050 { 2051 if (sysfs_chmod_file(&dev->kobj, attr, mode)) { 2052 dev_warn(dev, "Failed to change permissions of %s.\n", 2053 attr->name); 2054 } 2055 } 2056 2057 static void dme1737_chmod_group(struct device *dev, 2058 const struct attribute_group *group, 2059 umode_t mode) 2060 { 2061 struct attribute **attr; 2062 2063 for (attr = group->attrs; *attr; attr++) 2064 dme1737_chmod_file(dev, *attr, mode); 2065 } 2066 2067 static void dme1737_remove_files(struct device *dev) 2068 { 2069 struct dme1737_data *data = dev_get_drvdata(dev); 2070 int ix; 2071 2072 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 2073 if (data->has_features & HAS_FAN(ix)) { 2074 sysfs_remove_group(&dev->kobj, 2075 &dme1737_fan_group[ix]); 2076 } 2077 } 2078 2079 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 2080 if (data->has_features & HAS_PWM(ix)) { 2081 sysfs_remove_group(&dev->kobj, 2082 &dme1737_pwm_group[ix]); 2083 if ((data->has_features & HAS_PWM_MIN) && ix < 3) { 2084 sysfs_remove_file(&dev->kobj, 2085 dme1737_auto_pwm_min_attr[ix]); 2086 } 2087 } 2088 } 2089 2090 if (data->has_features & HAS_TEMP_OFFSET) 2091 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group); 2092 if (data->has_features & HAS_VID) 2093 sysfs_remove_group(&dev->kobj, &dme1737_vid_group); 2094 if (data->has_features & HAS_ZONE3) 2095 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group); 2096 if (data->has_features & HAS_ZONE_HYST) 2097 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group); 2098 if (data->has_features & HAS_IN7) 2099 sysfs_remove_group(&dev->kobj, &dme1737_in7_group); 2100 sysfs_remove_group(&dev->kobj, &dme1737_group); 2101 2102 if (!data->client) 2103 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr); 2104 } 2105 2106 static int dme1737_create_files(struct device *dev) 2107 { 2108 struct dme1737_data *data = dev_get_drvdata(dev); 2109 int err, ix; 2110 2111 /* Create a name attribute for ISA devices */ 2112 if (!data->client) { 2113 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr); 2114 if (err) 2115 goto exit; 2116 } 2117 2118 /* Create standard sysfs attributes */ 2119 err = sysfs_create_group(&dev->kobj, &dme1737_group); 2120 if (err) 2121 goto exit_remove; 2122 2123 /* Create chip-dependent sysfs attributes */ 2124 if (data->has_features & HAS_TEMP_OFFSET) { 2125 err = sysfs_create_group(&dev->kobj, 2126 &dme1737_temp_offset_group); 2127 if (err) 2128 goto exit_remove; 2129 } 2130 if (data->has_features & HAS_VID) { 2131 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group); 2132 if (err) 2133 goto exit_remove; 2134 } 2135 if (data->has_features & HAS_ZONE3) { 2136 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group); 2137 if (err) 2138 goto exit_remove; 2139 } 2140 if (data->has_features & HAS_ZONE_HYST) { 2141 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group); 2142 if (err) 2143 goto exit_remove; 2144 } 2145 if (data->has_features & HAS_IN7) { 2146 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group); 2147 if (err) 2148 goto exit_remove; 2149 } 2150 2151 /* Create fan sysfs attributes */ 2152 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 2153 if (data->has_features & HAS_FAN(ix)) { 2154 err = sysfs_create_group(&dev->kobj, 2155 &dme1737_fan_group[ix]); 2156 if (err) 2157 goto exit_remove; 2158 } 2159 } 2160 2161 /* Create PWM sysfs attributes */ 2162 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 2163 if (data->has_features & HAS_PWM(ix)) { 2164 err = sysfs_create_group(&dev->kobj, 2165 &dme1737_pwm_group[ix]); 2166 if (err) 2167 goto exit_remove; 2168 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) { 2169 err = sysfs_create_file(&dev->kobj, 2170 dme1737_auto_pwm_min_attr[ix]); 2171 if (err) 2172 goto exit_remove; 2173 } 2174 } 2175 } 2176 2177 /* 2178 * Inform if the device is locked. Otherwise change the permissions of 2179 * selected attributes from read-only to read-writeable. 2180 */ 2181 if (data->config & 0x02) { 2182 dev_info(dev, "Device is locked. Some attributes " 2183 "will be read-only.\n"); 2184 } else { 2185 /* Change permissions of zone sysfs attributes */ 2186 dme1737_chmod_group(dev, &dme1737_zone_chmod_group, 2187 S_IRUGO | S_IWUSR); 2188 2189 /* Change permissions of chip-dependent sysfs attributes */ 2190 if (data->has_features & HAS_TEMP_OFFSET) { 2191 dme1737_chmod_group(dev, &dme1737_temp_offset_group, 2192 S_IRUGO | S_IWUSR); 2193 } 2194 if (data->has_features & HAS_ZONE3) { 2195 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group, 2196 S_IRUGO | S_IWUSR); 2197 } 2198 if (data->has_features & HAS_ZONE_HYST) { 2199 dme1737_chmod_group(dev, &dme1737_zone_hyst_group, 2200 S_IRUGO | S_IWUSR); 2201 } 2202 2203 /* Change permissions of PWM sysfs attributes */ 2204 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { 2205 if (data->has_features & HAS_PWM(ix)) { 2206 dme1737_chmod_group(dev, 2207 &dme1737_pwm_chmod_group[ix], 2208 S_IRUGO | S_IWUSR); 2209 if ((data->has_features & HAS_PWM_MIN) && 2210 ix < 3) { 2211 dme1737_chmod_file(dev, 2212 dme1737_auto_pwm_min_attr[ix], 2213 S_IRUGO | S_IWUSR); 2214 } 2215 } 2216 } 2217 2218 /* Change permissions of pwm[1-3] if in manual mode */ 2219 for (ix = 0; ix < 3; ix++) { 2220 if ((data->has_features & HAS_PWM(ix)) && 2221 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { 2222 dme1737_chmod_file(dev, 2223 dme1737_pwm_chmod_attr[ix], 2224 S_IRUGO | S_IWUSR); 2225 } 2226 } 2227 } 2228 2229 return 0; 2230 2231 exit_remove: 2232 dme1737_remove_files(dev); 2233 exit: 2234 return err; 2235 } 2236 2237 static int dme1737_init_device(struct device *dev) 2238 { 2239 struct dme1737_data *data = dev_get_drvdata(dev); 2240 struct i2c_client *client = data->client; 2241 int ix; 2242 u8 reg; 2243 2244 /* Point to the right nominal voltages array */ 2245 data->in_nominal = IN_NOMINAL(data->type); 2246 2247 data->config = dme1737_read(data, DME1737_REG_CONFIG); 2248 /* Inform if part is not monitoring/started */ 2249 if (!(data->config & 0x01)) { 2250 if (!force_start) { 2251 dev_err(dev, "Device is not monitoring. " 2252 "Use the force_start load parameter to " 2253 "override.\n"); 2254 return -EFAULT; 2255 } 2256 2257 /* Force monitoring */ 2258 data->config |= 0x01; 2259 dme1737_write(data, DME1737_REG_CONFIG, data->config); 2260 } 2261 /* Inform if part is not ready */ 2262 if (!(data->config & 0x04)) { 2263 dev_err(dev, "Device is not ready.\n"); 2264 return -EFAULT; 2265 } 2266 2267 /* 2268 * Determine which optional fan and pwm features are enabled (only 2269 * valid for I2C devices) 2270 */ 2271 if (client) { /* I2C chip */ 2272 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2); 2273 /* Check if optional fan3 input is enabled */ 2274 if (data->config2 & 0x04) 2275 data->has_features |= HAS_FAN(2); 2276 2277 /* 2278 * Fan4 and pwm3 are only available if the client's I2C address 2279 * is the default 0x2e. Otherwise the I/Os associated with 2280 * these functions are used for addr enable/select. 2281 */ 2282 if (client->addr == 0x2e) 2283 data->has_features |= HAS_FAN(3) | HAS_PWM(2); 2284 2285 /* 2286 * Determine which of the optional fan[5-6] and pwm[5-6] 2287 * features are enabled. For this, we need to query the runtime 2288 * registers through the Super-IO LPC interface. Try both 2289 * config ports 0x2e and 0x4e. 2290 */ 2291 if (dme1737_i2c_get_features(0x2e, data) && 2292 dme1737_i2c_get_features(0x4e, data)) { 2293 dev_warn(dev, "Failed to query Super-IO for optional " 2294 "features.\n"); 2295 } 2296 } 2297 2298 /* Fan[1-2] and pwm[1-2] are present in all chips */ 2299 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1); 2300 2301 /* Chip-dependent features */ 2302 switch (data->type) { 2303 case dme1737: 2304 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 | 2305 HAS_ZONE_HYST | HAS_PWM_MIN; 2306 break; 2307 case sch311x: 2308 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 | 2309 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2); 2310 break; 2311 case sch5027: 2312 data->has_features |= HAS_ZONE3; 2313 break; 2314 case sch5127: 2315 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7; 2316 break; 2317 default: 2318 break; 2319 } 2320 2321 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, " 2322 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n", 2323 (data->has_features & HAS_PWM(2)) ? "yes" : "no", 2324 (data->has_features & HAS_PWM(4)) ? "yes" : "no", 2325 (data->has_features & HAS_PWM(5)) ? "yes" : "no", 2326 (data->has_features & HAS_FAN(2)) ? "yes" : "no", 2327 (data->has_features & HAS_FAN(3)) ? "yes" : "no", 2328 (data->has_features & HAS_FAN(4)) ? "yes" : "no", 2329 (data->has_features & HAS_FAN(5)) ? "yes" : "no"); 2330 2331 reg = dme1737_read(data, DME1737_REG_TACH_PWM); 2332 /* Inform if fan-to-pwm mapping differs from the default */ 2333 if (client && reg != 0xa4) { /* I2C chip */ 2334 dev_warn(dev, "Non-standard fan to pwm mapping: " 2335 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, " 2336 "fan4->pwm%d. Please report to the driver " 2337 "maintainer.\n", 2338 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2339 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1); 2340 } else if (!client && reg != 0x24) { /* ISA chip */ 2341 dev_warn(dev, "Non-standard fan to pwm mapping: " 2342 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. " 2343 "Please report to the driver maintainer.\n", 2344 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2345 ((reg >> 4) & 0x03) + 1); 2346 } 2347 2348 /* 2349 * Switch pwm[1-3] to manual mode if they are currently disabled and 2350 * set the duty-cycles to 0% (which is identical to the PWMs being 2351 * disabled). 2352 */ 2353 if (!(data->config & 0x02)) { 2354 for (ix = 0; ix < 3; ix++) { 2355 data->pwm_config[ix] = dme1737_read(data, 2356 DME1737_REG_PWM_CONFIG(ix)); 2357 if ((data->has_features & HAS_PWM(ix)) && 2358 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) { 2359 dev_info(dev, "Switching pwm%d to " 2360 "manual mode.\n", ix + 1); 2361 data->pwm_config[ix] = PWM_EN_TO_REG(1, 2362 data->pwm_config[ix]); 2363 dme1737_write(data, DME1737_REG_PWM(ix), 0); 2364 dme1737_write(data, 2365 DME1737_REG_PWM_CONFIG(ix), 2366 data->pwm_config[ix]); 2367 } 2368 } 2369 } 2370 2371 /* Initialize the default PWM auto channels zone (acz) assignments */ 2372 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */ 2373 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */ 2374 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ 2375 2376 /* Set VRM */ 2377 if (data->has_features & HAS_VID) 2378 data->vrm = vid_which_vrm(); 2379 2380 return 0; 2381 } 2382 2383 /* --------------------------------------------------------------------- 2384 * I2C device detection and registration 2385 * --------------------------------------------------------------------- */ 2386 2387 static struct i2c_driver dme1737_i2c_driver; 2388 2389 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) 2390 { 2391 int err = 0, reg; 2392 u16 addr; 2393 2394 dme1737_sio_enter(sio_cip); 2395 2396 /* 2397 * Check device ID 2398 * We currently know about two kinds of DME1737 and SCH5027. 2399 */ 2400 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2401 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 || 2402 reg == SCH5027_ID)) { 2403 err = -ENODEV; 2404 goto exit; 2405 } 2406 2407 /* Select logical device A (runtime registers) */ 2408 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2409 2410 /* Get the base address of the runtime registers */ 2411 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2412 dme1737_sio_inb(sio_cip, 0x61); 2413 if (!addr) { 2414 err = -ENODEV; 2415 goto exit; 2416 } 2417 2418 /* 2419 * Read the runtime registers to determine which optional features 2420 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set 2421 * to '10' if the respective feature is enabled. 2422 */ 2423 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */ 2424 data->has_features |= HAS_FAN(5); 2425 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */ 2426 data->has_features |= HAS_PWM(5); 2427 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */ 2428 data->has_features |= HAS_FAN(4); 2429 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */ 2430 data->has_features |= HAS_PWM(4); 2431 2432 exit: 2433 dme1737_sio_exit(sio_cip); 2434 2435 return err; 2436 } 2437 2438 /* Return 0 if detection is successful, -ENODEV otherwise */ 2439 static int dme1737_i2c_detect(struct i2c_client *client, 2440 struct i2c_board_info *info) 2441 { 2442 struct i2c_adapter *adapter = client->adapter; 2443 struct device *dev = &adapter->dev; 2444 u8 company, verstep = 0; 2445 const char *name; 2446 2447 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2448 return -ENODEV; 2449 2450 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY); 2451 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP); 2452 2453 if (company == DME1737_COMPANY_SMSC && 2454 verstep == SCH5027_VERSTEP) { 2455 name = "sch5027"; 2456 } else if (company == DME1737_COMPANY_SMSC && 2457 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { 2458 name = "dme1737"; 2459 } else { 2460 return -ENODEV; 2461 } 2462 2463 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", 2464 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737", 2465 client->addr, verstep); 2466 strlcpy(info->type, name, I2C_NAME_SIZE); 2467 2468 return 0; 2469 } 2470 2471 static int dme1737_i2c_probe(struct i2c_client *client, 2472 const struct i2c_device_id *id) 2473 { 2474 struct dme1737_data *data; 2475 struct device *dev = &client->dev; 2476 int err; 2477 2478 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL); 2479 if (!data) 2480 return -ENOMEM; 2481 2482 i2c_set_clientdata(client, data); 2483 data->type = id->driver_data; 2484 data->client = client; 2485 data->name = client->name; 2486 mutex_init(&data->update_lock); 2487 2488 /* Initialize the DME1737 chip */ 2489 err = dme1737_init_device(dev); 2490 if (err) { 2491 dev_err(dev, "Failed to initialize device.\n"); 2492 return err; 2493 } 2494 2495 /* Create sysfs files */ 2496 err = dme1737_create_files(dev); 2497 if (err) { 2498 dev_err(dev, "Failed to create sysfs files.\n"); 2499 return err; 2500 } 2501 2502 /* Register device */ 2503 data->hwmon_dev = hwmon_device_register(dev); 2504 if (IS_ERR(data->hwmon_dev)) { 2505 dev_err(dev, "Failed to register device.\n"); 2506 err = PTR_ERR(data->hwmon_dev); 2507 goto exit_remove; 2508 } 2509 2510 return 0; 2511 2512 exit_remove: 2513 dme1737_remove_files(dev); 2514 return err; 2515 } 2516 2517 static int dme1737_i2c_remove(struct i2c_client *client) 2518 { 2519 struct dme1737_data *data = i2c_get_clientdata(client); 2520 2521 hwmon_device_unregister(data->hwmon_dev); 2522 dme1737_remove_files(&client->dev); 2523 2524 return 0; 2525 } 2526 2527 static const struct i2c_device_id dme1737_id[] = { 2528 { "dme1737", dme1737 }, 2529 { "sch5027", sch5027 }, 2530 { } 2531 }; 2532 MODULE_DEVICE_TABLE(i2c, dme1737_id); 2533 2534 static struct i2c_driver dme1737_i2c_driver = { 2535 .class = I2C_CLASS_HWMON, 2536 .driver = { 2537 .name = "dme1737", 2538 }, 2539 .probe = dme1737_i2c_probe, 2540 .remove = dme1737_i2c_remove, 2541 .id_table = dme1737_id, 2542 .detect = dme1737_i2c_detect, 2543 .address_list = normal_i2c, 2544 }; 2545 2546 /* --------------------------------------------------------------------- 2547 * ISA device detection and registration 2548 * --------------------------------------------------------------------- */ 2549 2550 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr) 2551 { 2552 int err = 0, reg; 2553 unsigned short base_addr; 2554 2555 dme1737_sio_enter(sio_cip); 2556 2557 /* 2558 * Check device ID 2559 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 2560 */ 2561 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2562 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID || 2563 reg == SCH5127_ID)) { 2564 err = -ENODEV; 2565 goto exit; 2566 } 2567 2568 /* Select logical device A (runtime registers) */ 2569 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2570 2571 /* Get the base address of the runtime registers */ 2572 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2573 dme1737_sio_inb(sio_cip, 0x61); 2574 if (!base_addr) { 2575 pr_err("Base address not set\n"); 2576 err = -ENODEV; 2577 goto exit; 2578 } 2579 2580 /* 2581 * Access to the hwmon registers is through an index/data register 2582 * pair located at offset 0x70/0x71. 2583 */ 2584 *addr = base_addr + 0x70; 2585 2586 exit: 2587 dme1737_sio_exit(sio_cip); 2588 return err; 2589 } 2590 2591 static int __init dme1737_isa_device_add(unsigned short addr) 2592 { 2593 struct resource res = { 2594 .start = addr, 2595 .end = addr + DME1737_EXTENT - 1, 2596 .name = "dme1737", 2597 .flags = IORESOURCE_IO, 2598 }; 2599 int err; 2600 2601 err = acpi_check_resource_conflict(&res); 2602 if (err) 2603 goto exit; 2604 2605 pdev = platform_device_alloc("dme1737", addr); 2606 if (!pdev) { 2607 pr_err("Failed to allocate device\n"); 2608 err = -ENOMEM; 2609 goto exit; 2610 } 2611 2612 err = platform_device_add_resources(pdev, &res, 1); 2613 if (err) { 2614 pr_err("Failed to add device resource (err = %d)\n", err); 2615 goto exit_device_put; 2616 } 2617 2618 err = platform_device_add(pdev); 2619 if (err) { 2620 pr_err("Failed to add device (err = %d)\n", err); 2621 goto exit_device_put; 2622 } 2623 2624 return 0; 2625 2626 exit_device_put: 2627 platform_device_put(pdev); 2628 pdev = NULL; 2629 exit: 2630 return err; 2631 } 2632 2633 static int __devinit dme1737_isa_probe(struct platform_device *pdev) 2634 { 2635 u8 company, device; 2636 struct resource *res; 2637 struct dme1737_data *data; 2638 struct device *dev = &pdev->dev; 2639 int err; 2640 2641 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 2642 if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) { 2643 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n", 2644 (unsigned short)res->start, 2645 (unsigned short)res->start + DME1737_EXTENT - 1); 2646 return -EBUSY; 2647 } 2648 2649 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL); 2650 if (!data) 2651 return -ENOMEM; 2652 2653 data->addr = res->start; 2654 platform_set_drvdata(pdev, data); 2655 2656 /* Skip chip detection if module is loaded with force_id parameter */ 2657 switch (force_id) { 2658 case SCH3112_ID: 2659 case SCH3114_ID: 2660 case SCH3116_ID: 2661 data->type = sch311x; 2662 break; 2663 case SCH5127_ID: 2664 data->type = sch5127; 2665 break; 2666 default: 2667 company = dme1737_read(data, DME1737_REG_COMPANY); 2668 device = dme1737_read(data, DME1737_REG_DEVICE); 2669 2670 if ((company == DME1737_COMPANY_SMSC) && 2671 (device == SCH311X_DEVICE)) { 2672 data->type = sch311x; 2673 } else if ((company == DME1737_COMPANY_SMSC) && 2674 (device == SCH5127_DEVICE)) { 2675 data->type = sch5127; 2676 } else { 2677 return -ENODEV; 2678 } 2679 } 2680 2681 if (data->type == sch5127) 2682 data->name = "sch5127"; 2683 else 2684 data->name = "sch311x"; 2685 2686 /* Initialize the mutex */ 2687 mutex_init(&data->update_lock); 2688 2689 dev_info(dev, "Found a %s chip at 0x%04x\n", 2690 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr); 2691 2692 /* Initialize the chip */ 2693 err = dme1737_init_device(dev); 2694 if (err) { 2695 dev_err(dev, "Failed to initialize device.\n"); 2696 return err; 2697 } 2698 2699 /* Create sysfs files */ 2700 err = dme1737_create_files(dev); 2701 if (err) { 2702 dev_err(dev, "Failed to create sysfs files.\n"); 2703 return err; 2704 } 2705 2706 /* Register device */ 2707 data->hwmon_dev = hwmon_device_register(dev); 2708 if (IS_ERR(data->hwmon_dev)) { 2709 dev_err(dev, "Failed to register device.\n"); 2710 err = PTR_ERR(data->hwmon_dev); 2711 goto exit_remove_files; 2712 } 2713 2714 return 0; 2715 2716 exit_remove_files: 2717 dme1737_remove_files(dev); 2718 return err; 2719 } 2720 2721 static int __devexit dme1737_isa_remove(struct platform_device *pdev) 2722 { 2723 struct dme1737_data *data = platform_get_drvdata(pdev); 2724 2725 hwmon_device_unregister(data->hwmon_dev); 2726 dme1737_remove_files(&pdev->dev); 2727 2728 return 0; 2729 } 2730 2731 static struct platform_driver dme1737_isa_driver = { 2732 .driver = { 2733 .owner = THIS_MODULE, 2734 .name = "dme1737", 2735 }, 2736 .probe = dme1737_isa_probe, 2737 .remove = __devexit_p(dme1737_isa_remove), 2738 }; 2739 2740 /* --------------------------------------------------------------------- 2741 * Module initialization and cleanup 2742 * --------------------------------------------------------------------- */ 2743 2744 static int __init dme1737_init(void) 2745 { 2746 int err; 2747 unsigned short addr; 2748 2749 err = i2c_add_driver(&dme1737_i2c_driver); 2750 if (err) 2751 goto exit; 2752 2753 if (dme1737_isa_detect(0x2e, &addr) && 2754 dme1737_isa_detect(0x4e, &addr) && 2755 (!probe_all_addr || 2756 (dme1737_isa_detect(0x162e, &addr) && 2757 dme1737_isa_detect(0x164e, &addr)))) { 2758 /* Return 0 if we didn't find an ISA device */ 2759 return 0; 2760 } 2761 2762 err = platform_driver_register(&dme1737_isa_driver); 2763 if (err) 2764 goto exit_del_i2c_driver; 2765 2766 /* Sets global pdev as a side effect */ 2767 err = dme1737_isa_device_add(addr); 2768 if (err) 2769 goto exit_del_isa_driver; 2770 2771 return 0; 2772 2773 exit_del_isa_driver: 2774 platform_driver_unregister(&dme1737_isa_driver); 2775 exit_del_i2c_driver: 2776 i2c_del_driver(&dme1737_i2c_driver); 2777 exit: 2778 return err; 2779 } 2780 2781 static void __exit dme1737_exit(void) 2782 { 2783 if (pdev) { 2784 platform_device_unregister(pdev); 2785 platform_driver_unregister(&dme1737_isa_driver); 2786 } 2787 2788 i2c_del_driver(&dme1737_i2c_driver); 2789 } 2790 2791 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>"); 2792 MODULE_DESCRIPTION("DME1737 sensors"); 2793 MODULE_LICENSE("GPL"); 2794 2795 module_init(dme1737_init); 2796 module_exit(dme1737_exit); 2797