xref: /linux/drivers/hwmon/axi-fan-control.c (revision 37744feebc086908fd89760650f458ab19071750) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Fan Control HDL CORE driver
4  *
5  * Copyright 2019 Analog Devices Inc.
6  */
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/fpga/adi-axi-common.h>
10 #include <linux/hwmon.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 
18 #define ADI_AXI_PCORE_VER_MAJOR(version)	(((version) >> 16) & 0xff)
19 #define ADI_AXI_PCORE_VER_MINOR(version)	(((version) >> 8) & 0xff)
20 #define ADI_AXI_PCORE_VER_PATCH(version)	((version) & 0xff)
21 
22 /* register map */
23 #define ADI_REG_RSTN		0x0080
24 #define ADI_REG_PWM_WIDTH	0x0084
25 #define ADI_REG_TACH_PERIOD	0x0088
26 #define ADI_REG_TACH_TOLERANCE	0x008c
27 #define ADI_REG_PWM_PERIOD	0x00c0
28 #define ADI_REG_TACH_MEASUR	0x00c4
29 #define ADI_REG_TEMPERATURE	0x00c8
30 
31 #define ADI_REG_IRQ_MASK	0x0040
32 #define ADI_REG_IRQ_PENDING	0x0044
33 #define ADI_REG_IRQ_SRC		0x0048
34 
35 /* IRQ sources */
36 #define ADI_IRQ_SRC_PWM_CHANGED		BIT(0)
37 #define ADI_IRQ_SRC_TACH_ERR		BIT(1)
38 #define ADI_IRQ_SRC_TEMP_INCREASE	BIT(2)
39 #define ADI_IRQ_SRC_NEW_MEASUR		BIT(3)
40 #define ADI_IRQ_SRC_MASK		GENMASK(3, 0)
41 #define ADI_IRQ_MASK_OUT_ALL		0xFFFFFFFFU
42 
43 #define SYSFS_PWM_MAX			255
44 
45 struct axi_fan_control_data {
46 	void __iomem *base;
47 	struct device *hdev;
48 	unsigned long clk_rate;
49 	int irq;
50 	/* pulses per revolution */
51 	u32 ppr;
52 	bool hw_pwm_req;
53 	bool update_tacho_params;
54 	u8 fan_fault;
55 };
56 
57 static inline void axi_iowrite(const u32 val, const u32 reg,
58 			       const struct axi_fan_control_data *ctl)
59 {
60 	iowrite32(val, ctl->base + reg);
61 }
62 
63 static inline u32 axi_ioread(const u32 reg,
64 			     const struct axi_fan_control_data *ctl)
65 {
66 	return ioread32(ctl->base + reg);
67 }
68 
69 static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl)
70 {
71 	u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl);
72 	u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl);
73 	/*
74 	 * PWM_PERIOD is a RO register set by the core. It should never be 0.
75 	 * For now we are trusting the HW...
76 	 */
77 	return DIV_ROUND_CLOSEST(pwm_width * SYSFS_PWM_MAX, pwm_period);
78 }
79 
80 static int axi_fan_control_set_pwm_duty(const long val,
81 					struct axi_fan_control_data *ctl)
82 {
83 	u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl);
84 	u32 new_width;
85 	long __val = clamp_val(val, 0, SYSFS_PWM_MAX);
86 
87 	new_width = DIV_ROUND_CLOSEST(__val * pwm_period, SYSFS_PWM_MAX);
88 
89 	axi_iowrite(new_width, ADI_REG_PWM_WIDTH, ctl);
90 
91 	return 0;
92 }
93 
94 static long axi_fan_control_get_fan_rpm(const struct axi_fan_control_data *ctl)
95 {
96 	const u32 tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl);
97 
98 	if (tach == 0)
99 		/* should we return error, EAGAIN maybe? */
100 		return 0;
101 	/*
102 	 * The tacho period should be:
103 	 *      TACH = 60/(ppr * rpm), where rpm is revolutions per second
104 	 *      and ppr is pulses per revolution.
105 	 * Given the tacho period, we can multiply it by the input clock
106 	 * so that we know how many clocks we need to have this period.
107 	 * From this, we can derive the RPM value.
108 	 */
109 	return DIV_ROUND_CLOSEST(60 * ctl->clk_rate, ctl->ppr * tach);
110 }
111 
112 static int axi_fan_control_read_temp(struct device *dev, u32 attr, long *val)
113 {
114 	struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
115 	long raw_temp;
116 
117 	switch (attr) {
118 	case hwmon_temp_input:
119 		raw_temp = axi_ioread(ADI_REG_TEMPERATURE, ctl);
120 		/*
121 		 * The formula for the temperature is:
122 		 *      T = (ADC * 501.3743 / 2^bits) - 273.6777
123 		 * It's multiplied by 1000 to have millidegrees as
124 		 * specified by the hwmon sysfs interface.
125 		 */
126 		*val = ((raw_temp * 501374) >> 16) - 273677;
127 		return 0;
128 	default:
129 		return -ENOTSUPP;
130 	}
131 }
132 
133 static int axi_fan_control_read_fan(struct device *dev, u32 attr, long *val)
134 {
135 	struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
136 
137 	switch (attr) {
138 	case hwmon_fan_fault:
139 		*val = ctl->fan_fault;
140 		/* clear it now */
141 		ctl->fan_fault = 0;
142 		return 0;
143 	case hwmon_fan_input:
144 		*val = axi_fan_control_get_fan_rpm(ctl);
145 		return 0;
146 	default:
147 		return -ENOTSUPP;
148 	}
149 }
150 
151 static int axi_fan_control_read_pwm(struct device *dev, u32 attr, long *val)
152 {
153 	struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
154 
155 	switch (attr) {
156 	case hwmon_pwm_input:
157 		*val = axi_fan_control_get_pwm_duty(ctl);
158 		return 0;
159 	default:
160 		return -ENOTSUPP;
161 	}
162 }
163 
164 static int axi_fan_control_write_pwm(struct device *dev, u32 attr, long val)
165 {
166 	struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
167 
168 	switch (attr) {
169 	case hwmon_pwm_input:
170 		return axi_fan_control_set_pwm_duty(val, ctl);
171 	default:
172 		return -ENOTSUPP;
173 	}
174 }
175 
176 static int axi_fan_control_read_labels(struct device *dev,
177 				       enum hwmon_sensor_types type,
178 				       u32 attr, int channel, const char **str)
179 {
180 	switch (type) {
181 	case hwmon_fan:
182 		*str = "FAN";
183 		return 0;
184 	case hwmon_temp:
185 		*str = "SYSMON4";
186 		return 0;
187 	default:
188 		return -ENOTSUPP;
189 	}
190 }
191 
192 static int axi_fan_control_read(struct device *dev,
193 				enum hwmon_sensor_types type,
194 				u32 attr, int channel, long *val)
195 {
196 	switch (type) {
197 	case hwmon_fan:
198 		return axi_fan_control_read_fan(dev, attr, val);
199 	case hwmon_pwm:
200 		return axi_fan_control_read_pwm(dev, attr, val);
201 	case hwmon_temp:
202 		return axi_fan_control_read_temp(dev, attr, val);
203 	default:
204 		return -ENOTSUPP;
205 	}
206 }
207 
208 static int axi_fan_control_write(struct device *dev,
209 				 enum hwmon_sensor_types type,
210 				 u32 attr, int channel, long val)
211 {
212 	switch (type) {
213 	case hwmon_pwm:
214 		return axi_fan_control_write_pwm(dev, attr, val);
215 	default:
216 		return -ENOTSUPP;
217 	}
218 }
219 
220 static umode_t axi_fan_control_fan_is_visible(const u32 attr)
221 {
222 	switch (attr) {
223 	case hwmon_fan_input:
224 	case hwmon_fan_fault:
225 	case hwmon_fan_label:
226 		return 0444;
227 	default:
228 		return 0;
229 	}
230 }
231 
232 static umode_t axi_fan_control_pwm_is_visible(const u32 attr)
233 {
234 	switch (attr) {
235 	case hwmon_pwm_input:
236 		return 0644;
237 	default:
238 		return 0;
239 	}
240 }
241 
242 static umode_t axi_fan_control_temp_is_visible(const u32 attr)
243 {
244 	switch (attr) {
245 	case hwmon_temp_input:
246 	case hwmon_temp_label:
247 		return 0444;
248 	default:
249 		return 0;
250 	}
251 }
252 
253 static umode_t axi_fan_control_is_visible(const void *data,
254 					  enum hwmon_sensor_types type,
255 					  u32 attr, int channel)
256 {
257 	switch (type) {
258 	case hwmon_fan:
259 		return axi_fan_control_fan_is_visible(attr);
260 	case hwmon_pwm:
261 		return axi_fan_control_pwm_is_visible(attr);
262 	case hwmon_temp:
263 		return axi_fan_control_temp_is_visible(attr);
264 	default:
265 		return 0;
266 	}
267 }
268 
269 /*
270  * This core has two main ways of changing the PWM duty cycle. It is done,
271  * either by a request from userspace (writing on pwm1_input) or by the
272  * core itself. When the change is done by the core, it will use predefined
273  * parameters to evaluate the tach signal and, on that case we cannot set them.
274  * On the other hand, when the request is done by the user, with some arbitrary
275  * value that the core does not now about, we have to provide the tach
276  * parameters so that, the core can evaluate the signal. On the IRQ handler we
277  * distinguish this by using the ADI_IRQ_SRC_TEMP_INCREASE interrupt. This tell
278  * us that the CORE requested a new duty cycle. After this, there is 5s delay
279  * on which the core waits for the fan rotation speed to stabilize. After this
280  * we get ADI_IRQ_SRC_PWM_CHANGED irq where we will decide if we need to set
281  * the tach parameters or not on the next tach measurement cycle (corresponding
282  * already to the ney duty cycle) based on the %ctl->hw_pwm_req flag.
283  */
284 static irqreturn_t axi_fan_control_irq_handler(int irq, void *data)
285 {
286 	struct axi_fan_control_data *ctl = (struct axi_fan_control_data *)data;
287 	u32 irq_pending = axi_ioread(ADI_REG_IRQ_PENDING, ctl);
288 	u32 clear_mask;
289 
290 	if (irq_pending & ADI_IRQ_SRC_NEW_MEASUR) {
291 		if (ctl->update_tacho_params) {
292 			u32 new_tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl);
293 
294 			/* get 25% tolerance */
295 			u32 tach_tol = DIV_ROUND_CLOSEST(new_tach * 25, 100);
296 			/* set new tacho parameters */
297 			axi_iowrite(new_tach, ADI_REG_TACH_PERIOD, ctl);
298 			axi_iowrite(tach_tol, ADI_REG_TACH_TOLERANCE, ctl);
299 			ctl->update_tacho_params = false;
300 		}
301 	}
302 
303 	if (irq_pending & ADI_IRQ_SRC_PWM_CHANGED) {
304 		/*
305 		 * if the pwm changes on behalf of software,
306 		 * we need to provide new tacho parameters to the core.
307 		 * Wait for the next measurement for that...
308 		 */
309 		if (!ctl->hw_pwm_req) {
310 			ctl->update_tacho_params = true;
311 		} else {
312 			ctl->hw_pwm_req = false;
313 			sysfs_notify(&ctl->hdev->kobj, NULL, "pwm1");
314 		}
315 	}
316 
317 	if (irq_pending & ADI_IRQ_SRC_TEMP_INCREASE)
318 		/* hardware requested a new pwm */
319 		ctl->hw_pwm_req = true;
320 
321 	if (irq_pending & ADI_IRQ_SRC_TACH_ERR)
322 		ctl->fan_fault = 1;
323 
324 	/* clear all interrupts */
325 	clear_mask = irq_pending & ADI_IRQ_SRC_MASK;
326 	axi_iowrite(clear_mask, ADI_REG_IRQ_PENDING, ctl);
327 
328 	return IRQ_HANDLED;
329 }
330 
331 static int axi_fan_control_init(struct axi_fan_control_data *ctl,
332 				const struct device_node *np)
333 {
334 	int ret;
335 
336 	/* get fan pulses per revolution */
337 	ret = of_property_read_u32(np, "pulses-per-revolution", &ctl->ppr);
338 	if (ret)
339 		return ret;
340 
341 	/* 1, 2 and 4 are the typical and accepted values */
342 	if (ctl->ppr != 1 && ctl->ppr != 2 && ctl->ppr != 4)
343 		return -EINVAL;
344 	/*
345 	 * Enable all IRQs
346 	 */
347 	axi_iowrite(ADI_IRQ_MASK_OUT_ALL &
348 		    ~(ADI_IRQ_SRC_NEW_MEASUR | ADI_IRQ_SRC_TACH_ERR |
349 		      ADI_IRQ_SRC_PWM_CHANGED | ADI_IRQ_SRC_TEMP_INCREASE),
350 		    ADI_REG_IRQ_MASK, ctl);
351 
352 	/* bring the device out of reset */
353 	axi_iowrite(0x01, ADI_REG_RSTN, ctl);
354 
355 	return ret;
356 }
357 
358 static const struct hwmon_channel_info *axi_fan_control_info[] = {
359 	HWMON_CHANNEL_INFO(pwm, HWMON_PWM_INPUT),
360 	HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_LABEL),
361 	HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_LABEL),
362 	NULL
363 };
364 
365 static const struct hwmon_ops axi_fan_control_hwmon_ops = {
366 	.is_visible = axi_fan_control_is_visible,
367 	.read = axi_fan_control_read,
368 	.write = axi_fan_control_write,
369 	.read_string = axi_fan_control_read_labels,
370 };
371 
372 static const struct hwmon_chip_info axi_chip_info = {
373 	.ops = &axi_fan_control_hwmon_ops,
374 	.info = axi_fan_control_info,
375 };
376 
377 static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a');
378 
379 static const struct of_device_id axi_fan_control_of_match[] = {
380 	{ .compatible = "adi,axi-fan-control-1.00.a",
381 		.data = (void *)&version_1_0_0},
382 	{},
383 };
384 MODULE_DEVICE_TABLE(of, axi_fan_control_of_match);
385 
386 static int axi_fan_control_probe(struct platform_device *pdev)
387 {
388 	struct axi_fan_control_data *ctl;
389 	struct clk *clk;
390 	const struct of_device_id *id;
391 	const char *name = "axi_fan_control";
392 	u32 version;
393 	int ret;
394 
395 	id = of_match_node(axi_fan_control_of_match, pdev->dev.of_node);
396 	if (!id)
397 		return -EINVAL;
398 
399 	ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL);
400 	if (!ctl)
401 		return -ENOMEM;
402 
403 	ctl->base = devm_platform_ioremap_resource(pdev, 0);
404 	if (IS_ERR(ctl->base))
405 		return PTR_ERR(ctl->base);
406 
407 	clk = devm_clk_get(&pdev->dev, NULL);
408 	if (IS_ERR(clk)) {
409 		dev_err(&pdev->dev, "clk_get failed with %ld\n", PTR_ERR(clk));
410 		return PTR_ERR(clk);
411 	}
412 
413 	ctl->clk_rate = clk_get_rate(clk);
414 	if (!ctl->clk_rate)
415 		return -EINVAL;
416 
417 	version = axi_ioread(ADI_AXI_REG_VERSION, ctl);
418 	if (ADI_AXI_PCORE_VER_MAJOR(version) !=
419 	    ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data))) {
420 		dev_err(&pdev->dev, "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
421 			ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data)),
422 			ADI_AXI_PCORE_VER_MINOR((*(u32 *)id->data)),
423 			ADI_AXI_PCORE_VER_PATCH((*(u32 *)id->data)),
424 			ADI_AXI_PCORE_VER_MAJOR(version),
425 			ADI_AXI_PCORE_VER_MINOR(version),
426 			ADI_AXI_PCORE_VER_PATCH(version));
427 		return -ENODEV;
428 	}
429 
430 	ctl->irq = platform_get_irq(pdev, 0);
431 	if (ctl->irq < 0)
432 		return ctl->irq;
433 
434 	ret = devm_request_threaded_irq(&pdev->dev, ctl->irq, NULL,
435 					axi_fan_control_irq_handler,
436 					IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
437 					pdev->driver_override, ctl);
438 	if (ret) {
439 		dev_err(&pdev->dev, "failed to request an irq, %d", ret);
440 		return ret;
441 	}
442 
443 	ret = axi_fan_control_init(ctl, pdev->dev.of_node);
444 	if (ret) {
445 		dev_err(&pdev->dev, "Failed to initialize device\n");
446 		return ret;
447 	}
448 
449 	ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev,
450 							 name,
451 							 ctl,
452 							 &axi_chip_info,
453 							 NULL);
454 
455 	return PTR_ERR_OR_ZERO(ctl->hdev);
456 }
457 
458 static struct platform_driver axi_fan_control_driver = {
459 	.driver = {
460 		.name = "axi_fan_control_driver",
461 		.of_match_table = axi_fan_control_of_match,
462 	},
463 	.probe = axi_fan_control_probe,
464 };
465 module_platform_driver(axi_fan_control_driver);
466 
467 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
468 MODULE_DESCRIPTION("Analog Devices Fan Control HDL CORE driver");
469 MODULE_LICENSE("GPL");
470