1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/errno.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/hwmon.h> 11 #include <linux/hwmon-sysfs.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/sysfs.h> 20 #include <linux/thermal.h> 21 22 /* ASPEED PWM & FAN Tach Register Definition */ 23 #define ASPEED_PTCR_CTRL 0x00 24 #define ASPEED_PTCR_CLK_CTRL 0x04 25 #define ASPEED_PTCR_DUTY0_CTRL 0x08 26 #define ASPEED_PTCR_DUTY1_CTRL 0x0c 27 #define ASPEED_PTCR_TYPEM_CTRL 0x10 28 #define ASPEED_PTCR_TYPEM_CTRL1 0x14 29 #define ASPEED_PTCR_TYPEN_CTRL 0x18 30 #define ASPEED_PTCR_TYPEN_CTRL1 0x1c 31 #define ASPEED_PTCR_TACH_SOURCE 0x20 32 #define ASPEED_PTCR_TRIGGER 0x28 33 #define ASPEED_PTCR_RESULT 0x2c 34 #define ASPEED_PTCR_INTR_CTRL 0x30 35 #define ASPEED_PTCR_INTR_STS 0x34 36 #define ASPEED_PTCR_TYPEM_LIMIT 0x38 37 #define ASPEED_PTCR_TYPEN_LIMIT 0x3C 38 #define ASPEED_PTCR_CTRL_EXT 0x40 39 #define ASPEED_PTCR_CLK_CTRL_EXT 0x44 40 #define ASPEED_PTCR_DUTY2_CTRL 0x48 41 #define ASPEED_PTCR_DUTY3_CTRL 0x4c 42 #define ASPEED_PTCR_TYPEO_CTRL 0x50 43 #define ASPEED_PTCR_TYPEO_CTRL1 0x54 44 #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60 45 #define ASPEED_PTCR_TYPEO_LIMIT 0x78 46 47 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */ 48 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15 49 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6 50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15)) 51 52 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14 53 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5 54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14)) 55 56 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13 57 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4 58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13)) 59 60 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12 61 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3 62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12)) 63 64 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x)) 65 66 #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11) 67 #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10) 68 #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9) 69 #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8) 70 71 #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1) 72 #define ASPEED_PTCR_CTRL_CLK_EN BIT(0) 73 74 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */ 75 /* TYPE N */ 76 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16) 77 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24 78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20 79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16 80 /* TYPE M */ 81 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0) 82 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8 83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4 84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0 85 86 /* 87 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control 88 * 0/1/2/3 register 89 */ 90 #define DUTY_CTRL_PWM2_FALL_POINT 24 91 #define DUTY_CTRL_PWM2_RISE_POINT 16 92 #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16) 93 #define DUTY_CTRL_PWM1_FALL_POINT 8 94 #define DUTY_CTRL_PWM1_RISE_POINT 0 95 #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0) 96 97 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */ 98 #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16)) 99 #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0) 100 #define TYPE_CTRL_FAN_PERIOD 16 101 #define TYPE_CTRL_FAN_MODE 4 102 #define TYPE_CTRL_FAN_DIVISION 1 103 #define TYPE_CTRL_FAN_TYPE_EN 1 104 105 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */ 106 /* bit [0,1] at 0x20, bit [2] at 0x60 */ 107 #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2) 108 #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2) 109 #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2)) 110 #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2) 111 112 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */ 113 #define RESULT_STATUS_MASK BIT(31) 114 #define RESULT_VALUE_MASK 0xfffff 115 116 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */ 117 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15 118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6 119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15)) 120 121 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14 122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5 123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14)) 124 125 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13 126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4 127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13)) 128 129 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12 130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3 131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12)) 132 133 #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11) 134 #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10) 135 #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9) 136 #define ASPEED_PTCR_CTRL_PWME_EN BIT(8) 137 138 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */ 139 /* TYPE O */ 140 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0) 141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8 142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4 143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0 144 145 #define PWM_MAX 255 146 147 #define BOTH_EDGES 0x02 /* 10b */ 148 149 #define M_PWM_DIV_H 0x00 150 #define M_PWM_DIV_L 0x05 151 #define M_PWM_PERIOD 0x5F 152 #define M_TACH_CLK_DIV 0x00 153 /* 154 * 5:4 Type N fan tach mode selection bit: 155 * 00: falling 156 * 01: rising 157 * 10: both 158 * 11: reserved. 159 */ 160 #define M_TACH_MODE 0x02 /* 10b */ 161 #define M_TACH_UNIT 0x0420 162 #define INIT_FAN_CTRL 0xFF 163 164 /* How long we sleep in us while waiting for an RPM result. */ 165 #define ASPEED_RPM_STATUS_SLEEP_USEC 500 166 167 #define MAX_CDEV_NAME_LEN 16 168 169 #define MAX_ASPEED_FAN_TACH_CHANNELS 16 170 171 struct aspeed_cooling_device { 172 char name[16]; 173 struct aspeed_pwm_tacho_data *priv; 174 struct thermal_cooling_device *tcdev; 175 int pwm_port; 176 u8 *cooling_levels; 177 u8 max_state; 178 u8 cur_state; 179 }; 180 181 struct aspeed_pwm_tacho_data { 182 struct regmap *regmap; 183 struct reset_control *rst; 184 unsigned long clk_freq; 185 bool pwm_present[8]; 186 bool fan_tach_present[MAX_ASPEED_FAN_TACH_CHANNELS]; 187 u8 type_pwm_clock_unit[3]; 188 u8 type_pwm_clock_division_h[3]; 189 u8 type_pwm_clock_division_l[3]; 190 u8 type_fan_tach_clock_division[3]; 191 u8 type_fan_tach_mode[3]; 192 u16 type_fan_tach_unit[3]; 193 u8 pwm_port_type[8]; 194 u8 pwm_port_fan_ctrl[8]; 195 u8 fan_tach_ch_source[MAX_ASPEED_FAN_TACH_CHANNELS]; 196 struct aspeed_cooling_device *cdev[8]; 197 const struct attribute_group *groups[3]; 198 }; 199 200 enum type { TYPEM, TYPEN, TYPEO }; 201 202 struct type_params { 203 u32 l_value; 204 u32 h_value; 205 u32 unit_value; 206 u32 clk_ctrl_mask; 207 u32 clk_ctrl_reg; 208 u32 ctrl_reg; 209 u32 ctrl_reg1; 210 }; 211 212 static const struct type_params type_params[] = { 213 [TYPEM] = { 214 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L, 215 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H, 216 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT, 217 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK, 218 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 219 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL, 220 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1, 221 }, 222 [TYPEN] = { 223 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L, 224 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H, 225 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT, 226 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK, 227 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 228 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL, 229 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1, 230 }, 231 [TYPEO] = { 232 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L, 233 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H, 234 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT, 235 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK, 236 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT, 237 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL, 238 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1, 239 } 240 }; 241 242 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH }; 243 244 struct pwm_port_params { 245 u32 pwm_en; 246 u32 ctrl_reg; 247 u32 type_part1; 248 u32 type_part2; 249 u32 type_mask; 250 u32 duty_ctrl_rise_point; 251 u32 duty_ctrl_fall_point; 252 u32 duty_ctrl_reg; 253 u32 duty_ctrl_rise_fall_mask; 254 }; 255 256 static const struct pwm_port_params pwm_port_params[] = { 257 [PWMA] = { 258 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN, 259 .ctrl_reg = ASPEED_PTCR_CTRL, 260 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1, 261 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2, 262 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK, 263 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 264 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 265 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 266 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 267 }, 268 [PWMB] = { 269 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN, 270 .ctrl_reg = ASPEED_PTCR_CTRL, 271 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1, 272 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2, 273 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK, 274 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 275 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 276 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 277 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 278 }, 279 [PWMC] = { 280 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN, 281 .ctrl_reg = ASPEED_PTCR_CTRL, 282 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1, 283 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2, 284 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK, 285 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 286 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 287 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 288 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 289 }, 290 [PWMD] = { 291 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN, 292 .ctrl_reg = ASPEED_PTCR_CTRL, 293 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1, 294 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2, 295 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK, 296 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 297 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 298 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 299 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 300 }, 301 [PWME] = { 302 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN, 303 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 304 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1, 305 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2, 306 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK, 307 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 308 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 309 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 310 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 311 }, 312 [PWMF] = { 313 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN, 314 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 315 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1, 316 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2, 317 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK, 318 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 319 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 320 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 321 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 322 }, 323 [PWMG] = { 324 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN, 325 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 326 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1, 327 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2, 328 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK, 329 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 330 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 331 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 332 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 333 }, 334 [PWMH] = { 335 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN, 336 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 337 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1, 338 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2, 339 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK, 340 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 341 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 342 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 343 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 344 } 345 }; 346 347 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg, 348 unsigned int val) 349 { 350 void __iomem *regs = (void __iomem *)context; 351 352 writel(val, regs + reg); 353 return 0; 354 } 355 356 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg, 357 unsigned int *val) 358 { 359 void __iomem *regs = (void __iomem *)context; 360 361 *val = readl(regs + reg); 362 return 0; 363 } 364 365 static const struct regmap_config aspeed_pwm_tacho_regmap_config = { 366 .reg_bits = 32, 367 .val_bits = 32, 368 .reg_stride = 4, 369 .max_register = ASPEED_PTCR_TYPEO_LIMIT, 370 .reg_write = regmap_aspeed_pwm_tacho_reg_write, 371 .reg_read = regmap_aspeed_pwm_tacho_reg_read, 372 .fast_io = true, 373 }; 374 375 static void aspeed_set_clock_enable(struct regmap *regmap, bool val) 376 { 377 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 378 ASPEED_PTCR_CTRL_CLK_EN, 379 val ? ASPEED_PTCR_CTRL_CLK_EN : 0); 380 } 381 382 static void aspeed_set_clock_source(struct regmap *regmap, int val) 383 { 384 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 385 ASPEED_PTCR_CTRL_CLK_SRC, 386 val ? ASPEED_PTCR_CTRL_CLK_SRC : 0); 387 } 388 389 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type, 390 u8 div_high, u8 div_low, u8 unit) 391 { 392 u32 reg_value = ((div_high << type_params[type].h_value) | 393 (div_low << type_params[type].l_value) | 394 (unit << type_params[type].unit_value)); 395 396 regmap_update_bits(regmap, type_params[type].clk_ctrl_reg, 397 type_params[type].clk_ctrl_mask, reg_value); 398 } 399 400 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port, 401 bool enable) 402 { 403 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 404 pwm_port_params[pwm_port].pwm_en, 405 enable ? pwm_port_params[pwm_port].pwm_en : 0); 406 } 407 408 static void aspeed_set_pwm_port_type(struct regmap *regmap, 409 u8 pwm_port, u8 type) 410 { 411 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1; 412 413 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2; 414 415 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 416 pwm_port_params[pwm_port].type_mask, reg_value); 417 } 418 419 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap, 420 u8 pwm_port, u8 rising, 421 u8 falling) 422 { 423 u32 reg_value = (rising << 424 pwm_port_params[pwm_port].duty_ctrl_rise_point); 425 reg_value |= (falling << 426 pwm_port_params[pwm_port].duty_ctrl_fall_point); 427 428 regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg, 429 pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask, 430 reg_value); 431 } 432 433 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type, 434 bool enable) 435 { 436 regmap_update_bits(regmap, type_params[type].ctrl_reg, 437 TYPE_CTRL_FAN_TYPE_EN, 438 enable ? TYPE_CTRL_FAN_TYPE_EN : 0); 439 } 440 441 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type, 442 u8 mode, u16 unit, u8 division) 443 { 444 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) | 445 (unit << TYPE_CTRL_FAN_PERIOD) | 446 (division << TYPE_CTRL_FAN_DIVISION)); 447 448 regmap_update_bits(regmap, type_params[type].ctrl_reg, 449 TYPE_CTRL_FAN_MASK, reg_value); 450 regmap_update_bits(regmap, type_params[type].ctrl_reg1, 451 TYPE_CTRL_FAN1_MASK, unit << 16); 452 } 453 454 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch, 455 bool enable) 456 { 457 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 458 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch), 459 enable ? 460 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0); 461 } 462 463 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch, 464 u8 fan_tach_ch_source) 465 { 466 u32 reg_value1 = ((fan_tach_ch_source & 0x3) << 467 TACH_PWM_SOURCE_BIT01(fan_tach_ch)); 468 u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) << 469 TACH_PWM_SOURCE_BIT2(fan_tach_ch)); 470 471 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE, 472 TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch), 473 reg_value1); 474 475 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 476 TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch), 477 reg_value2); 478 } 479 480 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv, 481 u8 index, u8 fan_ctrl) 482 { 483 u16 period, dc_time_on; 484 485 period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]]; 486 period += 1; 487 dc_time_on = (fan_ctrl * period) / PWM_MAX; 488 489 if (dc_time_on == 0) { 490 aspeed_set_pwm_port_enable(priv->regmap, index, false); 491 } else { 492 if (dc_time_on == period) 493 dc_time_on = 0; 494 495 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0, 496 dc_time_on); 497 aspeed_set_pwm_port_enable(priv->regmap, index, true); 498 } 499 } 500 501 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data 502 *priv, u8 type) 503 { 504 u32 clk; 505 u16 tacho_unit; 506 u8 clk_unit, div_h, div_l, tacho_div; 507 508 clk = priv->clk_freq; 509 clk_unit = priv->type_pwm_clock_unit[type]; 510 div_h = priv->type_pwm_clock_division_h[type]; 511 div_h = 0x1 << div_h; 512 div_l = priv->type_pwm_clock_division_l[type]; 513 if (div_l == 0) 514 div_l = 1; 515 else 516 div_l = div_l * 2; 517 518 tacho_unit = priv->type_fan_tach_unit[type]; 519 tacho_div = priv->type_fan_tach_clock_division[type]; 520 521 tacho_div = 0x4 << (tacho_div * 2); 522 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit); 523 } 524 525 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv, 526 u8 fan_tach_ch) 527 { 528 u32 raw_data, tach_div, clk_source, msec, usec, val; 529 u8 fan_tach_ch_source, type, mode, both; 530 int ret; 531 532 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0); 533 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch); 534 535 fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch]; 536 type = priv->pwm_port_type[fan_tach_ch_source]; 537 538 msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type)); 539 usec = msec * 1000; 540 541 ret = regmap_read_poll_timeout( 542 priv->regmap, 543 ASPEED_PTCR_RESULT, 544 val, 545 (val & RESULT_STATUS_MASK), 546 ASPEED_RPM_STATUS_SLEEP_USEC, 547 usec); 548 549 /* return -ETIMEDOUT if we didn't get an answer. */ 550 if (ret) 551 return ret; 552 553 raw_data = val & RESULT_VALUE_MASK; 554 tach_div = priv->type_fan_tach_clock_division[type]; 555 /* 556 * We need the mode to determine if the raw_data is double (from 557 * counting both edges). 558 */ 559 mode = priv->type_fan_tach_mode[type]; 560 both = (mode & BOTH_EDGES) ? 1 : 0; 561 562 tach_div = (0x4 << both) << (tach_div * 2); 563 clk_source = priv->clk_freq; 564 565 if (raw_data == 0) 566 return 0; 567 568 return (clk_source * 60) / (2 * raw_data * tach_div); 569 } 570 571 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr, 572 const char *buf, size_t count) 573 { 574 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 575 int index = sensor_attr->index; 576 int ret; 577 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 578 long fan_ctrl; 579 580 ret = kstrtol(buf, 10, &fan_ctrl); 581 if (ret != 0) 582 return ret; 583 584 if (fan_ctrl < 0 || fan_ctrl > PWM_MAX) 585 return -EINVAL; 586 587 if (priv->pwm_port_fan_ctrl[index] == fan_ctrl) 588 return count; 589 590 priv->pwm_port_fan_ctrl[index] = fan_ctrl; 591 aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl); 592 593 return count; 594 } 595 596 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr, 597 char *buf) 598 { 599 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 600 int index = sensor_attr->index; 601 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 602 603 return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]); 604 } 605 606 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr, 607 char *buf) 608 { 609 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 610 int index = sensor_attr->index; 611 int rpm; 612 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 613 614 rpm = aspeed_get_fan_tach_ch_rpm(priv, index); 615 if (rpm < 0) 616 return rpm; 617 618 return sprintf(buf, "%d\n", rpm); 619 } 620 621 static umode_t pwm_is_visible(struct kobject *kobj, 622 struct attribute *a, int index) 623 { 624 struct device *dev = kobj_to_dev(kobj); 625 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 626 627 if (!priv->pwm_present[index]) 628 return 0; 629 return a->mode; 630 } 631 632 static umode_t fan_dev_is_visible(struct kobject *kobj, 633 struct attribute *a, int index) 634 { 635 struct device *dev = kobj_to_dev(kobj); 636 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 637 638 if (!priv->fan_tach_present[index]) 639 return 0; 640 return a->mode; 641 } 642 643 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0); 644 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1); 645 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2); 646 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3); 647 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4); 648 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5); 649 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6); 650 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7); 651 static struct attribute *pwm_dev_attrs[] = { 652 &sensor_dev_attr_pwm1.dev_attr.attr, 653 &sensor_dev_attr_pwm2.dev_attr.attr, 654 &sensor_dev_attr_pwm3.dev_attr.attr, 655 &sensor_dev_attr_pwm4.dev_attr.attr, 656 &sensor_dev_attr_pwm5.dev_attr.attr, 657 &sensor_dev_attr_pwm6.dev_attr.attr, 658 &sensor_dev_attr_pwm7.dev_attr.attr, 659 &sensor_dev_attr_pwm8.dev_attr.attr, 660 NULL, 661 }; 662 663 static const struct attribute_group pwm_dev_group = { 664 .attrs = pwm_dev_attrs, 665 .is_visible = pwm_is_visible, 666 }; 667 668 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0); 669 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1); 670 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2); 671 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3); 672 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4); 673 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5); 674 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6); 675 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7); 676 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8); 677 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9); 678 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10); 679 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11); 680 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12); 681 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13); 682 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14); 683 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15); 684 static struct attribute *fan_dev_attrs[] = { 685 &sensor_dev_attr_fan1_input.dev_attr.attr, 686 &sensor_dev_attr_fan2_input.dev_attr.attr, 687 &sensor_dev_attr_fan3_input.dev_attr.attr, 688 &sensor_dev_attr_fan4_input.dev_attr.attr, 689 &sensor_dev_attr_fan5_input.dev_attr.attr, 690 &sensor_dev_attr_fan6_input.dev_attr.attr, 691 &sensor_dev_attr_fan7_input.dev_attr.attr, 692 &sensor_dev_attr_fan8_input.dev_attr.attr, 693 &sensor_dev_attr_fan9_input.dev_attr.attr, 694 &sensor_dev_attr_fan10_input.dev_attr.attr, 695 &sensor_dev_attr_fan11_input.dev_attr.attr, 696 &sensor_dev_attr_fan12_input.dev_attr.attr, 697 &sensor_dev_attr_fan13_input.dev_attr.attr, 698 &sensor_dev_attr_fan14_input.dev_attr.attr, 699 &sensor_dev_attr_fan15_input.dev_attr.attr, 700 &sensor_dev_attr_fan16_input.dev_attr.attr, 701 NULL 702 }; 703 704 static const struct attribute_group fan_dev_group = { 705 .attrs = fan_dev_attrs, 706 .is_visible = fan_dev_is_visible, 707 }; 708 709 /* 710 * The clock type is type M : 711 * The PWM frequency = 24MHz / (type M clock division L bit * 712 * type M clock division H bit * (type M PWM period bit + 1)) 713 */ 714 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv) 715 { 716 priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H; 717 priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L; 718 priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD; 719 aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H, 720 M_PWM_DIV_L, M_PWM_PERIOD); 721 aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true); 722 priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV; 723 priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT; 724 priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE; 725 aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE, 726 M_TACH_UNIT, M_TACH_CLK_DIV); 727 } 728 729 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv, 730 u8 pwm_port) 731 { 732 aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true); 733 priv->pwm_present[pwm_port] = true; 734 735 priv->pwm_port_type[pwm_port] = TYPEM; 736 aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM); 737 738 priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL; 739 aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL); 740 } 741 742 static int aspeed_create_fan_tach_channel(struct device *dev, 743 struct aspeed_pwm_tacho_data *priv, 744 u8 *fan_tach_ch, 745 int count, 746 u8 pwm_source) 747 { 748 u8 val, index; 749 750 for (val = 0; val < count; val++) { 751 index = fan_tach_ch[val]; 752 if (index >= MAX_ASPEED_FAN_TACH_CHANNELS) { 753 dev_err(dev, "Invalid Fan Tach input channel %u\n.", index); 754 return -EINVAL; 755 } 756 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true); 757 priv->fan_tach_present[index] = true; 758 priv->fan_tach_ch_source[index] = pwm_source; 759 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source); 760 } 761 762 return 0; 763 } 764 765 static int 766 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, 767 unsigned long *state) 768 { 769 struct aspeed_cooling_device *cdev = tcdev->devdata; 770 771 *state = cdev->max_state; 772 773 return 0; 774 } 775 776 static int 777 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, 778 unsigned long *state) 779 { 780 struct aspeed_cooling_device *cdev = tcdev->devdata; 781 782 *state = cdev->cur_state; 783 784 return 0; 785 } 786 787 static int 788 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, 789 unsigned long state) 790 { 791 struct aspeed_cooling_device *cdev = tcdev->devdata; 792 793 if (state > cdev->max_state) 794 return -EINVAL; 795 796 cdev->cur_state = state; 797 cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] = 798 cdev->cooling_levels[cdev->cur_state]; 799 aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port, 800 cdev->cooling_levels[cdev->cur_state]); 801 802 return 0; 803 } 804 805 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = { 806 .get_max_state = aspeed_pwm_cz_get_max_state, 807 .get_cur_state = aspeed_pwm_cz_get_cur_state, 808 .set_cur_state = aspeed_pwm_cz_set_cur_state, 809 }; 810 811 static int aspeed_create_pwm_cooling(struct device *dev, 812 struct device_node *child, 813 struct aspeed_pwm_tacho_data *priv, 814 u32 pwm_port, u8 num_levels) 815 { 816 int ret; 817 struct aspeed_cooling_device *cdev; 818 819 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); 820 821 if (!cdev) 822 return -ENOMEM; 823 824 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); 825 if (!cdev->cooling_levels) 826 return -ENOMEM; 827 828 cdev->max_state = num_levels - 1; 829 ret = of_property_read_u8_array(child, "cooling-levels", 830 cdev->cooling_levels, 831 num_levels); 832 if (ret) { 833 dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); 834 return ret; 835 } 836 snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port); 837 838 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, 839 cdev->name, cdev, &aspeed_pwm_cool_ops); 840 if (IS_ERR(cdev->tcdev)) 841 return PTR_ERR(cdev->tcdev); 842 843 cdev->priv = priv; 844 cdev->pwm_port = pwm_port; 845 846 priv->cdev[pwm_port] = cdev; 847 848 return 0; 849 } 850 851 static int aspeed_create_fan(struct device *dev, 852 struct device_node *child, 853 struct aspeed_pwm_tacho_data *priv) 854 { 855 u8 *fan_tach_ch; 856 u32 pwm_port; 857 int ret, count; 858 859 ret = of_property_read_u32(child, "reg", &pwm_port); 860 if (ret) 861 return ret; 862 if (pwm_port >= ARRAY_SIZE(pwm_port_params)) 863 return -EINVAL; 864 aspeed_create_pwm_port(priv, (u8)pwm_port); 865 866 ret = of_property_count_u8_elems(child, "cooling-levels"); 867 868 if (ret > 0) { 869 ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port, 870 ret); 871 if (ret) 872 return ret; 873 } 874 875 count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch"); 876 if (count < 1) 877 return -EINVAL; 878 fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch), 879 GFP_KERNEL); 880 if (!fan_tach_ch) 881 return -ENOMEM; 882 ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch", 883 fan_tach_ch, count); 884 if (ret) 885 return ret; 886 887 ret = aspeed_create_fan_tach_channel(dev, priv, fan_tach_ch, count, pwm_port); 888 if (ret) 889 return ret; 890 891 return 0; 892 } 893 894 static void aspeed_pwm_tacho_remove(void *data) 895 { 896 struct aspeed_pwm_tacho_data *priv = data; 897 898 reset_control_assert(priv->rst); 899 } 900 901 static int aspeed_pwm_tacho_probe(struct platform_device *pdev) 902 { 903 struct device *dev = &pdev->dev; 904 struct device_node *np, *child; 905 struct aspeed_pwm_tacho_data *priv; 906 void __iomem *regs; 907 struct device *hwmon; 908 struct clk *clk; 909 int ret; 910 911 np = dev->of_node; 912 regs = devm_platform_ioremap_resource(pdev, 0); 913 if (IS_ERR(regs)) 914 return PTR_ERR(regs); 915 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 916 if (!priv) 917 return -ENOMEM; 918 priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs, 919 &aspeed_pwm_tacho_regmap_config); 920 if (IS_ERR(priv->regmap)) 921 return PTR_ERR(priv->regmap); 922 923 priv->rst = devm_reset_control_get_exclusive(dev, NULL); 924 if (IS_ERR(priv->rst)) { 925 dev_err(dev, 926 "missing or invalid reset controller device tree entry"); 927 return PTR_ERR(priv->rst); 928 } 929 reset_control_deassert(priv->rst); 930 931 ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv); 932 if (ret) 933 return ret; 934 935 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0); 936 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0); 937 938 clk = devm_clk_get(dev, NULL); 939 if (IS_ERR(clk)) 940 return -ENODEV; 941 priv->clk_freq = clk_get_rate(clk); 942 aspeed_set_clock_enable(priv->regmap, true); 943 aspeed_set_clock_source(priv->regmap, 0); 944 945 aspeed_create_type(priv); 946 947 for_each_child_of_node(np, child) { 948 ret = aspeed_create_fan(dev, child, priv); 949 if (ret) { 950 of_node_put(child); 951 return ret; 952 } 953 } 954 955 priv->groups[0] = &pwm_dev_group; 956 priv->groups[1] = &fan_dev_group; 957 priv->groups[2] = NULL; 958 hwmon = devm_hwmon_device_register_with_groups(dev, 959 "aspeed_pwm_tacho", 960 priv, priv->groups); 961 return PTR_ERR_OR_ZERO(hwmon); 962 } 963 964 static const struct of_device_id of_pwm_tacho_match_table[] = { 965 { .compatible = "aspeed,ast2400-pwm-tacho", }, 966 { .compatible = "aspeed,ast2500-pwm-tacho", }, 967 {}, 968 }; 969 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table); 970 971 static struct platform_driver aspeed_pwm_tacho_driver = { 972 .probe = aspeed_pwm_tacho_probe, 973 .driver = { 974 .name = "aspeed_pwm_tacho", 975 .of_match_table = of_pwm_tacho_match_table, 976 }, 977 }; 978 979 module_platform_driver(aspeed_pwm_tacho_driver); 980 981 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>"); 982 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver"); 983 MODULE_LICENSE("GPL"); 984