1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/errno.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/hwmon.h> 11 #include <linux/hwmon-sysfs.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/sysfs.h> 20 #include <linux/thermal.h> 21 22 /* ASPEED PWM & FAN Tach Register Definition */ 23 #define ASPEED_PTCR_CTRL 0x00 24 #define ASPEED_PTCR_CLK_CTRL 0x04 25 #define ASPEED_PTCR_DUTY0_CTRL 0x08 26 #define ASPEED_PTCR_DUTY1_CTRL 0x0c 27 #define ASPEED_PTCR_TYPEM_CTRL 0x10 28 #define ASPEED_PTCR_TYPEM_CTRL1 0x14 29 #define ASPEED_PTCR_TYPEN_CTRL 0x18 30 #define ASPEED_PTCR_TYPEN_CTRL1 0x1c 31 #define ASPEED_PTCR_TACH_SOURCE 0x20 32 #define ASPEED_PTCR_TRIGGER 0x28 33 #define ASPEED_PTCR_RESULT 0x2c 34 #define ASPEED_PTCR_INTR_CTRL 0x30 35 #define ASPEED_PTCR_INTR_STS 0x34 36 #define ASPEED_PTCR_TYPEM_LIMIT 0x38 37 #define ASPEED_PTCR_TYPEN_LIMIT 0x3C 38 #define ASPEED_PTCR_CTRL_EXT 0x40 39 #define ASPEED_PTCR_CLK_CTRL_EXT 0x44 40 #define ASPEED_PTCR_DUTY2_CTRL 0x48 41 #define ASPEED_PTCR_DUTY3_CTRL 0x4c 42 #define ASPEED_PTCR_TYPEO_CTRL 0x50 43 #define ASPEED_PTCR_TYPEO_CTRL1 0x54 44 #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60 45 #define ASPEED_PTCR_TYPEO_LIMIT 0x78 46 47 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */ 48 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15 49 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6 50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15)) 51 52 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14 53 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5 54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14)) 55 56 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13 57 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4 58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13)) 59 60 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12 61 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3 62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12)) 63 64 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x)) 65 66 #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11) 67 #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10) 68 #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9) 69 #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8) 70 71 #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1) 72 #define ASPEED_PTCR_CTRL_CLK_EN BIT(0) 73 74 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */ 75 /* TYPE N */ 76 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16) 77 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24 78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20 79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16 80 /* TYPE M */ 81 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0) 82 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8 83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4 84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0 85 86 /* 87 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control 88 * 0/1/2/3 register 89 */ 90 #define DUTY_CTRL_PWM2_FALL_POINT 24 91 #define DUTY_CTRL_PWM2_RISE_POINT 16 92 #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16) 93 #define DUTY_CTRL_PWM1_FALL_POINT 8 94 #define DUTY_CTRL_PWM1_RISE_POINT 0 95 #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0) 96 97 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */ 98 #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16)) 99 #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0) 100 #define TYPE_CTRL_FAN_PERIOD 16 101 #define TYPE_CTRL_FAN_MODE 4 102 #define TYPE_CTRL_FAN_DIVISION 1 103 #define TYPE_CTRL_FAN_TYPE_EN 1 104 105 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */ 106 /* bit [0,1] at 0x20, bit [2] at 0x60 */ 107 #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2) 108 #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2) 109 #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2)) 110 #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2) 111 112 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */ 113 #define RESULT_STATUS_MASK BIT(31) 114 #define RESULT_VALUE_MASK 0xfffff 115 116 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */ 117 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15 118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6 119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15)) 120 121 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14 122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5 123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14)) 124 125 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13 126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4 127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13)) 128 129 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12 130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3 131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12)) 132 133 #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11) 134 #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10) 135 #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9) 136 #define ASPEED_PTCR_CTRL_PWME_EN BIT(8) 137 138 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */ 139 /* TYPE O */ 140 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0) 141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8 142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4 143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0 144 145 #define PWM_MAX 255 146 147 #define BOTH_EDGES 0x02 /* 10b */ 148 149 #define M_PWM_DIV_H 0x00 150 #define M_PWM_DIV_L 0x05 151 #define M_PWM_PERIOD 0x5F 152 #define M_TACH_CLK_DIV 0x00 153 /* 154 * 5:4 Type N fan tach mode selection bit: 155 * 00: falling 156 * 01: rising 157 * 10: both 158 * 11: reserved. 159 */ 160 #define M_TACH_MODE 0x02 /* 10b */ 161 #define M_TACH_UNIT 0x0420 162 #define INIT_FAN_CTRL 0xFF 163 164 /* How long we sleep in us while waiting for an RPM result. */ 165 #define ASPEED_RPM_STATUS_SLEEP_USEC 500 166 167 #define MAX_CDEV_NAME_LEN 16 168 169 #define MAX_ASPEED_FAN_TACH_CHANNELS 16 170 171 struct aspeed_cooling_device { 172 char name[16]; 173 struct aspeed_pwm_tacho_data *priv; 174 struct thermal_cooling_device *tcdev; 175 int pwm_port; 176 u8 *cooling_levels; 177 u8 max_state; 178 u8 cur_state; 179 }; 180 181 struct aspeed_pwm_tacho_data { 182 struct regmap *regmap; 183 struct reset_control *rst; 184 unsigned long clk_freq; 185 bool pwm_present[8]; 186 bool fan_tach_present[MAX_ASPEED_FAN_TACH_CHANNELS]; 187 u8 type_pwm_clock_unit[3]; 188 u8 type_pwm_clock_division_h[3]; 189 u8 type_pwm_clock_division_l[3]; 190 u8 type_fan_tach_clock_division[3]; 191 u8 type_fan_tach_mode[3]; 192 u16 type_fan_tach_unit[3]; 193 u8 pwm_port_type[8]; 194 u8 pwm_port_fan_ctrl[8]; 195 u8 fan_tach_ch_source[MAX_ASPEED_FAN_TACH_CHANNELS]; 196 struct aspeed_cooling_device *cdev[8]; 197 const struct attribute_group *groups[3]; 198 /* protects access to shared ASPEED_PTCR_RESULT */ 199 struct mutex tach_lock; 200 }; 201 202 enum type { TYPEM, TYPEN, TYPEO }; 203 204 struct type_params { 205 u32 l_value; 206 u32 h_value; 207 u32 unit_value; 208 u32 clk_ctrl_mask; 209 u32 clk_ctrl_reg; 210 u32 ctrl_reg; 211 u32 ctrl_reg1; 212 }; 213 214 static const struct type_params type_params[] = { 215 [TYPEM] = { 216 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L, 217 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H, 218 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT, 219 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK, 220 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 221 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL, 222 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1, 223 }, 224 [TYPEN] = { 225 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L, 226 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H, 227 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT, 228 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK, 229 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 230 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL, 231 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1, 232 }, 233 [TYPEO] = { 234 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L, 235 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H, 236 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT, 237 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK, 238 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT, 239 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL, 240 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1, 241 } 242 }; 243 244 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH }; 245 246 struct pwm_port_params { 247 u32 pwm_en; 248 u32 ctrl_reg; 249 u32 type_part1; 250 u32 type_part2; 251 u32 type_mask; 252 u32 duty_ctrl_rise_point; 253 u32 duty_ctrl_fall_point; 254 u32 duty_ctrl_reg; 255 u32 duty_ctrl_rise_fall_mask; 256 }; 257 258 static const struct pwm_port_params pwm_port_params[] = { 259 [PWMA] = { 260 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN, 261 .ctrl_reg = ASPEED_PTCR_CTRL, 262 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1, 263 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2, 264 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK, 265 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 266 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 267 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 268 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 269 }, 270 [PWMB] = { 271 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN, 272 .ctrl_reg = ASPEED_PTCR_CTRL, 273 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1, 274 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2, 275 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK, 276 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 277 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 278 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 279 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 280 }, 281 [PWMC] = { 282 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN, 283 .ctrl_reg = ASPEED_PTCR_CTRL, 284 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1, 285 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2, 286 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK, 287 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 288 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 289 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 290 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 291 }, 292 [PWMD] = { 293 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN, 294 .ctrl_reg = ASPEED_PTCR_CTRL, 295 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1, 296 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2, 297 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK, 298 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 299 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 300 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 301 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 302 }, 303 [PWME] = { 304 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN, 305 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 306 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1, 307 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2, 308 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK, 309 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 310 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 311 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 312 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 313 }, 314 [PWMF] = { 315 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN, 316 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 317 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1, 318 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2, 319 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK, 320 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 321 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 322 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 323 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 324 }, 325 [PWMG] = { 326 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN, 327 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 328 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1, 329 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2, 330 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK, 331 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 332 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 333 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 334 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 335 }, 336 [PWMH] = { 337 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN, 338 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 339 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1, 340 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2, 341 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK, 342 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 343 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 344 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 345 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 346 } 347 }; 348 349 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg, 350 unsigned int val) 351 { 352 void __iomem *regs = (void __iomem *)context; 353 354 writel(val, regs + reg); 355 return 0; 356 } 357 358 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg, 359 unsigned int *val) 360 { 361 void __iomem *regs = (void __iomem *)context; 362 363 *val = readl(regs + reg); 364 return 0; 365 } 366 367 static const struct regmap_config aspeed_pwm_tacho_regmap_config = { 368 .reg_bits = 32, 369 .val_bits = 32, 370 .reg_stride = 4, 371 .max_register = ASPEED_PTCR_TYPEO_LIMIT, 372 .reg_write = regmap_aspeed_pwm_tacho_reg_write, 373 .reg_read = regmap_aspeed_pwm_tacho_reg_read, 374 .fast_io = true, 375 }; 376 377 static void aspeed_set_clock_enable(struct regmap *regmap, bool val) 378 { 379 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 380 ASPEED_PTCR_CTRL_CLK_EN, 381 val ? ASPEED_PTCR_CTRL_CLK_EN : 0); 382 } 383 384 static void aspeed_set_clock_source(struct regmap *regmap, int val) 385 { 386 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 387 ASPEED_PTCR_CTRL_CLK_SRC, 388 val ? ASPEED_PTCR_CTRL_CLK_SRC : 0); 389 } 390 391 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type, 392 u8 div_high, u8 div_low, u8 unit) 393 { 394 u32 reg_value = ((div_high << type_params[type].h_value) | 395 (div_low << type_params[type].l_value) | 396 (unit << type_params[type].unit_value)); 397 398 regmap_update_bits(regmap, type_params[type].clk_ctrl_reg, 399 type_params[type].clk_ctrl_mask, reg_value); 400 } 401 402 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port, 403 bool enable) 404 { 405 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 406 pwm_port_params[pwm_port].pwm_en, 407 enable ? pwm_port_params[pwm_port].pwm_en : 0); 408 } 409 410 static void aspeed_set_pwm_port_type(struct regmap *regmap, 411 u8 pwm_port, u8 type) 412 { 413 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1; 414 415 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2; 416 417 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 418 pwm_port_params[pwm_port].type_mask, reg_value); 419 } 420 421 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap, 422 u8 pwm_port, u8 rising, 423 u8 falling) 424 { 425 u32 reg_value = (rising << 426 pwm_port_params[pwm_port].duty_ctrl_rise_point); 427 reg_value |= (falling << 428 pwm_port_params[pwm_port].duty_ctrl_fall_point); 429 430 regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg, 431 pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask, 432 reg_value); 433 } 434 435 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type, 436 bool enable) 437 { 438 regmap_update_bits(regmap, type_params[type].ctrl_reg, 439 TYPE_CTRL_FAN_TYPE_EN, 440 enable ? TYPE_CTRL_FAN_TYPE_EN : 0); 441 } 442 443 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type, 444 u8 mode, u16 unit, u8 division) 445 { 446 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) | 447 (unit << TYPE_CTRL_FAN_PERIOD) | 448 (division << TYPE_CTRL_FAN_DIVISION)); 449 450 regmap_update_bits(regmap, type_params[type].ctrl_reg, 451 TYPE_CTRL_FAN_MASK, reg_value); 452 regmap_update_bits(regmap, type_params[type].ctrl_reg1, 453 TYPE_CTRL_FAN1_MASK, unit << 16); 454 } 455 456 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch, 457 bool enable) 458 { 459 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 460 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch), 461 enable ? 462 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0); 463 } 464 465 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch, 466 u8 fan_tach_ch_source) 467 { 468 u32 reg_value1 = ((fan_tach_ch_source & 0x3) << 469 TACH_PWM_SOURCE_BIT01(fan_tach_ch)); 470 u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) << 471 TACH_PWM_SOURCE_BIT2(fan_tach_ch)); 472 473 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE, 474 TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch), 475 reg_value1); 476 477 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 478 TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch), 479 reg_value2); 480 } 481 482 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv, 483 u8 index, u8 fan_ctrl) 484 { 485 u16 period, dc_time_on; 486 487 period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]]; 488 period += 1; 489 dc_time_on = (fan_ctrl * period) / PWM_MAX; 490 491 if (dc_time_on == 0) { 492 aspeed_set_pwm_port_enable(priv->regmap, index, false); 493 } else { 494 if (dc_time_on == period) 495 dc_time_on = 0; 496 497 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0, 498 dc_time_on); 499 aspeed_set_pwm_port_enable(priv->regmap, index, true); 500 } 501 } 502 503 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data 504 *priv, u8 type) 505 { 506 u32 clk; 507 u16 tacho_unit; 508 u8 clk_unit, div_h, div_l, tacho_div; 509 510 clk = priv->clk_freq; 511 clk_unit = priv->type_pwm_clock_unit[type]; 512 div_h = priv->type_pwm_clock_division_h[type]; 513 div_h = 0x1 << div_h; 514 div_l = priv->type_pwm_clock_division_l[type]; 515 if (div_l == 0) 516 div_l = 1; 517 else 518 div_l = div_l * 2; 519 520 tacho_unit = priv->type_fan_tach_unit[type]; 521 tacho_div = priv->type_fan_tach_clock_division[type]; 522 523 tacho_div = 0x4 << (tacho_div * 2); 524 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit); 525 } 526 527 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv, 528 u8 fan_tach_ch) 529 { 530 u32 raw_data, tach_div, clk_source, msec, usec, val; 531 u8 fan_tach_ch_source, type, mode, both; 532 int ret; 533 534 mutex_lock(&priv->tach_lock); 535 536 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0); 537 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch); 538 539 fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch]; 540 type = priv->pwm_port_type[fan_tach_ch_source]; 541 542 msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type)); 543 usec = msec * 1000; 544 545 ret = regmap_read_poll_timeout( 546 priv->regmap, 547 ASPEED_PTCR_RESULT, 548 val, 549 (val & RESULT_STATUS_MASK), 550 ASPEED_RPM_STATUS_SLEEP_USEC, 551 usec); 552 553 mutex_unlock(&priv->tach_lock); 554 555 /* return -ETIMEDOUT if we didn't get an answer. */ 556 if (ret) 557 return ret; 558 559 raw_data = val & RESULT_VALUE_MASK; 560 tach_div = priv->type_fan_tach_clock_division[type]; 561 /* 562 * We need the mode to determine if the raw_data is double (from 563 * counting both edges). 564 */ 565 mode = priv->type_fan_tach_mode[type]; 566 both = (mode & BOTH_EDGES) ? 1 : 0; 567 568 tach_div = (0x4 << both) << (tach_div * 2); 569 clk_source = priv->clk_freq; 570 571 if (raw_data == 0) 572 return 0; 573 574 return (clk_source * 60) / (2 * raw_data * tach_div); 575 } 576 577 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr, 578 const char *buf, size_t count) 579 { 580 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 581 int index = sensor_attr->index; 582 int ret; 583 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 584 long fan_ctrl; 585 586 ret = kstrtol(buf, 10, &fan_ctrl); 587 if (ret != 0) 588 return ret; 589 590 if (fan_ctrl < 0 || fan_ctrl > PWM_MAX) 591 return -EINVAL; 592 593 if (priv->pwm_port_fan_ctrl[index] == fan_ctrl) 594 return count; 595 596 priv->pwm_port_fan_ctrl[index] = fan_ctrl; 597 aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl); 598 599 return count; 600 } 601 602 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr, 603 char *buf) 604 { 605 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 606 int index = sensor_attr->index; 607 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 608 609 return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]); 610 } 611 612 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr, 613 char *buf) 614 { 615 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 616 int index = sensor_attr->index; 617 int rpm; 618 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 619 620 rpm = aspeed_get_fan_tach_ch_rpm(priv, index); 621 if (rpm < 0) 622 return rpm; 623 624 return sprintf(buf, "%d\n", rpm); 625 } 626 627 static umode_t pwm_is_visible(struct kobject *kobj, 628 struct attribute *a, int index) 629 { 630 struct device *dev = kobj_to_dev(kobj); 631 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 632 633 if (!priv->pwm_present[index]) 634 return 0; 635 return a->mode; 636 } 637 638 static umode_t fan_dev_is_visible(struct kobject *kobj, 639 struct attribute *a, int index) 640 { 641 struct device *dev = kobj_to_dev(kobj); 642 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 643 644 if (!priv->fan_tach_present[index]) 645 return 0; 646 return a->mode; 647 } 648 649 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0); 650 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1); 651 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2); 652 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3); 653 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4); 654 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5); 655 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6); 656 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7); 657 static struct attribute *pwm_dev_attrs[] = { 658 &sensor_dev_attr_pwm1.dev_attr.attr, 659 &sensor_dev_attr_pwm2.dev_attr.attr, 660 &sensor_dev_attr_pwm3.dev_attr.attr, 661 &sensor_dev_attr_pwm4.dev_attr.attr, 662 &sensor_dev_attr_pwm5.dev_attr.attr, 663 &sensor_dev_attr_pwm6.dev_attr.attr, 664 &sensor_dev_attr_pwm7.dev_attr.attr, 665 &sensor_dev_attr_pwm8.dev_attr.attr, 666 NULL, 667 }; 668 669 static const struct attribute_group pwm_dev_group = { 670 .attrs = pwm_dev_attrs, 671 .is_visible = pwm_is_visible, 672 }; 673 674 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0); 675 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1); 676 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2); 677 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3); 678 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4); 679 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5); 680 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6); 681 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7); 682 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8); 683 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9); 684 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10); 685 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11); 686 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12); 687 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13); 688 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14); 689 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15); 690 static struct attribute *fan_dev_attrs[] = { 691 &sensor_dev_attr_fan1_input.dev_attr.attr, 692 &sensor_dev_attr_fan2_input.dev_attr.attr, 693 &sensor_dev_attr_fan3_input.dev_attr.attr, 694 &sensor_dev_attr_fan4_input.dev_attr.attr, 695 &sensor_dev_attr_fan5_input.dev_attr.attr, 696 &sensor_dev_attr_fan6_input.dev_attr.attr, 697 &sensor_dev_attr_fan7_input.dev_attr.attr, 698 &sensor_dev_attr_fan8_input.dev_attr.attr, 699 &sensor_dev_attr_fan9_input.dev_attr.attr, 700 &sensor_dev_attr_fan10_input.dev_attr.attr, 701 &sensor_dev_attr_fan11_input.dev_attr.attr, 702 &sensor_dev_attr_fan12_input.dev_attr.attr, 703 &sensor_dev_attr_fan13_input.dev_attr.attr, 704 &sensor_dev_attr_fan14_input.dev_attr.attr, 705 &sensor_dev_attr_fan15_input.dev_attr.attr, 706 &sensor_dev_attr_fan16_input.dev_attr.attr, 707 NULL 708 }; 709 710 static const struct attribute_group fan_dev_group = { 711 .attrs = fan_dev_attrs, 712 .is_visible = fan_dev_is_visible, 713 }; 714 715 /* 716 * The clock type is type M : 717 * The PWM frequency = 24MHz / (type M clock division L bit * 718 * type M clock division H bit * (type M PWM period bit + 1)) 719 */ 720 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv) 721 { 722 priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H; 723 priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L; 724 priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD; 725 aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H, 726 M_PWM_DIV_L, M_PWM_PERIOD); 727 aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true); 728 priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV; 729 priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT; 730 priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE; 731 aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE, 732 M_TACH_UNIT, M_TACH_CLK_DIV); 733 } 734 735 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv, 736 u8 pwm_port) 737 { 738 aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true); 739 priv->pwm_present[pwm_port] = true; 740 741 priv->pwm_port_type[pwm_port] = TYPEM; 742 aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM); 743 744 priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL; 745 aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL); 746 } 747 748 static int aspeed_create_fan_tach_channel(struct device *dev, 749 struct aspeed_pwm_tacho_data *priv, 750 u8 *fan_tach_ch, 751 int count, 752 u8 pwm_source) 753 { 754 u8 val, index; 755 756 for (val = 0; val < count; val++) { 757 index = fan_tach_ch[val]; 758 if (index >= MAX_ASPEED_FAN_TACH_CHANNELS) { 759 dev_err(dev, "Invalid Fan Tach input channel %u\n.", index); 760 return -EINVAL; 761 } 762 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true); 763 priv->fan_tach_present[index] = true; 764 priv->fan_tach_ch_source[index] = pwm_source; 765 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source); 766 } 767 768 return 0; 769 } 770 771 static int 772 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, 773 unsigned long *state) 774 { 775 struct aspeed_cooling_device *cdev = tcdev->devdata; 776 777 *state = cdev->max_state; 778 779 return 0; 780 } 781 782 static int 783 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, 784 unsigned long *state) 785 { 786 struct aspeed_cooling_device *cdev = tcdev->devdata; 787 788 *state = cdev->cur_state; 789 790 return 0; 791 } 792 793 static int 794 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, 795 unsigned long state) 796 { 797 struct aspeed_cooling_device *cdev = tcdev->devdata; 798 799 if (state > cdev->max_state) 800 return -EINVAL; 801 802 cdev->cur_state = state; 803 cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] = 804 cdev->cooling_levels[cdev->cur_state]; 805 aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port, 806 cdev->cooling_levels[cdev->cur_state]); 807 808 return 0; 809 } 810 811 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = { 812 .get_max_state = aspeed_pwm_cz_get_max_state, 813 .get_cur_state = aspeed_pwm_cz_get_cur_state, 814 .set_cur_state = aspeed_pwm_cz_set_cur_state, 815 }; 816 817 static int aspeed_create_pwm_cooling(struct device *dev, 818 struct device_node *child, 819 struct aspeed_pwm_tacho_data *priv, 820 u32 pwm_port, u8 num_levels) 821 { 822 int ret; 823 struct aspeed_cooling_device *cdev; 824 825 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); 826 827 if (!cdev) 828 return -ENOMEM; 829 830 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); 831 if (!cdev->cooling_levels) 832 return -ENOMEM; 833 834 cdev->max_state = num_levels - 1; 835 ret = of_property_read_u8_array(child, "cooling-levels", 836 cdev->cooling_levels, 837 num_levels); 838 if (ret) { 839 dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); 840 return ret; 841 } 842 snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port); 843 844 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, 845 cdev->name, cdev, &aspeed_pwm_cool_ops); 846 if (IS_ERR(cdev->tcdev)) 847 return PTR_ERR(cdev->tcdev); 848 849 cdev->priv = priv; 850 cdev->pwm_port = pwm_port; 851 852 priv->cdev[pwm_port] = cdev; 853 854 return 0; 855 } 856 857 static int aspeed_create_fan(struct device *dev, 858 struct device_node *child, 859 struct aspeed_pwm_tacho_data *priv) 860 { 861 u8 *fan_tach_ch; 862 u32 pwm_port; 863 int ret, count; 864 865 ret = of_property_read_u32(child, "reg", &pwm_port); 866 if (ret) 867 return ret; 868 if (pwm_port >= ARRAY_SIZE(pwm_port_params)) 869 return -EINVAL; 870 aspeed_create_pwm_port(priv, (u8)pwm_port); 871 872 ret = of_property_count_u8_elems(child, "cooling-levels"); 873 874 if (ret > 0) { 875 ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port, 876 ret); 877 if (ret) 878 return ret; 879 } 880 881 count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch"); 882 if (count < 1) 883 return -EINVAL; 884 fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch), 885 GFP_KERNEL); 886 if (!fan_tach_ch) 887 return -ENOMEM; 888 ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch", 889 fan_tach_ch, count); 890 if (ret) 891 return ret; 892 893 ret = aspeed_create_fan_tach_channel(dev, priv, fan_tach_ch, count, pwm_port); 894 if (ret) 895 return ret; 896 897 return 0; 898 } 899 900 static void aspeed_pwm_tacho_remove(void *data) 901 { 902 struct aspeed_pwm_tacho_data *priv = data; 903 904 reset_control_assert(priv->rst); 905 } 906 907 static int aspeed_pwm_tacho_probe(struct platform_device *pdev) 908 { 909 struct device *dev = &pdev->dev; 910 struct device_node *np, *child; 911 struct aspeed_pwm_tacho_data *priv; 912 void __iomem *regs; 913 struct device *hwmon; 914 struct clk *clk; 915 int ret; 916 917 np = dev->of_node; 918 regs = devm_platform_ioremap_resource(pdev, 0); 919 if (IS_ERR(regs)) 920 return PTR_ERR(regs); 921 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 922 if (!priv) 923 return -ENOMEM; 924 mutex_init(&priv->tach_lock); 925 priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs, 926 &aspeed_pwm_tacho_regmap_config); 927 if (IS_ERR(priv->regmap)) 928 return PTR_ERR(priv->regmap); 929 930 priv->rst = devm_reset_control_get_exclusive(dev, NULL); 931 if (IS_ERR(priv->rst)) { 932 dev_err(dev, 933 "missing or invalid reset controller device tree entry"); 934 return PTR_ERR(priv->rst); 935 } 936 reset_control_deassert(priv->rst); 937 938 ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv); 939 if (ret) 940 return ret; 941 942 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0); 943 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0); 944 945 clk = devm_clk_get(dev, NULL); 946 if (IS_ERR(clk)) 947 return -ENODEV; 948 priv->clk_freq = clk_get_rate(clk); 949 aspeed_set_clock_enable(priv->regmap, true); 950 aspeed_set_clock_source(priv->regmap, 0); 951 952 aspeed_create_type(priv); 953 954 for_each_child_of_node(np, child) { 955 ret = aspeed_create_fan(dev, child, priv); 956 if (ret) { 957 of_node_put(child); 958 return ret; 959 } 960 } 961 962 priv->groups[0] = &pwm_dev_group; 963 priv->groups[1] = &fan_dev_group; 964 priv->groups[2] = NULL; 965 hwmon = devm_hwmon_device_register_with_groups(dev, 966 "aspeed_pwm_tacho", 967 priv, priv->groups); 968 return PTR_ERR_OR_ZERO(hwmon); 969 } 970 971 static const struct of_device_id of_pwm_tacho_match_table[] = { 972 { .compatible = "aspeed,ast2400-pwm-tacho", }, 973 { .compatible = "aspeed,ast2500-pwm-tacho", }, 974 {}, 975 }; 976 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table); 977 978 static struct platform_driver aspeed_pwm_tacho_driver = { 979 .probe = aspeed_pwm_tacho_probe, 980 .driver = { 981 .name = "aspeed_pwm_tacho", 982 .of_match_table = of_pwm_tacho_match_table, 983 }, 984 }; 985 986 module_platform_driver(aspeed_pwm_tacho_driver); 987 988 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>"); 989 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver"); 990 MODULE_LICENSE("GPL"); 991