1 /* 2 abituguru3.c 3 4 Copyright (c) 2006-2008 Hans de Goede <j.w.r.degoede@hhs.nl> 5 Copyright (c) 2008 Alistair John Strachan <alistair@devzero.co.uk> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 /* 22 This driver supports the sensor part of revision 3 of the custom Abit uGuru 23 chip found on newer Abit uGuru motherboards. Note: because of lack of specs 24 only reading the sensors and their settings is supported. 25 */ 26 #include <linux/module.h> 27 #include <linux/init.h> 28 #include <linux/slab.h> 29 #include <linux/jiffies.h> 30 #include <linux/mutex.h> 31 #include <linux/err.h> 32 #include <linux/delay.h> 33 #include <linux/platform_device.h> 34 #include <linux/hwmon.h> 35 #include <linux/hwmon-sysfs.h> 36 #include <linux/dmi.h> 37 #include <asm/io.h> 38 39 /* uGuru3 bank addresses */ 40 #define ABIT_UGURU3_SETTINGS_BANK 0x01 41 #define ABIT_UGURU3_SENSORS_BANK 0x08 42 #define ABIT_UGURU3_MISC_BANK 0x09 43 #define ABIT_UGURU3_ALARMS_START 0x1E 44 #define ABIT_UGURU3_SETTINGS_START 0x24 45 #define ABIT_UGURU3_VALUES_START 0x80 46 #define ABIT_UGURU3_BOARD_ID 0x0A 47 /* uGuru3 sensor bank flags */ /* Alarm if: */ 48 #define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */ 49 #define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */ 50 #define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */ 51 #define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */ 52 #define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */ 53 #define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */ 54 #define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */ 55 #define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */ 56 #define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */ 57 /* sensor types */ 58 #define ABIT_UGURU3_IN_SENSOR 0 59 #define ABIT_UGURU3_TEMP_SENSOR 1 60 #define ABIT_UGURU3_FAN_SENSOR 2 61 62 /* Timeouts / Retries, if these turn out to need a lot of fiddling we could 63 convert them to params. Determined by trial and error. I assume this is 64 cpu-speed independent, since the ISA-bus and not the CPU should be the 65 bottleneck. */ 66 #define ABIT_UGURU3_WAIT_TIMEOUT 250 67 /* Normally the 0xAC at the end of synchronize() is reported after the 68 first read, but sometimes not and we need to poll */ 69 #define ABIT_UGURU3_SYNCHRONIZE_TIMEOUT 5 70 /* utility macros */ 71 #define ABIT_UGURU3_NAME "abituguru3" 72 #define ABIT_UGURU3_DEBUG(format, arg...) \ 73 if (verbose) \ 74 printk(KERN_DEBUG ABIT_UGURU3_NAME ": " format , ## arg) 75 76 /* Macros to help calculate the sysfs_names array length */ 77 #define ABIT_UGURU3_MAX_NO_SENSORS 26 78 /* sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0, 79 in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0 */ 80 #define ABIT_UGURU3_IN_NAMES_LENGTH (11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11) 81 /* sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0, 82 temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0, 83 temp??_label\0 */ 84 #define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13) 85 /* sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0, 86 fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0 */ 87 #define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12) 88 /* Worst case scenario 16 in sensors (longest names_length) and the rest 89 temp sensors (second longest names_length). */ 90 #define ABIT_UGURU3_SYSFS_NAMES_LENGTH (16 * ABIT_UGURU3_IN_NAMES_LENGTH + \ 91 (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH) 92 93 /* All the macros below are named identical to the openguru2 program 94 reverse engineered by Louis Kruger, hence the names might not be 100% 95 logical. I could come up with better names, but I prefer keeping the names 96 identical so that this driver can be compared with his work more easily. */ 97 /* Two i/o-ports are used by uGuru */ 98 #define ABIT_UGURU3_BASE 0x00E0 99 #define ABIT_UGURU3_CMD 0x00 100 #define ABIT_UGURU3_DATA 0x04 101 #define ABIT_UGURU3_REGION_LENGTH 5 102 /* The wait_xxx functions return this on success and the last contents 103 of the DATA register (0-255) on failure. */ 104 #define ABIT_UGURU3_SUCCESS -1 105 /* uGuru status flags */ 106 #define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01 107 #define ABIT_UGURU3_STATUS_BUSY 0x02 108 109 110 /* Structures */ 111 struct abituguru3_sensor_info { 112 const char* name; 113 int port; 114 int type; 115 int multiplier; 116 int divisor; 117 int offset; 118 }; 119 120 struct abituguru3_motherboard_info { 121 u16 id; 122 const char *dmi_name; 123 /* + 1 -> end of sensors indicated by a sensor with name == NULL */ 124 struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1]; 125 }; 126 127 /* For the Abit uGuru, we need to keep some data in memory. 128 The structure is dynamically allocated, at the same time when a new 129 abituguru3 device is allocated. */ 130 struct abituguru3_data { 131 struct device *hwmon_dev; /* hwmon registered device */ 132 struct mutex update_lock; /* protect access to data and uGuru */ 133 unsigned short addr; /* uguru base address */ 134 char valid; /* !=0 if following fields are valid */ 135 unsigned long last_updated; /* In jiffies */ 136 137 /* For convenience the sysfs attr and their names are generated 138 automatically. We have max 10 entries per sensor (for in sensors) */ 139 struct sensor_device_attribute_2 sysfs_attr[ABIT_UGURU3_MAX_NO_SENSORS 140 * 10]; 141 142 /* Buffer to store the dynamically generated sysfs names */ 143 char sysfs_names[ABIT_UGURU3_SYSFS_NAMES_LENGTH]; 144 145 /* Pointer to the sensors info for the detected motherboard */ 146 const struct abituguru3_sensor_info *sensors; 147 148 /* The abituguru3 supports upto 48 sensors, and thus has registers 149 sets for 48 sensors, for convienence reasons / simplicity of the 150 code we always read and store all registers for all 48 sensors */ 151 152 /* Alarms for all 48 sensors (1 bit per sensor) */ 153 u8 alarms[48/8]; 154 155 /* Value of all 48 sensors */ 156 u8 value[48]; 157 158 /* Settings of all 48 sensors, note in and temp sensors (the first 32 159 sensors) have 3 bytes of settings, while fans only have 2 bytes, 160 for convenience we use 3 bytes for all sensors */ 161 u8 settings[48][3]; 162 }; 163 164 165 /* Constants */ 166 static const struct abituguru3_motherboard_info abituguru3_motherboards[] = { 167 { 0x000C, NULL /* Unknown, need DMI string */, { 168 { "CPU Core", 0, 0, 10, 1, 0 }, 169 { "DDR", 1, 0, 10, 1, 0 }, 170 { "DDR VTT", 2, 0, 10, 1, 0 }, 171 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 172 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 173 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 174 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 175 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 176 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 177 { "ATX +5V", 9, 0, 30, 1, 0 }, 178 { "+3.3V", 10, 0, 20, 1, 0 }, 179 { "5VSB", 11, 0, 30, 1, 0 }, 180 { "CPU", 24, 1, 1, 1, 0 }, 181 { "System ", 25, 1, 1, 1, 0 }, 182 { "PWM", 26, 1, 1, 1, 0 }, 183 { "CPU Fan", 32, 2, 60, 1, 0 }, 184 { "NB Fan", 33, 2, 60, 1, 0 }, 185 { "SYS FAN", 34, 2, 60, 1, 0 }, 186 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 187 { NULL, 0, 0, 0, 0, 0 } } 188 }, 189 { 0x000D, NULL /* Abit AW8, need DMI string */, { 190 { "CPU Core", 0, 0, 10, 1, 0 }, 191 { "DDR", 1, 0, 10, 1, 0 }, 192 { "DDR VTT", 2, 0, 10, 1, 0 }, 193 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 194 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 195 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 196 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 197 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 198 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 199 { "ATX +5V", 9, 0, 30, 1, 0 }, 200 { "+3.3V", 10, 0, 20, 1, 0 }, 201 { "5VSB", 11, 0, 30, 1, 0 }, 202 { "CPU", 24, 1, 1, 1, 0 }, 203 { "System ", 25, 1, 1, 1, 0 }, 204 { "PWM1", 26, 1, 1, 1, 0 }, 205 { "PWM2", 27, 1, 1, 1, 0 }, 206 { "PWM3", 28, 1, 1, 1, 0 }, 207 { "PWM4", 29, 1, 1, 1, 0 }, 208 { "CPU Fan", 32, 2, 60, 1, 0 }, 209 { "NB Fan", 33, 2, 60, 1, 0 }, 210 { "SYS Fan", 34, 2, 60, 1, 0 }, 211 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 212 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 213 { "AUX3 Fan", 37, 2, 60, 1, 0 }, 214 { "AUX4 Fan", 38, 2, 60, 1, 0 }, 215 { "AUX5 Fan", 39, 2, 60, 1, 0 }, 216 { NULL, 0, 0, 0, 0, 0 } } 217 }, 218 { 0x000E, NULL /* AL-8, need DMI string */, { 219 { "CPU Core", 0, 0, 10, 1, 0 }, 220 { "DDR", 1, 0, 10, 1, 0 }, 221 { "DDR VTT", 2, 0, 10, 1, 0 }, 222 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 223 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 224 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 225 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 226 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 227 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 228 { "ATX +5V", 9, 0, 30, 1, 0 }, 229 { "+3.3V", 10, 0, 20, 1, 0 }, 230 { "5VSB", 11, 0, 30, 1, 0 }, 231 { "CPU", 24, 1, 1, 1, 0 }, 232 { "System ", 25, 1, 1, 1, 0 }, 233 { "PWM", 26, 1, 1, 1, 0 }, 234 { "CPU Fan", 32, 2, 60, 1, 0 }, 235 { "NB Fan", 33, 2, 60, 1, 0 }, 236 { "SYS Fan", 34, 2, 60, 1, 0 }, 237 { NULL, 0, 0, 0, 0, 0 } } 238 }, 239 { 0x000F, NULL /* Unknown, need DMI string */, { 240 { "CPU Core", 0, 0, 10, 1, 0 }, 241 { "DDR", 1, 0, 10, 1, 0 }, 242 { "DDR VTT", 2, 0, 10, 1, 0 }, 243 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 244 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 245 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 246 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 247 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 248 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 249 { "ATX +5V", 9, 0, 30, 1, 0 }, 250 { "+3.3V", 10, 0, 20, 1, 0 }, 251 { "5VSB", 11, 0, 30, 1, 0 }, 252 { "CPU", 24, 1, 1, 1, 0 }, 253 { "System ", 25, 1, 1, 1, 0 }, 254 { "PWM", 26, 1, 1, 1, 0 }, 255 { "CPU Fan", 32, 2, 60, 1, 0 }, 256 { "NB Fan", 33, 2, 60, 1, 0 }, 257 { "SYS Fan", 34, 2, 60, 1, 0 }, 258 { NULL, 0, 0, 0, 0, 0 } } 259 }, 260 { 0x0010, NULL /* Abit NI8 SLI GR, need DMI string */, { 261 { "CPU Core", 0, 0, 10, 1, 0 }, 262 { "DDR", 1, 0, 10, 1, 0 }, 263 { "DDR VTT", 2, 0, 10, 1, 0 }, 264 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 265 { "NB 1.4V", 4, 0, 10, 1, 0 }, 266 { "SB 1.5V", 6, 0, 10, 1, 0 }, 267 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 268 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 269 { "ATX +5V", 9, 0, 30, 1, 0 }, 270 { "+3.3V", 10, 0, 20, 1, 0 }, 271 { "5VSB", 11, 0, 30, 1, 0 }, 272 { "CPU", 24, 1, 1, 1, 0 }, 273 { "SYS", 25, 1, 1, 1, 0 }, 274 { "PWM", 26, 1, 1, 1, 0 }, 275 { "CPU Fan", 32, 2, 60, 1, 0 }, 276 { "NB Fan", 33, 2, 60, 1, 0 }, 277 { "SYS Fan", 34, 2, 60, 1, 0 }, 278 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 279 { "OTES1 Fan", 36, 2, 60, 1, 0 }, 280 { NULL, 0, 0, 0, 0, 0 } } 281 }, 282 { 0x0011, NULL /* Abit AT8 32X, need DMI string */, { 283 { "CPU Core", 0, 0, 10, 1, 0 }, 284 { "DDR", 1, 0, 20, 1, 0 }, 285 { "DDR VTT", 2, 0, 10, 1, 0 }, 286 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 }, 287 { "NB 1.8V", 4, 0, 10, 1, 0 }, 288 { "NB 1.8V Dual", 5, 0, 10, 1, 0 }, 289 { "HTV 1.2", 3, 0, 10, 1, 0 }, 290 { "PCIE 1.2V", 12, 0, 10, 1, 0 }, 291 { "NB 1.2V", 13, 0, 10, 1, 0 }, 292 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 293 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 294 { "ATX +5V", 9, 0, 30, 1, 0 }, 295 { "+3.3V", 10, 0, 20, 1, 0 }, 296 { "5VSB", 11, 0, 30, 1, 0 }, 297 { "CPU", 24, 1, 1, 1, 0 }, 298 { "NB", 25, 1, 1, 1, 0 }, 299 { "System", 26, 1, 1, 1, 0 }, 300 { "PWM", 27, 1, 1, 1, 0 }, 301 { "CPU Fan", 32, 2, 60, 1, 0 }, 302 { "NB Fan", 33, 2, 60, 1, 0 }, 303 { "SYS Fan", 34, 2, 60, 1, 0 }, 304 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 305 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 306 { NULL, 0, 0, 0, 0, 0 } } 307 }, 308 { 0x0012, NULL /* Abit AN8 32X, need DMI string */, { 309 { "CPU Core", 0, 0, 10, 1, 0 }, 310 { "DDR", 1, 0, 20, 1, 0 }, 311 { "DDR VTT", 2, 0, 10, 1, 0 }, 312 { "HyperTransport", 3, 0, 10, 1, 0 }, 313 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 }, 314 { "NB", 4, 0, 10, 1, 0 }, 315 { "SB", 6, 0, 10, 1, 0 }, 316 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 317 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 318 { "ATX +5V", 9, 0, 30, 1, 0 }, 319 { "+3.3V", 10, 0, 20, 1, 0 }, 320 { "5VSB", 11, 0, 30, 1, 0 }, 321 { "CPU", 24, 1, 1, 1, 0 }, 322 { "SYS", 25, 1, 1, 1, 0 }, 323 { "PWM", 26, 1, 1, 1, 0 }, 324 { "CPU Fan", 32, 2, 60, 1, 0 }, 325 { "NB Fan", 33, 2, 60, 1, 0 }, 326 { "SYS Fan", 34, 2, 60, 1, 0 }, 327 { "AUX1 Fan", 36, 2, 60, 1, 0 }, 328 { NULL, 0, 0, 0, 0, 0 } } 329 }, 330 { 0x0013, NULL /* Abit AW8D, need DMI string */, { 331 { "CPU Core", 0, 0, 10, 1, 0 }, 332 { "DDR", 1, 0, 10, 1, 0 }, 333 { "DDR VTT", 2, 0, 10, 1, 0 }, 334 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 335 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 336 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 337 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 338 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 339 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 340 { "ATX +5V", 9, 0, 30, 1, 0 }, 341 { "+3.3V", 10, 0, 20, 1, 0 }, 342 { "5VSB", 11, 0, 30, 1, 0 }, 343 { "CPU", 24, 1, 1, 1, 0 }, 344 { "System ", 25, 1, 1, 1, 0 }, 345 { "PWM1", 26, 1, 1, 1, 0 }, 346 { "PWM2", 27, 1, 1, 1, 0 }, 347 { "PWM3", 28, 1, 1, 1, 0 }, 348 { "PWM4", 29, 1, 1, 1, 0 }, 349 { "CPU Fan", 32, 2, 60, 1, 0 }, 350 { "NB Fan", 33, 2, 60, 1, 0 }, 351 { "SYS Fan", 34, 2, 60, 1, 0 }, 352 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 353 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 354 { "AUX3 Fan", 37, 2, 60, 1, 0 }, 355 { "AUX4 Fan", 38, 2, 60, 1, 0 }, 356 { "AUX5 Fan", 39, 2, 60, 1, 0 }, 357 { NULL, 0, 0, 0, 0, 0 } } 358 }, 359 { 0x0014, NULL /* Abit AB9 Pro, need DMI string */, { 360 { "CPU Core", 0, 0, 10, 1, 0 }, 361 { "DDR", 1, 0, 10, 1, 0 }, 362 { "DDR VTT", 2, 0, 10, 1, 0 }, 363 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 364 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 365 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 366 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 367 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 368 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 369 { "ATX +5V", 9, 0, 30, 1, 0 }, 370 { "+3.3V", 10, 0, 20, 1, 0 }, 371 { "5VSB", 11, 0, 30, 1, 0 }, 372 { "CPU", 24, 1, 1, 1, 0 }, 373 { "System ", 25, 1, 1, 1, 0 }, 374 { "PWM", 26, 1, 1, 1, 0 }, 375 { "CPU Fan", 32, 2, 60, 1, 0 }, 376 { "NB Fan", 33, 2, 60, 1, 0 }, 377 { "SYS Fan", 34, 2, 60, 1, 0 }, 378 { NULL, 0, 0, 0, 0, 0 } } 379 }, 380 { 0x0015, NULL /* Unknown, need DMI string */, { 381 { "CPU Core", 0, 0, 10, 1, 0 }, 382 { "DDR", 1, 0, 20, 1, 0 }, 383 { "DDR VTT", 2, 0, 10, 1, 0 }, 384 { "HyperTransport", 3, 0, 10, 1, 0 }, 385 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 }, 386 { "NB", 4, 0, 10, 1, 0 }, 387 { "SB", 6, 0, 10, 1, 0 }, 388 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 389 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 390 { "ATX +5V", 9, 0, 30, 1, 0 }, 391 { "+3.3V", 10, 0, 20, 1, 0 }, 392 { "5VSB", 11, 0, 30, 1, 0 }, 393 { "CPU", 24, 1, 1, 1, 0 }, 394 { "SYS", 25, 1, 1, 1, 0 }, 395 { "PWM", 26, 1, 1, 1, 0 }, 396 { "CPU Fan", 32, 2, 60, 1, 0 }, 397 { "NB Fan", 33, 2, 60, 1, 0 }, 398 { "SYS Fan", 34, 2, 60, 1, 0 }, 399 { "AUX1 Fan", 33, 2, 60, 1, 0 }, 400 { "AUX2 Fan", 35, 2, 60, 1, 0 }, 401 { "AUX3 Fan", 36, 2, 60, 1, 0 }, 402 { NULL, 0, 0, 0, 0, 0 } } 403 }, 404 { 0x0016, NULL /* AW9D-MAX, need DMI string */, { 405 { "CPU Core", 0, 0, 10, 1, 0 }, 406 { "DDR2", 1, 0, 20, 1, 0 }, 407 { "DDR2 VTT", 2, 0, 10, 1, 0 }, 408 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 409 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 }, 410 { "MCH 2.5V", 5, 0, 20, 1, 0 }, 411 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 412 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 413 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 414 { "ATX +5V", 9, 0, 30, 1, 0 }, 415 { "+3.3V", 10, 0, 20, 1, 0 }, 416 { "5VSB", 11, 0, 30, 1, 0 }, 417 { "CPU", 24, 1, 1, 1, 0 }, 418 { "System ", 25, 1, 1, 1, 0 }, 419 { "PWM1", 26, 1, 1, 1, 0 }, 420 { "PWM2", 27, 1, 1, 1, 0 }, 421 { "PWM3", 28, 1, 1, 1, 0 }, 422 { "PWM4", 29, 1, 1, 1, 0 }, 423 { "CPU Fan", 32, 2, 60, 1, 0 }, 424 { "NB Fan", 33, 2, 60, 1, 0 }, 425 { "SYS Fan", 34, 2, 60, 1, 0 }, 426 { "AUX1 Fan", 35, 2, 60, 1, 0 }, 427 { "AUX2 Fan", 36, 2, 60, 1, 0 }, 428 { "AUX3 Fan", 37, 2, 60, 1, 0 }, 429 { "OTES1 Fan", 38, 2, 60, 1, 0 }, 430 { NULL, 0, 0, 0, 0, 0 } } 431 }, 432 { 0x0017, NULL /* Unknown, need DMI string */, { 433 { "CPU Core", 0, 0, 10, 1, 0 }, 434 { "DDR2", 1, 0, 20, 1, 0 }, 435 { "DDR2 VTT", 2, 0, 10, 1, 0 }, 436 { "HyperTransport", 3, 0, 10, 1, 0 }, 437 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 }, 438 { "NB 1.8V", 4, 0, 10, 1, 0 }, 439 { "NB 1.2V ", 13, 0, 10, 1, 0 }, 440 { "SB 1.2V", 5, 0, 10, 1, 0 }, 441 { "PCIE 1.2V", 12, 0, 10, 1, 0 }, 442 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 443 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 444 { "ATX +5V", 9, 0, 30, 1, 0 }, 445 { "ATX +3.3V", 10, 0, 20, 1, 0 }, 446 { "ATX 5VSB", 11, 0, 30, 1, 0 }, 447 { "CPU", 24, 1, 1, 1, 0 }, 448 { "System ", 26, 1, 1, 1, 0 }, 449 { "PWM", 27, 1, 1, 1, 0 }, 450 { "CPU FAN", 32, 2, 60, 1, 0 }, 451 { "SYS FAN", 34, 2, 60, 1, 0 }, 452 { "AUX1 FAN", 35, 2, 60, 1, 0 }, 453 { "AUX2 FAN", 36, 2, 60, 1, 0 }, 454 { "AUX3 FAN", 37, 2, 60, 1, 0 }, 455 { NULL, 0, 0, 0, 0, 0 } } 456 }, 457 { 0x0018, NULL /* Unknown, need DMI string */, { 458 { "CPU Core", 0, 0, 10, 1, 0 }, 459 { "DDR2", 1, 0, 20, 1, 0 }, 460 { "DDR2 VTT", 2, 0, 10, 1, 0 }, 461 { "CPU VTT", 3, 0, 10, 1, 0 }, 462 { "MCH 1.25V", 4, 0, 10, 1, 0 }, 463 { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, 464 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 465 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 466 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 467 { "ATX +5V", 9, 0, 30, 1, 0 }, 468 { "+3.3V", 10, 0, 20, 1, 0 }, 469 { "5VSB", 11, 0, 30, 1, 0 }, 470 { "CPU", 24, 1, 1, 1, 0 }, 471 { "System ", 25, 1, 1, 1, 0 }, 472 { "PWM Phase1", 26, 1, 1, 1, 0 }, 473 { "PWM Phase2", 27, 1, 1, 1, 0 }, 474 { "PWM Phase3", 28, 1, 1, 1, 0 }, 475 { "PWM Phase4", 29, 1, 1, 1, 0 }, 476 { "PWM Phase5", 30, 1, 1, 1, 0 }, 477 { "CPU Fan", 32, 2, 60, 1, 0 }, 478 { "SYS Fan", 34, 2, 60, 1, 0 }, 479 { "AUX1 Fan", 33, 2, 60, 1, 0 }, 480 { "AUX2 Fan", 35, 2, 60, 1, 0 }, 481 { "AUX3 Fan", 36, 2, 60, 1, 0 }, 482 { NULL, 0, 0, 0, 0, 0 } } 483 }, 484 { 0x0019, NULL /* Unknown, need DMI string */, { 485 { "CPU Core", 7, 0, 10, 1, 0 }, 486 { "DDR2", 13, 0, 20, 1, 0 }, 487 { "DDR2 VTT", 14, 0, 10, 1, 0 }, 488 { "CPU VTT", 3, 0, 20, 1, 0 }, 489 { "NB 1.2V ", 4, 0, 10, 1, 0 }, 490 { "SB 1.5V", 6, 0, 10, 1, 0 }, 491 { "HyperTransport", 5, 0, 10, 1, 0 }, 492 { "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 }, 493 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 }, 494 { "ATX +5V", 9, 0, 30, 1, 0 }, 495 { "ATX +3.3V", 10, 0, 20, 1, 0 }, 496 { "ATX 5VSB", 11, 0, 30, 1, 0 }, 497 { "CPU", 24, 1, 1, 1, 0 }, 498 { "System ", 25, 1, 1, 1, 0 }, 499 { "PWM Phase1", 26, 1, 1, 1, 0 }, 500 { "PWM Phase2", 27, 1, 1, 1, 0 }, 501 { "PWM Phase3", 28, 1, 1, 1, 0 }, 502 { "PWM Phase4", 29, 1, 1, 1, 0 }, 503 { "PWM Phase5", 30, 1, 1, 1, 0 }, 504 { "CPU FAN", 32, 2, 60, 1, 0 }, 505 { "SYS FAN", 34, 2, 60, 1, 0 }, 506 { "AUX1 FAN", 33, 2, 60, 1, 0 }, 507 { "AUX2 FAN", 35, 2, 60, 1, 0 }, 508 { "AUX3 FAN", 36, 2, 60, 1, 0 }, 509 { NULL, 0, 0, 0, 0, 0 } } 510 }, 511 { 0x001A, "IP35 Pro(Intel P35-ICH9R)", { 512 { "CPU Core", 0, 0, 10, 1, 0 }, 513 { "DDR2", 1, 0, 20, 1, 0 }, 514 { "DDR2 VTT", 2, 0, 10, 1, 0 }, 515 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 }, 516 { "MCH 1.25V", 4, 0, 10, 1, 0 }, 517 { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, 518 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 519 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 520 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 }, 521 { "ATX +5V", 9, 0, 30, 1, 0 }, 522 { "+3.3V", 10, 0, 20, 1, 0 }, 523 { "5VSB", 11, 0, 30, 1, 0 }, 524 { "CPU", 24, 1, 1, 1, 0 }, 525 { "System ", 25, 1, 1, 1, 0 }, 526 { "PWM ", 26, 1, 1, 1, 0 }, 527 { "PWM Phase2", 27, 1, 1, 1, 0 }, 528 { "PWM Phase3", 28, 1, 1, 1, 0 }, 529 { "PWM Phase4", 29, 1, 1, 1, 0 }, 530 { "PWM Phase5", 30, 1, 1, 1, 0 }, 531 { "CPU Fan", 32, 2, 60, 1, 0 }, 532 { "SYS Fan", 34, 2, 60, 1, 0 }, 533 { "AUX1 Fan", 33, 2, 60, 1, 0 }, 534 { "AUX2 Fan", 35, 2, 60, 1, 0 }, 535 { "AUX3 Fan", 36, 2, 60, 1, 0 }, 536 { "AUX4 Fan", 37, 2, 60, 1, 0 }, 537 { NULL, 0, 0, 0, 0, 0 } } 538 }, 539 { 0x001B, NULL /* Unknown, need DMI string */, { 540 { "CPU Core", 0, 0, 10, 1, 0 }, 541 { "DDR3", 1, 0, 20, 1, 0 }, 542 { "DDR3 VTT", 2, 0, 10, 1, 0 }, 543 { "CPU VTT", 3, 0, 10, 1, 0 }, 544 { "MCH 1.25V", 4, 0, 10, 1, 0 }, 545 { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, 546 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 547 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 548 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 }, 549 { "ATX +5V", 9, 0, 30, 1, 0 }, 550 { "+3.3V", 10, 0, 20, 1, 0 }, 551 { "5VSB", 11, 0, 30, 1, 0 }, 552 { "CPU", 24, 1, 1, 1, 0 }, 553 { "System", 25, 1, 1, 1, 0 }, 554 { "PWM Phase1", 26, 1, 1, 1, 0 }, 555 { "PWM Phase2", 27, 1, 1, 1, 0 }, 556 { "PWM Phase3", 28, 1, 1, 1, 0 }, 557 { "PWM Phase4", 29, 1, 1, 1, 0 }, 558 { "PWM Phase5", 30, 1, 1, 1, 0 }, 559 { "CPU Fan", 32, 2, 60, 1, 0 }, 560 { "SYS Fan", 34, 2, 60, 1, 0 }, 561 { "AUX1 Fan", 33, 2, 60, 1, 0 }, 562 { "AUX2 Fan", 35, 2, 60, 1, 0 }, 563 { "AUX3 Fan", 36, 2, 60, 1, 0 }, 564 { NULL, 0, 0, 0, 0, 0 } } 565 }, 566 { 0x001C, NULL /* Unknown, need DMI string */, { 567 { "CPU Core", 0, 0, 10, 1, 0 }, 568 { "DDR2", 1, 0, 20, 1, 0 }, 569 { "DDR2 VTT", 2, 0, 10, 1, 0 }, 570 { "CPU VTT", 3, 0, 10, 1, 0 }, 571 { "MCH 1.25V", 4, 0, 10, 1, 0 }, 572 { "ICHIO 1.5V", 5, 0, 10, 1, 0 }, 573 { "ICH 1.05V", 6, 0, 10, 1, 0 }, 574 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 }, 575 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 }, 576 { "ATX +5V", 9, 0, 30, 1, 0 }, 577 { "+3.3V", 10, 0, 20, 1, 0 }, 578 { "5VSB", 11, 0, 30, 1, 0 }, 579 { "CPU", 24, 1, 1, 1, 0 }, 580 { "System", 25, 1, 1, 1, 0 }, 581 { "PWM Phase1", 26, 1, 1, 1, 0 }, 582 { "PWM Phase2", 27, 1, 1, 1, 0 }, 583 { "PWM Phase3", 28, 1, 1, 1, 0 }, 584 { "PWM Phase4", 29, 1, 1, 1, 0 }, 585 { "PWM Phase5", 30, 1, 1, 1, 0 }, 586 { "CPU Fan", 32, 2, 60, 1, 0 }, 587 { "SYS Fan", 34, 2, 60, 1, 0 }, 588 { "AUX1 Fan", 33, 2, 60, 1, 0 }, 589 { "AUX2 Fan", 35, 2, 60, 1, 0 }, 590 { "AUX3 Fan", 36, 2, 60, 1, 0 }, 591 { NULL, 0, 0, 0, 0, 0 } } 592 }, 593 { 0x0000, NULL, { { NULL, 0, 0, 0, 0, 0 } } } 594 }; 595 596 597 /* Insmod parameters */ 598 static int force; 599 module_param(force, bool, 0); 600 MODULE_PARM_DESC(force, "Set to one to force detection."); 601 /* Default verbose is 1, since this driver is still in the testing phase */ 602 static int verbose = 1; 603 module_param(verbose, bool, 0644); 604 MODULE_PARM_DESC(verbose, "Enable/disable verbose error reporting"); 605 606 607 /* wait while the uguru is busy (usually after a write) */ 608 static int abituguru3_wait_while_busy(struct abituguru3_data *data) 609 { 610 u8 x; 611 int timeout = ABIT_UGURU3_WAIT_TIMEOUT; 612 613 while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & 614 ABIT_UGURU3_STATUS_BUSY) { 615 timeout--; 616 if (timeout == 0) 617 return x; 618 /* sleep a bit before our last try, to give the uGuru3 one 619 last chance to respond. */ 620 if (timeout == 1) 621 msleep(1); 622 } 623 return ABIT_UGURU3_SUCCESS; 624 } 625 626 /* wait till uguru is ready to be read */ 627 static int abituguru3_wait_for_read(struct abituguru3_data *data) 628 { 629 u8 x; 630 int timeout = ABIT_UGURU3_WAIT_TIMEOUT; 631 632 while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & 633 ABIT_UGURU3_STATUS_READY_FOR_READ)) { 634 timeout--; 635 if (timeout == 0) 636 return x; 637 /* sleep a bit before our last try, to give the uGuru3 one 638 last chance to respond. */ 639 if (timeout == 1) 640 msleep(1); 641 } 642 return ABIT_UGURU3_SUCCESS; 643 } 644 645 /* This synchronizes us with the uGuru3's protocol state machine, this 646 must be done before each command. */ 647 static int abituguru3_synchronize(struct abituguru3_data *data) 648 { 649 int x, timeout = ABIT_UGURU3_SYNCHRONIZE_TIMEOUT; 650 651 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 652 ABIT_UGURU3_DEBUG("synchronize timeout during initial busy " 653 "wait, status: 0x%02x\n", x); 654 return -EIO; 655 } 656 657 outb(0x20, data->addr + ABIT_UGURU3_DATA); 658 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 659 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, " 660 "status: 0x%02x\n", x); 661 return -EIO; 662 } 663 664 outb(0x10, data->addr + ABIT_UGURU3_CMD); 665 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 666 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, " 667 "status: 0x%02x\n", x); 668 return -EIO; 669 } 670 671 outb(0x00, data->addr + ABIT_UGURU3_CMD); 672 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 673 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, " 674 "status: 0x%02x\n", x); 675 return -EIO; 676 } 677 678 if ((x = abituguru3_wait_for_read(data)) != ABIT_UGURU3_SUCCESS) { 679 ABIT_UGURU3_DEBUG("synchronize timeout waiting for read, " 680 "status: 0x%02x\n", x); 681 return -EIO; 682 } 683 684 while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) { 685 timeout--; 686 if (timeout == 0) { 687 ABIT_UGURU3_DEBUG("synchronize timeout cmd does not " 688 "hold 0xAC after synchronize, cmd: 0x%02x\n", 689 x); 690 return -EIO; 691 } 692 msleep(1); 693 } 694 return 0; 695 } 696 697 /* Read count bytes from sensor sensor_addr in bank bank_addr and store the 698 result in buf */ 699 static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset, 700 u8 count, u8 *buf) 701 { 702 int i, x; 703 704 if ((x = abituguru3_synchronize(data))) 705 return x; 706 707 outb(0x1A, data->addr + ABIT_UGURU3_DATA); 708 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 709 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " 710 "sending 0x1A, status: 0x%02x\n", (unsigned int)bank, 711 (unsigned int)offset, x); 712 return -EIO; 713 } 714 715 outb(bank, data->addr + ABIT_UGURU3_CMD); 716 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 717 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " 718 "sending the bank, status: 0x%02x\n", 719 (unsigned int)bank, (unsigned int)offset, x); 720 return -EIO; 721 } 722 723 outb(offset, data->addr + ABIT_UGURU3_CMD); 724 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 725 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " 726 "sending the offset, status: 0x%02x\n", 727 (unsigned int)bank, (unsigned int)offset, x); 728 return -EIO; 729 } 730 731 outb(count, data->addr + ABIT_UGURU3_CMD); 732 if ((x = abituguru3_wait_while_busy(data)) != ABIT_UGURU3_SUCCESS) { 733 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " 734 "sending the count, status: 0x%02x\n", 735 (unsigned int)bank, (unsigned int)offset, x); 736 return -EIO; 737 } 738 739 for (i = 0; i < count; i++) { 740 if ((x = abituguru3_wait_for_read(data)) != 741 ABIT_UGURU3_SUCCESS) { 742 ABIT_UGURU3_DEBUG("timeout reading byte %d from " 743 "0x%02x:0x%02x, status: 0x%02x\n", i, 744 (unsigned int)bank, (unsigned int)offset, x); 745 break; 746 } 747 buf[i] = inb(data->addr + ABIT_UGURU3_CMD); 748 } 749 return i; 750 } 751 752 /* Sensor settings are stored 1 byte per offset with the bytes 753 placed add consecutive offsets. */ 754 static int abituguru3_read_increment_offset(struct abituguru3_data *data, 755 u8 bank, u8 offset, u8 count, 756 u8 *buf, int offset_count) 757 { 758 int i, x; 759 760 for (i = 0; i < offset_count; i++) 761 if ((x = abituguru3_read(data, bank, offset + i, count, 762 buf + i * count)) != count) 763 return i * count + (i && (x < 0)) ? 0 : x; 764 765 return i * count; 766 } 767 768 /* Following are the sysfs callback functions. These functions expect: 769 sensor_device_attribute_2->index: index into the data->sensors array 770 sensor_device_attribute_2->nr: register offset, bitmask or NA. */ 771 static struct abituguru3_data *abituguru3_update_device(struct device *dev); 772 773 static ssize_t show_value(struct device *dev, 774 struct device_attribute *devattr, char *buf) 775 { 776 int value; 777 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); 778 struct abituguru3_data *data = abituguru3_update_device(dev); 779 const struct abituguru3_sensor_info *sensor; 780 781 if (!data) 782 return -EIO; 783 784 sensor = &data->sensors[attr->index]; 785 786 /* are we reading a setting, or is this a normal read? */ 787 if (attr->nr) 788 value = data->settings[sensor->port][attr->nr]; 789 else 790 value = data->value[sensor->port]; 791 792 /* convert the value */ 793 value = (value * sensor->multiplier) / sensor->divisor + 794 sensor->offset; 795 796 /* alternatively we could update the sensors settings struct for this, 797 but then its contents would differ from the windows sw ini files */ 798 if (sensor->type == ABIT_UGURU3_TEMP_SENSOR) 799 value *= 1000; 800 801 return sprintf(buf, "%d\n", value); 802 } 803 804 static ssize_t show_alarm(struct device *dev, 805 struct device_attribute *devattr, char *buf) 806 { 807 int port; 808 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); 809 struct abituguru3_data *data = abituguru3_update_device(dev); 810 811 if (!data) 812 return -EIO; 813 814 port = data->sensors[attr->index].port; 815 816 /* See if the alarm bit for this sensor is set and if a bitmask is 817 given in attr->nr also check if the alarm matches the type of alarm 818 we're looking for (for volt it can be either low or high). The type 819 is stored in a few readonly bits in the settings of the sensor. */ 820 if ((data->alarms[port / 8] & (0x01 << (port % 8))) && 821 (!attr->nr || (data->settings[port][0] & attr->nr))) 822 return sprintf(buf, "1\n"); 823 else 824 return sprintf(buf, "0\n"); 825 } 826 827 static ssize_t show_mask(struct device *dev, 828 struct device_attribute *devattr, char *buf) 829 { 830 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); 831 struct abituguru3_data *data = dev_get_drvdata(dev); 832 833 if (data->settings[data->sensors[attr->index].port][0] & attr->nr) 834 return sprintf(buf, "1\n"); 835 else 836 return sprintf(buf, "0\n"); 837 } 838 839 static ssize_t show_label(struct device *dev, 840 struct device_attribute *devattr, char *buf) 841 { 842 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr); 843 struct abituguru3_data *data = dev_get_drvdata(dev); 844 845 return sprintf(buf, "%s\n", data->sensors[attr->index].name); 846 } 847 848 static ssize_t show_name(struct device *dev, 849 struct device_attribute *devattr, char *buf) 850 { 851 return sprintf(buf, "%s\n", ABIT_UGURU3_NAME); 852 } 853 854 /* Sysfs attr templates, the real entries are generated automatically. */ 855 static const 856 struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { { 857 SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0), 858 SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0), 859 SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0), 860 SENSOR_ATTR_2(in%d_min_alarm, 0444, show_alarm, NULL, 861 ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0), 862 SENSOR_ATTR_2(in%d_max_alarm, 0444, show_alarm, NULL, 863 ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0), 864 SENSOR_ATTR_2(in%d_beep, 0444, show_mask, NULL, 865 ABIT_UGURU3_BEEP_ENABLE, 0), 866 SENSOR_ATTR_2(in%d_shutdown, 0444, show_mask, NULL, 867 ABIT_UGURU3_SHUTDOWN_ENABLE, 0), 868 SENSOR_ATTR_2(in%d_min_alarm_enable, 0444, show_mask, NULL, 869 ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0), 870 SENSOR_ATTR_2(in%d_max_alarm_enable, 0444, show_mask, NULL, 871 ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0), 872 SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0) 873 }, { 874 SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0), 875 SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0), 876 SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0), 877 SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0), 878 SENSOR_ATTR_2(temp%d_beep, 0444, show_mask, NULL, 879 ABIT_UGURU3_BEEP_ENABLE, 0), 880 SENSOR_ATTR_2(temp%d_shutdown, 0444, show_mask, NULL, 881 ABIT_UGURU3_SHUTDOWN_ENABLE, 0), 882 SENSOR_ATTR_2(temp%d_alarm_enable, 0444, show_mask, NULL, 883 ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0), 884 SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0) 885 }, { 886 SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0), 887 SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0), 888 SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0), 889 SENSOR_ATTR_2(fan%d_beep, 0444, show_mask, NULL, 890 ABIT_UGURU3_BEEP_ENABLE, 0), 891 SENSOR_ATTR_2(fan%d_shutdown, 0444, show_mask, NULL, 892 ABIT_UGURU3_SHUTDOWN_ENABLE, 0), 893 SENSOR_ATTR_2(fan%d_alarm_enable, 0444, show_mask, NULL, 894 ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0), 895 SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0) 896 } }; 897 898 static struct sensor_device_attribute_2 abituguru3_sysfs_attr[] = { 899 SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0), 900 }; 901 902 static int __devinit abituguru3_probe(struct platform_device *pdev) 903 { 904 const int no_sysfs_attr[3] = { 10, 8, 7 }; 905 int sensor_index[3] = { 0, 1, 1 }; 906 struct abituguru3_data *data; 907 int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV; 908 char *sysfs_filename; 909 u8 buf[2]; 910 u16 id; 911 912 if (!(data = kzalloc(sizeof(struct abituguru3_data), GFP_KERNEL))) 913 return -ENOMEM; 914 915 data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start; 916 mutex_init(&data->update_lock); 917 platform_set_drvdata(pdev, data); 918 919 /* Read the motherboard ID */ 920 if ((i = abituguru3_read(data, ABIT_UGURU3_MISC_BANK, 921 ABIT_UGURU3_BOARD_ID, 2, buf)) != 2) { 922 goto abituguru3_probe_error; 923 } 924 925 /* Completely read the uGuru to see if one really is there */ 926 if (!abituguru3_update_device(&pdev->dev)) 927 goto abituguru3_probe_error; 928 929 /* lookup the ID in our motherboard table */ 930 id = ((u16)buf[0] << 8) | (u16)buf[1]; 931 for (i = 0; abituguru3_motherboards[i].id; i++) 932 if (abituguru3_motherboards[i].id == id) 933 break; 934 if (!abituguru3_motherboards[i].id) { 935 printk(KERN_ERR ABIT_UGURU3_NAME ": error unknown motherboard " 936 "ID: %04X. Please report this to the abituguru3 " 937 "maintainer (see MAINTAINERS)\n", (unsigned int)id); 938 goto abituguru3_probe_error; 939 } 940 data->sensors = abituguru3_motherboards[i].sensors; 941 942 printk(KERN_INFO ABIT_UGURU3_NAME ": found Abit uGuru3, motherboard " 943 "ID: %04X\n", (unsigned int)id); 944 945 #ifdef CONFIG_DMI 946 if (!abituguru3_motherboards[i].dmi_name) { 947 printk(KERN_WARNING ABIT_UGURU3_NAME ": this motherboard was " 948 "not detected using DMI. Please send the output of " 949 "\"dmidecode\" to the abituguru3 maintainer" 950 "(see MAINTAINERS)\n"); 951 } 952 #endif 953 954 /* Fill the sysfs attr array */ 955 sysfs_attr_i = 0; 956 sysfs_filename = data->sysfs_names; 957 sysfs_names_free = ABIT_UGURU3_SYSFS_NAMES_LENGTH; 958 for (i = 0; data->sensors[i].name; i++) { 959 /* Fail safe check, this should never happen! */ 960 if (i >= ABIT_UGURU3_MAX_NO_SENSORS) { 961 printk(KERN_ERR ABIT_UGURU3_NAME 962 ": Fatal error motherboard has more sensors " 963 "then ABIT_UGURU3_MAX_NO_SENSORS. This should " 964 "never happen please report to the abituguru3 " 965 "maintainer (see MAINTAINERS)\n"); 966 res = -ENAMETOOLONG; 967 goto abituguru3_probe_error; 968 } 969 type = data->sensors[i].type; 970 for (j = 0; j < no_sysfs_attr[type]; j++) { 971 used = snprintf(sysfs_filename, sysfs_names_free, 972 abituguru3_sysfs_templ[type][j].dev_attr.attr. 973 name, sensor_index[type]) + 1; 974 data->sysfs_attr[sysfs_attr_i] = 975 abituguru3_sysfs_templ[type][j]; 976 data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name = 977 sysfs_filename; 978 data->sysfs_attr[sysfs_attr_i].index = i; 979 sysfs_filename += used; 980 sysfs_names_free -= used; 981 sysfs_attr_i++; 982 } 983 sensor_index[type]++; 984 } 985 /* Fail safe check, this should never happen! */ 986 if (sysfs_names_free < 0) { 987 printk(KERN_ERR ABIT_UGURU3_NAME 988 ": Fatal error ran out of space for sysfs attr names. " 989 "This should never happen please report to the " 990 "abituguru3 maintainer (see MAINTAINERS)\n"); 991 res = -ENAMETOOLONG; 992 goto abituguru3_probe_error; 993 } 994 995 /* Register sysfs hooks */ 996 for (i = 0; i < sysfs_attr_i; i++) 997 if (device_create_file(&pdev->dev, 998 &data->sysfs_attr[i].dev_attr)) 999 goto abituguru3_probe_error; 1000 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) 1001 if (device_create_file(&pdev->dev, 1002 &abituguru3_sysfs_attr[i].dev_attr)) 1003 goto abituguru3_probe_error; 1004 1005 data->hwmon_dev = hwmon_device_register(&pdev->dev); 1006 if (IS_ERR(data->hwmon_dev)) { 1007 res = PTR_ERR(data->hwmon_dev); 1008 goto abituguru3_probe_error; 1009 } 1010 1011 return 0; /* success */ 1012 1013 abituguru3_probe_error: 1014 for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++) 1015 device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr); 1016 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) 1017 device_remove_file(&pdev->dev, 1018 &abituguru3_sysfs_attr[i].dev_attr); 1019 kfree(data); 1020 return res; 1021 } 1022 1023 static int __devexit abituguru3_remove(struct platform_device *pdev) 1024 { 1025 int i; 1026 struct abituguru3_data *data = platform_get_drvdata(pdev); 1027 1028 platform_set_drvdata(pdev, NULL); 1029 hwmon_device_unregister(data->hwmon_dev); 1030 for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++) 1031 device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr); 1032 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) 1033 device_remove_file(&pdev->dev, 1034 &abituguru3_sysfs_attr[i].dev_attr); 1035 kfree(data); 1036 1037 return 0; 1038 } 1039 1040 static struct abituguru3_data *abituguru3_update_device(struct device *dev) 1041 { 1042 int i; 1043 struct abituguru3_data *data = dev_get_drvdata(dev); 1044 1045 mutex_lock(&data->update_lock); 1046 if (!data->valid || time_after(jiffies, data->last_updated + HZ)) { 1047 /* Clear data->valid while updating */ 1048 data->valid = 0; 1049 /* Read alarms */ 1050 if (abituguru3_read_increment_offset(data, 1051 ABIT_UGURU3_SETTINGS_BANK, 1052 ABIT_UGURU3_ALARMS_START, 1053 1, data->alarms, 48/8) != (48/8)) 1054 goto LEAVE_UPDATE; 1055 /* Read in and temp sensors (3 byte settings / sensor) */ 1056 for (i = 0; i < 32; i++) { 1057 if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK, 1058 ABIT_UGURU3_VALUES_START + i, 1059 1, &data->value[i]) != 1) 1060 goto LEAVE_UPDATE; 1061 if (abituguru3_read_increment_offset(data, 1062 ABIT_UGURU3_SETTINGS_BANK, 1063 ABIT_UGURU3_SETTINGS_START + i * 3, 1064 1, 1065 data->settings[i], 3) != 3) 1066 goto LEAVE_UPDATE; 1067 } 1068 /* Read temp sensors (2 byte settings / sensor) */ 1069 for (i = 0; i < 16; i++) { 1070 if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK, 1071 ABIT_UGURU3_VALUES_START + 32 + i, 1072 1, &data->value[32 + i]) != 1) 1073 goto LEAVE_UPDATE; 1074 if (abituguru3_read_increment_offset(data, 1075 ABIT_UGURU3_SETTINGS_BANK, 1076 ABIT_UGURU3_SETTINGS_START + 32 * 3 + 1077 i * 2, 1, 1078 data->settings[32 + i], 2) != 2) 1079 goto LEAVE_UPDATE; 1080 } 1081 data->last_updated = jiffies; 1082 data->valid = 1; 1083 } 1084 LEAVE_UPDATE: 1085 mutex_unlock(&data->update_lock); 1086 if (data->valid) 1087 return data; 1088 else 1089 return NULL; 1090 } 1091 1092 #ifdef CONFIG_PM 1093 static int abituguru3_suspend(struct platform_device *pdev, pm_message_t state) 1094 { 1095 struct abituguru3_data *data = platform_get_drvdata(pdev); 1096 /* make sure all communications with the uguru3 are done and no new 1097 ones are started */ 1098 mutex_lock(&data->update_lock); 1099 return 0; 1100 } 1101 1102 static int abituguru3_resume(struct platform_device *pdev) 1103 { 1104 struct abituguru3_data *data = platform_get_drvdata(pdev); 1105 mutex_unlock(&data->update_lock); 1106 return 0; 1107 } 1108 #else 1109 #define abituguru3_suspend NULL 1110 #define abituguru3_resume NULL 1111 #endif /* CONFIG_PM */ 1112 1113 static struct platform_driver abituguru3_driver = { 1114 .driver = { 1115 .owner = THIS_MODULE, 1116 .name = ABIT_UGURU3_NAME, 1117 }, 1118 .probe = abituguru3_probe, 1119 .remove = __devexit_p(abituguru3_remove), 1120 .suspend = abituguru3_suspend, 1121 .resume = abituguru3_resume 1122 }; 1123 1124 #ifdef CONFIG_DMI 1125 1126 static int __init abituguru3_dmi_detect(void) 1127 { 1128 const char *board_vendor, *board_name; 1129 int i, err = (force) ? 1 : -ENODEV; 1130 1131 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); 1132 if (!board_vendor || strcmp(board_vendor, "http://www.abit.com.tw/")) 1133 return err; 1134 1135 board_name = dmi_get_system_info(DMI_BOARD_NAME); 1136 if (!board_name) 1137 return err; 1138 1139 for (i = 0; abituguru3_motherboards[i].id; i++) { 1140 const char *dmi_name = abituguru3_motherboards[i].dmi_name; 1141 if (dmi_name && !strcmp(dmi_name, board_name)) 1142 break; 1143 } 1144 1145 if (!abituguru3_motherboards[i].id) 1146 return 1; 1147 1148 return 0; 1149 } 1150 1151 #else /* !CONFIG_DMI */ 1152 1153 static inline int abituguru3_dmi_detect(void) 1154 { 1155 return -ENODEV; 1156 } 1157 1158 #endif /* CONFIG_DMI */ 1159 1160 /* FIXME: Manual detection should die eventually; we need to collect stable 1161 * DMI model names first before we can rely entirely on CONFIG_DMI. 1162 */ 1163 1164 static int __init abituguru3_detect(void) 1165 { 1166 /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or 1167 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05 1168 or 0x55 at CMD instead, why is unknown. */ 1169 u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA); 1170 u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD); 1171 if (((data_val == 0x00) || (data_val == 0x08)) && 1172 ((cmd_val == 0xAC) || (cmd_val == 0x05) || 1173 (cmd_val == 0x55))) 1174 return 0; 1175 1176 ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = " 1177 "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val); 1178 1179 if (force) { 1180 printk(KERN_INFO ABIT_UGURU3_NAME ": Assuming Abit uGuru3 is " 1181 "present because of \"force\" parameter\n"); 1182 return 0; 1183 } 1184 1185 /* No uGuru3 found */ 1186 return -ENODEV; 1187 } 1188 1189 static struct platform_device *abituguru3_pdev; 1190 1191 static int __init abituguru3_init(void) 1192 { 1193 struct resource res = { .flags = IORESOURCE_IO }; 1194 int err; 1195 1196 /* Attempt DMI detection first */ 1197 err = abituguru3_dmi_detect(); 1198 if (err < 0) 1199 return err; 1200 1201 /* Fall back to manual detection if there was no exact 1202 * board name match, or force was specified. 1203 */ 1204 if (err > 0) { 1205 err = abituguru3_detect(); 1206 if (err) 1207 return err; 1208 } 1209 1210 err = platform_driver_register(&abituguru3_driver); 1211 if (err) 1212 goto exit; 1213 1214 abituguru3_pdev = platform_device_alloc(ABIT_UGURU3_NAME, 1215 ABIT_UGURU3_BASE); 1216 if (!abituguru3_pdev) { 1217 printk(KERN_ERR ABIT_UGURU3_NAME 1218 ": Device allocation failed\n"); 1219 err = -ENOMEM; 1220 goto exit_driver_unregister; 1221 } 1222 1223 res.start = ABIT_UGURU3_BASE; 1224 res.end = ABIT_UGURU3_BASE + ABIT_UGURU3_REGION_LENGTH - 1; 1225 res.name = ABIT_UGURU3_NAME; 1226 1227 err = platform_device_add_resources(abituguru3_pdev, &res, 1); 1228 if (err) { 1229 printk(KERN_ERR ABIT_UGURU3_NAME 1230 ": Device resource addition failed (%d)\n", err); 1231 goto exit_device_put; 1232 } 1233 1234 err = platform_device_add(abituguru3_pdev); 1235 if (err) { 1236 printk(KERN_ERR ABIT_UGURU3_NAME 1237 ": Device addition failed (%d)\n", err); 1238 goto exit_device_put; 1239 } 1240 1241 return 0; 1242 1243 exit_device_put: 1244 platform_device_put(abituguru3_pdev); 1245 exit_driver_unregister: 1246 platform_driver_unregister(&abituguru3_driver); 1247 exit: 1248 return err; 1249 } 1250 1251 static void __exit abituguru3_exit(void) 1252 { 1253 platform_device_unregister(abituguru3_pdev); 1254 platform_driver_unregister(&abituguru3_driver); 1255 } 1256 1257 MODULE_AUTHOR("Hans de Goede <j.w.r.degoede@hhs.nl>"); 1258 MODULE_DESCRIPTION("Abit uGuru3 Sensor device"); 1259 MODULE_LICENSE("GPL"); 1260 1261 module_init(abituguru3_init); 1262 module_exit(abituguru3_exit); 1263