1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021-2022 NVIDIA Corporation 4 * 5 * Author: Dipen Patel <dipenp@nvidia.com> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/stat.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/hte.h> 17 #include <linux/uaccess.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/gpio/consumer.h> 20 21 #define HTE_SUSPEND 0 22 23 /* HTE source clock TSC is 1GHz for T264 and 31.25MHz for others */ 24 #define HTE_TS_CLK_RATE_HZ 31250000ULL 25 #define HTE_TS_CLK_RATE_1G 1000000000ULL 26 #define HTE_CLK_RATE_NS 32 27 #define HTE_CLK_RATE_NS_1G 1 28 29 #define NV_AON_SLICE_INVALID -1 30 #define NV_LINES_IN_SLICE 32 31 32 /* AON HTE line map For slice 1 */ 33 #define NV_AON_HTE_SLICE1_IRQ_GPIO_28 12 34 #define NV_AON_HTE_SLICE1_IRQ_GPIO_29 13 35 36 /* AON HTE line map For slice 2 */ 37 #define NV_AON_HTE_SLICE2_IRQ_GPIO_0 0 38 #define NV_AON_HTE_SLICE2_IRQ_GPIO_1 1 39 #define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2 40 #define NV_AON_HTE_SLICE2_IRQ_GPIO_3 3 41 #define NV_AON_HTE_SLICE2_IRQ_GPIO_4 4 42 #define NV_AON_HTE_SLICE2_IRQ_GPIO_5 5 43 #define NV_AON_HTE_SLICE2_IRQ_GPIO_6 6 44 #define NV_AON_HTE_SLICE2_IRQ_GPIO_7 7 45 #define NV_AON_HTE_SLICE2_IRQ_GPIO_8 8 46 #define NV_AON_HTE_SLICE2_IRQ_GPIO_9 9 47 #define NV_AON_HTE_SLICE2_IRQ_GPIO_10 10 48 #define NV_AON_HTE_SLICE2_IRQ_GPIO_11 11 49 #define NV_AON_HTE_SLICE2_IRQ_GPIO_12 12 50 #define NV_AON_HTE_SLICE2_IRQ_GPIO_13 13 51 #define NV_AON_HTE_SLICE2_IRQ_GPIO_14 14 52 #define NV_AON_HTE_SLICE2_IRQ_GPIO_15 15 53 #define NV_AON_HTE_SLICE2_IRQ_GPIO_16 16 54 #define NV_AON_HTE_SLICE2_IRQ_GPIO_17 17 55 #define NV_AON_HTE_SLICE2_IRQ_GPIO_18 18 56 #define NV_AON_HTE_SLICE2_IRQ_GPIO_19 19 57 #define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20 58 #define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21 59 #define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22 60 #define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23 61 #define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24 62 #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 63 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 64 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 65 #define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 66 #define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 67 #define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 68 #define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 69 70 #define HTE_TECTRL 0x0 71 #define HTE_TETSCH 0x4 72 #define HTE_TETSCL 0x8 73 #define HTE_TESRC 0xC 74 #define HTE_TECCV 0x10 75 #define HTE_TEPCV 0x14 76 #define HTE_TECMD 0x1C 77 #define HTE_TESTATUS 0x20 78 #define HTE_SLICE0_TETEN 0x40 79 #define HTE_SLICE1_TETEN 0x60 80 81 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN) 82 83 #define HTE_TECTRL_ENABLE_ENABLE 0x1 84 85 #define HTE_TECTRL_OCCU_SHIFT 0x8 86 #define HTE_TECTRL_INTR_SHIFT 0x1 87 #define HTE_TECTRL_INTR_ENABLE 0x1 88 89 #define HTE_TESRC_SLICE_SHIFT 16 90 #define HTE_TESRC_SLICE_DEFAULT_MASK 0xFF 91 92 #define HTE_TECMD_CMD_POP 0x1 93 94 #define HTE_TESTATUS_OCCUPANCY_SHIFT 8 95 #define HTE_TESTATUS_OCCUPANCY_MASK 0xFF 96 97 enum tegra_hte_type { 98 HTE_TEGRA_TYPE_GPIO = 1U << 0, 99 HTE_TEGRA_TYPE_LIC = 1U << 1, 100 }; 101 102 struct hte_slices { 103 u32 r_val; 104 unsigned long flags; 105 /* to prevent lines mapped to same slice updating its register */ 106 spinlock_t s_lock; 107 }; 108 109 struct tegra_hte_line_mapped { 110 int slice; 111 u32 bit_index; 112 }; 113 114 struct tegra_hte_line_data { 115 unsigned long flags; 116 void *data; 117 }; 118 119 struct tegra_hte_data { 120 enum tegra_hte_type type; 121 u32 slices; 122 u32 map_sz; 123 u32 sec_map_sz; 124 u64 tsc_clkrate_hz; 125 u32 tsc_clkrate_ns; 126 const struct tegra_hte_line_mapped *map; 127 const struct tegra_hte_line_mapped *sec_map; 128 }; 129 130 struct tegra_hte_soc { 131 int hte_irq; 132 u32 itr_thrshld; 133 u32 conf_rval; 134 struct hte_slices *sl; 135 const struct tegra_hte_data *prov_data; 136 struct tegra_hte_line_data *line_data; 137 struct hte_chip *chip; 138 struct gpio_device *gdev; 139 void __iomem *regs; 140 }; 141 142 static const struct tegra_hte_line_mapped tegra194_aon_gpio_map[] = { 143 /* gpio, slice, bit_index */ 144 /* AA port */ 145 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 146 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 147 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 148 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 149 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 150 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 151 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 152 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 153 /* BB port */ 154 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 155 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 156 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 157 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 158 /* CC port */ 159 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 160 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 161 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 162 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 163 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 164 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 165 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 166 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 167 /* DD port */ 168 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 169 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 170 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 171 /* EE port */ 172 [23] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 173 [24] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 174 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 175 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 176 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 177 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 178 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 179 }; 180 181 static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { 182 /* gpio, slice, bit_index */ 183 /* AA port */ 184 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 185 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 186 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 187 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 188 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 189 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 190 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 191 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 192 /* BB port */ 193 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 194 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 195 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 196 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 197 [12] = {NV_AON_SLICE_INVALID, 0}, 198 [13] = {NV_AON_SLICE_INVALID, 0}, 199 [14] = {NV_AON_SLICE_INVALID, 0}, 200 [15] = {NV_AON_SLICE_INVALID, 0}, 201 /* CC port */ 202 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 203 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 204 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 205 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 206 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 207 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 208 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 209 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 210 /* DD port */ 211 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 212 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 213 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 214 [27] = {NV_AON_SLICE_INVALID, 0}, 215 [28] = {NV_AON_SLICE_INVALID, 0}, 216 [29] = {NV_AON_SLICE_INVALID, 0}, 217 [30] = {NV_AON_SLICE_INVALID, 0}, 218 [31] = {NV_AON_SLICE_INVALID, 0}, 219 /* EE port */ 220 [32] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 221 [33] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 222 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 223 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 224 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 225 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 226 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 227 [39] = {NV_AON_SLICE_INVALID, 0}, 228 }; 229 230 static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { 231 /* gpio, slice, bit_index */ 232 /* AA port */ 233 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 234 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 235 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 236 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 237 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 238 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 239 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 240 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 241 /* BB port */ 242 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 243 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 244 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 245 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 246 /* CC port */ 247 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 248 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 249 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 250 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 251 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 252 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 253 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 254 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 255 /* DD port */ 256 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 257 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 258 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 259 /* EE port */ 260 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 261 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 262 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 263 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 264 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 265 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 266 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 267 [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 268 /* GG port */ 269 [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 270 }; 271 272 static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { 273 /* gpio, slice, bit_index */ 274 /* AA port */ 275 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 276 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 277 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 278 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 279 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 280 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 281 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 282 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 283 /* BB port */ 284 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 285 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 286 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 287 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 288 [12] = {NV_AON_SLICE_INVALID, 0}, 289 [13] = {NV_AON_SLICE_INVALID, 0}, 290 [14] = {NV_AON_SLICE_INVALID, 0}, 291 [15] = {NV_AON_SLICE_INVALID, 0}, 292 /* CC port */ 293 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 294 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 295 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 296 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 297 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 298 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 299 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 300 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 301 /* DD port */ 302 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 303 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 304 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 305 [27] = {NV_AON_SLICE_INVALID, 0}, 306 [28] = {NV_AON_SLICE_INVALID, 0}, 307 [29] = {NV_AON_SLICE_INVALID, 0}, 308 [30] = {NV_AON_SLICE_INVALID, 0}, 309 [31] = {NV_AON_SLICE_INVALID, 0}, 310 /* EE port */ 311 [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 312 [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 313 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 314 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 315 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 316 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 317 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 318 [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 319 /* GG port */ 320 [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 321 }; 322 323 static const struct tegra_hte_line_mapped tegra264_aon_gpio_map[] = { 324 /* gpio, slice, bit_index */ 325 /* AA port */ 326 [0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 327 [1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 328 [2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 329 [3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 330 [4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 331 [5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 332 [6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 333 [7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 334 /* BB port */ 335 [8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 336 [9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 337 /* CC port */ 338 [10] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 339 [11] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 340 [12] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 341 [13] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 342 [14] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 343 [15] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 344 [16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 345 [17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 346 /* DD port */ 347 [18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 348 [19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 349 [20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 350 [21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 351 [22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 352 [23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 353 [24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 354 [25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 355 /* EE port */ 356 [26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 357 [27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 358 [28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 359 [29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 360 }; 361 362 static const struct tegra_hte_line_mapped tegra264_aon_gpio_sec_map[] = { 363 /* gpio, slice, bit_index */ 364 /* AA port */ 365 [0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 366 [1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 367 [2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 368 [3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 369 [4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 370 [5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 371 [6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 372 [7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 373 /* BB port */ 374 [8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 375 [9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 376 [10] = {NV_AON_SLICE_INVALID, 0}, 377 [11] = {NV_AON_SLICE_INVALID, 0}, 378 [12] = {NV_AON_SLICE_INVALID, 0}, 379 [13] = {NV_AON_SLICE_INVALID, 0}, 380 [14] = {NV_AON_SLICE_INVALID, 0}, 381 [15] = {NV_AON_SLICE_INVALID, 0}, 382 /* CC port */ 383 [16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 384 [17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 385 [18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 386 [19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 387 [20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 388 [21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 389 [22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 390 [23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 391 /* DD port */ 392 [24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 393 [25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 394 [26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 395 [27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 396 [28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 397 [29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 398 [30] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 399 [31] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 400 /* EE port */ 401 [32] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 402 [33] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 403 [34] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 404 [35] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 405 [36] = {NV_AON_SLICE_INVALID, 0}, 406 [37] = {NV_AON_SLICE_INVALID, 0}, 407 [38] = {NV_AON_SLICE_INVALID, 0}, 408 [39] = {NV_AON_SLICE_INVALID, 0}, 409 }; 410 411 static const struct tegra_hte_data t194_aon_hte = { 412 .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), 413 .map = tegra194_aon_gpio_map, 414 .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), 415 .sec_map = tegra194_aon_gpio_sec_map, 416 .type = HTE_TEGRA_TYPE_GPIO, 417 .slices = 3, 418 .tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ, 419 .tsc_clkrate_ns = HTE_CLK_RATE_NS, 420 }; 421 422 static const struct tegra_hte_data t234_aon_hte = { 423 .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), 424 .map = tegra234_aon_gpio_map, 425 .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), 426 .sec_map = tegra234_aon_gpio_sec_map, 427 .type = HTE_TEGRA_TYPE_GPIO, 428 .slices = 3, 429 .tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ, 430 .tsc_clkrate_ns = HTE_CLK_RATE_NS, 431 }; 432 433 static const struct tegra_hte_data t264_aon_hte = { 434 .map_sz = ARRAY_SIZE(tegra264_aon_gpio_map), 435 .map = tegra264_aon_gpio_map, 436 .sec_map_sz = ARRAY_SIZE(tegra264_aon_gpio_sec_map), 437 .sec_map = tegra264_aon_gpio_sec_map, 438 .type = HTE_TEGRA_TYPE_GPIO, 439 .slices = 4, 440 .tsc_clkrate_hz = HTE_TS_CLK_RATE_1G, 441 .tsc_clkrate_ns = HTE_CLK_RATE_NS_1G, 442 }; 443 444 static const struct tegra_hte_data t194_lic_hte = { 445 .map_sz = 0, 446 .map = NULL, 447 .type = HTE_TEGRA_TYPE_LIC, 448 .slices = 11, 449 .tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ, 450 .tsc_clkrate_ns = HTE_CLK_RATE_NS, 451 }; 452 453 static const struct tegra_hte_data t234_lic_hte = { 454 .map_sz = 0, 455 .map = NULL, 456 .type = HTE_TEGRA_TYPE_LIC, 457 .slices = 17, 458 .tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ, 459 .tsc_clkrate_ns = HTE_CLK_RATE_NS, 460 }; 461 462 static const struct tegra_hte_data t264_lic_hte = { 463 .map_sz = 0, 464 .map = NULL, 465 .type = HTE_TEGRA_TYPE_LIC, 466 .slices = 10, 467 .tsc_clkrate_hz = HTE_TS_CLK_RATE_1G, 468 .tsc_clkrate_ns = HTE_CLK_RATE_NS_1G, 469 }; 470 471 static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) 472 { 473 return readl(hte->regs + reg); 474 } 475 476 static inline void tegra_hte_writel(struct tegra_hte_soc *hte, u32 reg, 477 u32 val) 478 { 479 writel(val, hte->regs + reg); 480 } 481 482 static int tegra_hte_map_to_line_id(u32 eid, 483 const struct tegra_hte_line_mapped *m, 484 u32 map_sz, u32 *mapped) 485 { 486 487 if (m) { 488 if (eid >= map_sz) 489 return -EINVAL; 490 if (m[eid].slice == NV_AON_SLICE_INVALID) 491 return -EINVAL; 492 493 *mapped = (m[eid].slice << 5) + m[eid].bit_index; 494 } else { 495 *mapped = eid; 496 } 497 498 return 0; 499 } 500 501 static int tegra_hte_line_xlate(struct hte_chip *gc, 502 const struct of_phandle_args *args, 503 struct hte_ts_desc *desc, u32 *xlated_id) 504 { 505 int ret = 0; 506 u32 line_id; 507 struct tegra_hte_soc *gs; 508 const struct tegra_hte_line_mapped *map = NULL; 509 u32 map_sz = 0; 510 511 if (!gc || !desc || !xlated_id) 512 return -EINVAL; 513 514 if (args) { 515 if (gc->of_hte_n_cells < 1) 516 return -EINVAL; 517 518 if (args->args_count != gc->of_hte_n_cells) 519 return -EINVAL; 520 521 desc->attr.line_id = args->args[0]; 522 } 523 524 gs = gc->data; 525 if (!gs || !gs->prov_data) 526 return -EINVAL; 527 528 /* 529 * GPIO consumers can access GPIOs in two ways: 530 * 531 * 1) Using the global GPIO numberspace. 532 * 533 * This is the old, now DEPRECATED method and should not be used in 534 * new code. TODO: Check if tegra is even concerned by this. 535 * 536 * 2) Using GPIO descriptors that can be assigned to consumer devices 537 * using device-tree, ACPI or lookup tables. 538 * 539 * The code below addresses both the consumer use cases and maps into 540 * HTE/GTE namespace. 541 */ 542 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { 543 line_id = desc->attr.line_id - gpio_device_get_base(gs->gdev); 544 map = gs->prov_data->map; 545 map_sz = gs->prov_data->map_sz; 546 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { 547 line_id = desc->attr.line_id; 548 map = gs->prov_data->sec_map; 549 map_sz = gs->prov_data->sec_map_sz; 550 } else { 551 line_id = desc->attr.line_id; 552 } 553 554 ret = tegra_hte_map_to_line_id(line_id, map, map_sz, xlated_id); 555 if (ret < 0) { 556 dev_err(gc->dev, "line_id:%u mapping failed\n", 557 desc->attr.line_id); 558 return ret; 559 } 560 561 if (*xlated_id > gc->nlines) 562 return -EINVAL; 563 564 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", 565 desc->attr.line_id, *xlated_id); 566 567 return 0; 568 } 569 570 static int tegra_hte_line_xlate_plat(struct hte_chip *gc, 571 struct hte_ts_desc *desc, u32 *xlated_id) 572 { 573 return tegra_hte_line_xlate(gc, NULL, desc, xlated_id); 574 } 575 576 static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en) 577 { 578 u32 slice, sl_bit_shift, line_bit, val, reg; 579 struct tegra_hte_soc *gs; 580 581 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 582 583 if (!chip) 584 return -EINVAL; 585 586 gs = chip->data; 587 588 if (line_id > chip->nlines) { 589 dev_err(chip->dev, 590 "line id: %u is not supported by this controller\n", 591 line_id); 592 return -EINVAL; 593 } 594 595 slice = line_id >> sl_bit_shift; 596 line_bit = line_id & (HTE_SLICE_SIZE - 1); 597 reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; 598 599 spin_lock(&gs->sl[slice].s_lock); 600 601 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { 602 spin_unlock(&gs->sl[slice].s_lock); 603 dev_dbg(chip->dev, "device suspended"); 604 return -EBUSY; 605 } 606 607 val = tegra_hte_readl(gs, reg); 608 if (en) 609 val = val | (1 << line_bit); 610 else 611 val = val & (~(1 << line_bit)); 612 tegra_hte_writel(gs, reg, val); 613 614 spin_unlock(&gs->sl[slice].s_lock); 615 616 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", 617 line_id, slice, line_bit, reg); 618 619 return 0; 620 } 621 622 static int tegra_hte_enable(struct hte_chip *chip, u32 line_id) 623 { 624 if (!chip) 625 return -EINVAL; 626 627 return tegra_hte_en_dis_common(chip, line_id, true); 628 } 629 630 static int tegra_hte_disable(struct hte_chip *chip, u32 line_id) 631 { 632 if (!chip) 633 return -EINVAL; 634 635 return tegra_hte_en_dis_common(chip, line_id, false); 636 } 637 638 static int tegra_hte_request(struct hte_chip *chip, struct hte_ts_desc *desc, 639 u32 line_id) 640 { 641 int ret; 642 struct tegra_hte_soc *gs; 643 struct hte_line_attr *attr; 644 645 if (!chip || !chip->data || !desc) 646 return -EINVAL; 647 648 gs = chip->data; 649 attr = &desc->attr; 650 651 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 652 if (!attr->line_data) 653 return -EINVAL; 654 655 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, 656 attr->edge_flags); 657 if (ret) 658 return ret; 659 660 gs->line_data[line_id].data = attr->line_data; 661 gs->line_data[line_id].flags = attr->edge_flags; 662 } 663 664 return tegra_hte_en_dis_common(chip, line_id, true); 665 } 666 667 static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc, 668 u32 line_id) 669 { 670 struct tegra_hte_soc *gs; 671 struct hte_line_attr *attr; 672 int ret; 673 674 if (!chip || !chip->data || !desc) 675 return -EINVAL; 676 677 gs = chip->data; 678 attr = &desc->attr; 679 680 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 681 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, 682 gs->line_data[line_id].flags); 683 if (ret) 684 return ret; 685 686 gs->line_data[line_id].data = NULL; 687 gs->line_data[line_id].flags = 0; 688 } 689 690 return tegra_hte_en_dis_common(chip, line_id, false); 691 } 692 693 static int tegra_hte_clk_src_info(struct hte_chip *chip, 694 struct hte_clk_info *ci) 695 { 696 struct tegra_hte_soc *hte_dev = chip->data; 697 698 if (!ci) 699 return -EINVAL; 700 701 ci->hz = hte_dev->prov_data->tsc_clkrate_hz; 702 ci->type = CLOCK_MONOTONIC; 703 704 return 0; 705 } 706 707 static int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id) 708 { 709 struct gpio_desc *desc; 710 711 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 712 desc = gs->line_data[line_id].data; 713 if (desc) 714 return gpiod_get_raw_value(desc); 715 } 716 717 return -1; 718 } 719 720 static void tegra_hte_read_fifo(struct tegra_hte_soc *gs) 721 { 722 u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; 723 u64 tsc; 724 u8 tsc_ns_shift; 725 struct hte_ts_data el; 726 727 tsc_ns_shift = __builtin_ctz(gs->prov_data->tsc_clkrate_ns); 728 while ((tegra_hte_readl(gs, HTE_TESTATUS) >> 729 HTE_TESTATUS_OCCUPANCY_SHIFT) & 730 HTE_TESTATUS_OCCUPANCY_MASK) { 731 tsh = tegra_hte_readl(gs, HTE_TETSCH); 732 tsl = tegra_hte_readl(gs, HTE_TETSCL); 733 tsc = (((u64)tsh << 32) | tsl); 734 735 src = tegra_hte_readl(gs, HTE_TESRC); 736 slice = (src >> HTE_TESRC_SLICE_SHIFT) & 737 HTE_TESRC_SLICE_DEFAULT_MASK; 738 739 pv = tegra_hte_readl(gs, HTE_TEPCV); 740 cv = tegra_hte_readl(gs, HTE_TECCV); 741 acv = pv ^ cv; 742 while (acv) { 743 bit_index = __builtin_ctz(acv); 744 line_id = bit_index + (slice << 5); 745 el.tsc = tsc << tsc_ns_shift; 746 el.raw_level = tegra_hte_get_level(gs, line_id); 747 hte_push_ts_ns(gs->chip, line_id, &el); 748 acv &= ~BIT(bit_index); 749 } 750 tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP); 751 } 752 } 753 754 static irqreturn_t tegra_hte_isr(int irq, void *dev_id) 755 { 756 struct tegra_hte_soc *gs = dev_id; 757 (void)irq; 758 759 tegra_hte_read_fifo(gs); 760 761 return IRQ_HANDLED; 762 } 763 764 static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, 765 const struct hte_ts_desc *hdesc) 766 { 767 struct tegra_hte_soc *hte_dev = chip->data; 768 769 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) 770 return false; 771 772 return hte_dev->gdev == gpiod_to_gpio_device(hdesc->attr.line_data); 773 } 774 775 static const struct of_device_id tegra_hte_of_match[] = { 776 { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, 777 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, 778 { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, 779 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, 780 { .compatible = "nvidia,tegra264-gte-lic", .data = &t264_lic_hte}, 781 { .compatible = "nvidia,tegra264-gte-aon", .data = &t264_aon_hte}, 782 { } 783 }; 784 MODULE_DEVICE_TABLE(of, tegra_hte_of_match); 785 786 static const struct hte_ops g_ops = { 787 .request = tegra_hte_request, 788 .release = tegra_hte_release, 789 .enable = tegra_hte_enable, 790 .disable = tegra_hte_disable, 791 .get_clk_src_info = tegra_hte_clk_src_info, 792 }; 793 794 static void tegra_gte_disable(void *data) 795 { 796 struct platform_device *pdev = data; 797 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); 798 799 tegra_hte_writel(gs, HTE_TECTRL, 0); 800 } 801 802 static void tegra_hte_put_gpio_device(void *data) 803 { 804 struct gpio_device *gdev = data; 805 806 gpio_device_put(gdev); 807 } 808 809 static int tegra_hte_probe(struct platform_device *pdev) 810 { 811 int ret; 812 u32 i, slices, val = 0; 813 u32 nlines; 814 struct device *dev; 815 struct tegra_hte_soc *hte_dev; 816 struct hte_chip *gc; 817 struct device_node *gpio_ctrl; 818 819 dev = &pdev->dev; 820 821 hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); 822 if (!hte_dev) 823 return -ENOMEM; 824 825 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 826 if (!gc) 827 return -ENOMEM; 828 829 dev_set_drvdata(&pdev->dev, hte_dev); 830 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); 831 832 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); 833 if (ret != 0) 834 slices = hte_dev->prov_data->slices; 835 836 dev_dbg(dev, "slices:%d\n", slices); 837 nlines = slices << 5; 838 839 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); 840 if (IS_ERR(hte_dev->regs)) 841 return PTR_ERR(hte_dev->regs); 842 843 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", 844 &hte_dev->itr_thrshld); 845 if (ret != 0) 846 hte_dev->itr_thrshld = 1; 847 848 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), 849 GFP_KERNEL); 850 if (!hte_dev->sl) 851 return -ENOMEM; 852 853 ret = platform_get_irq(pdev, 0); 854 if (ret < 0) 855 return ret; 856 hte_dev->hte_irq = ret; 857 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, 858 dev_name(dev), hte_dev); 859 if (ret < 0) { 860 dev_err(dev, "request irq failed.\n"); 861 return ret; 862 } 863 864 gc->nlines = nlines; 865 gc->ops = &g_ops; 866 gc->dev = dev; 867 gc->data = hte_dev; 868 gc->xlate_of = tegra_hte_line_xlate; 869 gc->xlate_plat = tegra_hte_line_xlate_plat; 870 gc->of_hte_n_cells = 1; 871 872 if (hte_dev->prov_data && 873 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 874 hte_dev->line_data = devm_kcalloc(dev, nlines, 875 sizeof(*hte_dev->line_data), 876 GFP_KERNEL); 877 if (!hte_dev->line_data) 878 return -ENOMEM; 879 880 gc->match_from_linedata = tegra_hte_match_from_linedata; 881 882 if (of_device_is_compatible(dev->of_node, 883 "nvidia,tegra194-gte-aon")) { 884 hte_dev->gdev = 885 gpio_device_find_by_label("tegra194-gpio-aon"); 886 } else { 887 gpio_ctrl = of_parse_phandle(dev->of_node, 888 "nvidia,gpio-controller", 889 0); 890 if (!gpio_ctrl) { 891 dev_err(dev, 892 "gpio controller node not found\n"); 893 return -ENODEV; 894 } 895 896 hte_dev->gdev = 897 gpio_device_find_by_fwnode(of_fwnode_handle(gpio_ctrl)); 898 of_node_put(gpio_ctrl); 899 } 900 901 if (!hte_dev->gdev) 902 return dev_err_probe(dev, -EPROBE_DEFER, 903 "wait for gpio controller\n"); 904 905 ret = devm_add_action_or_reset(dev, tegra_hte_put_gpio_device, 906 hte_dev->gdev); 907 if (ret) 908 return ret; 909 } 910 911 hte_dev->chip = gc; 912 913 ret = devm_hte_register_chip(hte_dev->chip); 914 if (ret) { 915 dev_err(gc->dev, "hte chip register failed"); 916 return ret; 917 } 918 919 for (i = 0; i < slices; i++) { 920 hte_dev->sl[i].flags = 0; 921 spin_lock_init(&hte_dev->sl[i].s_lock); 922 } 923 924 val = HTE_TECTRL_ENABLE_ENABLE | 925 (HTE_TECTRL_INTR_ENABLE << HTE_TECTRL_INTR_SHIFT) | 926 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); 927 tegra_hte_writel(hte_dev, HTE_TECTRL, val); 928 929 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); 930 if (ret) 931 return ret; 932 933 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); 934 935 return 0; 936 } 937 938 static int tegra_hte_resume_early(struct device *dev) 939 { 940 u32 i; 941 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 942 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 943 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 944 945 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); 946 947 for (i = 0; i < slices; i++) { 948 spin_lock(&gs->sl[i].s_lock); 949 tegra_hte_writel(gs, 950 ((i << sl_bit_shift) + HTE_SLICE0_TETEN), 951 gs->sl[i].r_val); 952 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); 953 spin_unlock(&gs->sl[i].s_lock); 954 } 955 956 return 0; 957 } 958 959 static int tegra_hte_suspend_late(struct device *dev) 960 { 961 u32 i; 962 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 963 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 964 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 965 966 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); 967 for (i = 0; i < slices; i++) { 968 spin_lock(&gs->sl[i].s_lock); 969 gs->sl[i].r_val = tegra_hte_readl(gs, 970 ((i << sl_bit_shift) + HTE_SLICE0_TETEN)); 971 set_bit(HTE_SUSPEND, &gs->sl[i].flags); 972 spin_unlock(&gs->sl[i].s_lock); 973 } 974 975 return 0; 976 } 977 978 static const struct dev_pm_ops tegra_hte_pm = { 979 LATE_SYSTEM_SLEEP_PM_OPS(tegra_hte_suspend_late, tegra_hte_resume_early) 980 }; 981 982 static struct platform_driver tegra_hte_driver = { 983 .probe = tegra_hte_probe, 984 .driver = { 985 .name = "tegra_hte", 986 .pm = pm_sleep_ptr(&tegra_hte_pm), 987 .of_match_table = tegra_hte_of_match, 988 }, 989 }; 990 991 module_platform_driver(tegra_hte_driver); 992 993 MODULE_AUTHOR("Dipen Patel <dipenp@nvidia.com>"); 994 MODULE_DESCRIPTION("NVIDIA Tegra HTE (Hardware Timestamping Engine) driver"); 995 MODULE_LICENSE("GPL"); 996