1 // SPDX-License-Identifier: GPL-2.0-only 2 /* OMAP SSI port driver. 3 * 4 * Copyright (C) 2010 Nokia Corporation. All rights reserved. 5 * Copyright (C) 2014 Sebastian Reichel <sre@kernel.org> 6 * 7 * Contact: Carlos Chinea <carlos.chinea@nokia.com> 8 */ 9 10 #include <linux/platform_device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/delay.h> 14 15 #include <linux/gpio/consumer.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/debugfs.h> 18 19 #include "omap_ssi_regs.h" 20 #include "omap_ssi.h" 21 22 static inline int hsi_dummy_msg(struct hsi_msg *msg __maybe_unused) 23 { 24 return 0; 25 } 26 27 static inline int hsi_dummy_cl(struct hsi_client *cl __maybe_unused) 28 { 29 return 0; 30 } 31 32 static inline unsigned int ssi_wakein(struct hsi_port *port) 33 { 34 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 35 return gpiod_get_value(omap_port->wake_gpio); 36 } 37 38 #ifdef CONFIG_DEBUG_FS 39 static void ssi_debug_remove_port(struct hsi_port *port) 40 { 41 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 42 43 debugfs_remove_recursive(omap_port->dir); 44 } 45 46 static int ssi_port_regs_show(struct seq_file *m, void *p __maybe_unused) 47 { 48 struct hsi_port *port = m->private; 49 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 50 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 51 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 52 void __iomem *base = omap_ssi->sys; 53 unsigned int ch; 54 55 pm_runtime_get_sync(omap_port->pdev); 56 if (omap_port->wake_irq > 0) 57 seq_printf(m, "CAWAKE\t\t: %d\n", ssi_wakein(port)); 58 seq_printf(m, "WAKE\t\t: 0x%08x\n", 59 readl(base + SSI_WAKE_REG(port->num))); 60 seq_printf(m, "MPU_ENABLE_IRQ%d\t: 0x%08x\n", 0, 61 readl(base + SSI_MPU_ENABLE_REG(port->num, 0))); 62 seq_printf(m, "MPU_STATUS_IRQ%d\t: 0x%08x\n", 0, 63 readl(base + SSI_MPU_STATUS_REG(port->num, 0))); 64 /* SST */ 65 base = omap_port->sst_base; 66 seq_puts(m, "\nSST\n===\n"); 67 seq_printf(m, "ID SST\t\t: 0x%08x\n", 68 readl(base + SSI_SST_ID_REG)); 69 seq_printf(m, "MODE\t\t: 0x%08x\n", 70 readl(base + SSI_SST_MODE_REG)); 71 seq_printf(m, "FRAMESIZE\t: 0x%08x\n", 72 readl(base + SSI_SST_FRAMESIZE_REG)); 73 seq_printf(m, "DIVISOR\t\t: 0x%08x\n", 74 readl(base + SSI_SST_DIVISOR_REG)); 75 seq_printf(m, "CHANNELS\t: 0x%08x\n", 76 readl(base + SSI_SST_CHANNELS_REG)); 77 seq_printf(m, "ARBMODE\t\t: 0x%08x\n", 78 readl(base + SSI_SST_ARBMODE_REG)); 79 seq_printf(m, "TXSTATE\t\t: 0x%08x\n", 80 readl(base + SSI_SST_TXSTATE_REG)); 81 seq_printf(m, "BUFSTATE\t: 0x%08x\n", 82 readl(base + SSI_SST_BUFSTATE_REG)); 83 seq_printf(m, "BREAK\t\t: 0x%08x\n", 84 readl(base + SSI_SST_BREAK_REG)); 85 for (ch = 0; ch < omap_port->channels; ch++) { 86 seq_printf(m, "BUFFER_CH%d\t: 0x%08x\n", ch, 87 readl(base + SSI_SST_BUFFER_CH_REG(ch))); 88 } 89 /* SSR */ 90 base = omap_port->ssr_base; 91 seq_puts(m, "\nSSR\n===\n"); 92 seq_printf(m, "ID SSR\t\t: 0x%08x\n", 93 readl(base + SSI_SSR_ID_REG)); 94 seq_printf(m, "MODE\t\t: 0x%08x\n", 95 readl(base + SSI_SSR_MODE_REG)); 96 seq_printf(m, "FRAMESIZE\t: 0x%08x\n", 97 readl(base + SSI_SSR_FRAMESIZE_REG)); 98 seq_printf(m, "CHANNELS\t: 0x%08x\n", 99 readl(base + SSI_SSR_CHANNELS_REG)); 100 seq_printf(m, "TIMEOUT\t\t: 0x%08x\n", 101 readl(base + SSI_SSR_TIMEOUT_REG)); 102 seq_printf(m, "RXSTATE\t\t: 0x%08x\n", 103 readl(base + SSI_SSR_RXSTATE_REG)); 104 seq_printf(m, "BUFSTATE\t: 0x%08x\n", 105 readl(base + SSI_SSR_BUFSTATE_REG)); 106 seq_printf(m, "BREAK\t\t: 0x%08x\n", 107 readl(base + SSI_SSR_BREAK_REG)); 108 seq_printf(m, "ERROR\t\t: 0x%08x\n", 109 readl(base + SSI_SSR_ERROR_REG)); 110 seq_printf(m, "ERRORACK\t: 0x%08x\n", 111 readl(base + SSI_SSR_ERRORACK_REG)); 112 for (ch = 0; ch < omap_port->channels; ch++) { 113 seq_printf(m, "BUFFER_CH%d\t: 0x%08x\n", ch, 114 readl(base + SSI_SSR_BUFFER_CH_REG(ch))); 115 } 116 pm_runtime_put_autosuspend(omap_port->pdev); 117 118 return 0; 119 } 120 121 DEFINE_SHOW_ATTRIBUTE(ssi_port_regs); 122 123 static int ssi_div_get(void *data, u64 *val) 124 { 125 struct hsi_port *port = data; 126 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 127 128 pm_runtime_get_sync(omap_port->pdev); 129 *val = readl(omap_port->sst_base + SSI_SST_DIVISOR_REG); 130 pm_runtime_put_autosuspend(omap_port->pdev); 131 132 return 0; 133 } 134 135 static int ssi_div_set(void *data, u64 val) 136 { 137 struct hsi_port *port = data; 138 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 139 140 if (val > 127) 141 return -EINVAL; 142 143 pm_runtime_get_sync(omap_port->pdev); 144 writel(val, omap_port->sst_base + SSI_SST_DIVISOR_REG); 145 omap_port->sst.divisor = val; 146 pm_runtime_put_autosuspend(omap_port->pdev); 147 148 return 0; 149 } 150 151 DEFINE_DEBUGFS_ATTRIBUTE(ssi_sst_div_fops, ssi_div_get, ssi_div_set, "%llu\n"); 152 153 static void ssi_debug_add_port(struct omap_ssi_port *omap_port, 154 struct dentry *dir) 155 { 156 struct hsi_port *port = to_hsi_port(omap_port->dev); 157 158 dir = debugfs_create_dir(dev_name(omap_port->dev), dir); 159 omap_port->dir = dir; 160 debugfs_create_file("regs", S_IRUGO, dir, port, &ssi_port_regs_fops); 161 dir = debugfs_create_dir("sst", dir); 162 debugfs_create_file_unsafe("divisor", 0644, dir, port, 163 &ssi_sst_div_fops); 164 } 165 #endif 166 167 static void ssi_process_errqueue(struct work_struct *work) 168 { 169 struct omap_ssi_port *omap_port; 170 struct list_head *head, *tmp; 171 struct hsi_msg *msg; 172 173 omap_port = container_of(work, struct omap_ssi_port, errqueue_work.work); 174 175 list_for_each_safe(head, tmp, &omap_port->errqueue) { 176 msg = list_entry(head, struct hsi_msg, link); 177 msg->complete(msg); 178 list_del(head); 179 } 180 } 181 182 static int ssi_claim_lch(struct hsi_msg *msg) 183 { 184 185 struct hsi_port *port = hsi_get_port(msg->cl); 186 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 187 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 188 int lch; 189 190 for (lch = 0; lch < SSI_MAX_GDD_LCH; lch++) 191 if (!omap_ssi->gdd_trn[lch].msg) { 192 omap_ssi->gdd_trn[lch].msg = msg; 193 omap_ssi->gdd_trn[lch].sg = msg->sgt.sgl; 194 return lch; 195 } 196 197 return -EBUSY; 198 } 199 200 static int ssi_start_dma(struct hsi_msg *msg, int lch) 201 { 202 struct hsi_port *port = hsi_get_port(msg->cl); 203 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 204 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 205 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 206 void __iomem *gdd = omap_ssi->gdd; 207 int err; 208 u16 csdp; 209 u16 ccr; 210 u32 s_addr; 211 u32 d_addr; 212 u32 tmp; 213 214 /* Hold clocks during the transfer */ 215 pm_runtime_get(omap_port->pdev); 216 217 if (!pm_runtime_active(omap_port->pdev)) { 218 dev_warn(&port->device, "ssi_start_dma called without runtime PM!\n"); 219 pm_runtime_put_autosuspend(omap_port->pdev); 220 return -EREMOTEIO; 221 } 222 223 if (msg->ttype == HSI_MSG_READ) { 224 err = dma_map_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents, 225 DMA_FROM_DEVICE); 226 if (!err) { 227 dev_dbg(&ssi->device, "DMA map SG failed !\n"); 228 pm_runtime_put_autosuspend(omap_port->pdev); 229 return -EIO; 230 } 231 csdp = SSI_DST_BURST_4x32_BIT | SSI_DST_MEMORY_PORT | 232 SSI_SRC_SINGLE_ACCESS0 | SSI_SRC_PERIPHERAL_PORT | 233 SSI_DATA_TYPE_S32; 234 ccr = msg->channel + 0x10 + (port->num * 8); /* Sync */ 235 ccr |= SSI_DST_AMODE_POSTINC | SSI_SRC_AMODE_CONST | 236 SSI_CCR_ENABLE; 237 s_addr = omap_port->ssr_dma + 238 SSI_SSR_BUFFER_CH_REG(msg->channel); 239 d_addr = sg_dma_address(msg->sgt.sgl); 240 } else { 241 err = dma_map_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents, 242 DMA_TO_DEVICE); 243 if (!err) { 244 dev_dbg(&ssi->device, "DMA map SG failed !\n"); 245 pm_runtime_put_autosuspend(omap_port->pdev); 246 return -EIO; 247 } 248 csdp = SSI_SRC_BURST_4x32_BIT | SSI_SRC_MEMORY_PORT | 249 SSI_DST_SINGLE_ACCESS0 | SSI_DST_PERIPHERAL_PORT | 250 SSI_DATA_TYPE_S32; 251 ccr = (msg->channel + 1 + (port->num * 8)) & 0xf; /* Sync */ 252 ccr |= SSI_SRC_AMODE_POSTINC | SSI_DST_AMODE_CONST | 253 SSI_CCR_ENABLE; 254 s_addr = sg_dma_address(msg->sgt.sgl); 255 d_addr = omap_port->sst_dma + 256 SSI_SST_BUFFER_CH_REG(msg->channel); 257 } 258 dev_dbg(&ssi->device, "lch %d cdsp %08x ccr %04x s_addr %08x d_addr %08x\n", 259 lch, csdp, ccr, s_addr, d_addr); 260 261 writew_relaxed(csdp, gdd + SSI_GDD_CSDP_REG(lch)); 262 writew_relaxed(SSI_BLOCK_IE | SSI_TOUT_IE, gdd + SSI_GDD_CICR_REG(lch)); 263 writel_relaxed(d_addr, gdd + SSI_GDD_CDSA_REG(lch)); 264 writel_relaxed(s_addr, gdd + SSI_GDD_CSSA_REG(lch)); 265 writew_relaxed(SSI_BYTES_TO_FRAMES(msg->sgt.sgl->length), 266 gdd + SSI_GDD_CEN_REG(lch)); 267 268 spin_lock_bh(&omap_ssi->lock); 269 tmp = readl(omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 270 tmp |= SSI_GDD_LCH(lch); 271 writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 272 spin_unlock_bh(&omap_ssi->lock); 273 writew(ccr, gdd + SSI_GDD_CCR_REG(lch)); 274 msg->status = HSI_STATUS_PROCEEDING; 275 276 return 0; 277 } 278 279 static int ssi_start_pio(struct hsi_msg *msg) 280 { 281 struct hsi_port *port = hsi_get_port(msg->cl); 282 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 283 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 284 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 285 u32 val; 286 287 pm_runtime_get(omap_port->pdev); 288 289 if (!pm_runtime_active(omap_port->pdev)) { 290 dev_warn(&port->device, "ssi_start_pio called without runtime PM!\n"); 291 pm_runtime_put_autosuspend(omap_port->pdev); 292 return -EREMOTEIO; 293 } 294 295 if (msg->ttype == HSI_MSG_WRITE) { 296 val = SSI_DATAACCEPT(msg->channel); 297 /* Hold clocks for pio writes */ 298 pm_runtime_get(omap_port->pdev); 299 } else { 300 val = SSI_DATAAVAILABLE(msg->channel) | SSI_ERROROCCURED; 301 } 302 dev_dbg(&port->device, "Single %s transfer\n", 303 msg->ttype ? "write" : "read"); 304 val |= readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 305 writel(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 306 pm_runtime_put_autosuspend(omap_port->pdev); 307 msg->actual_len = 0; 308 msg->status = HSI_STATUS_PROCEEDING; 309 310 return 0; 311 } 312 313 static int ssi_start_transfer(struct list_head *queue) 314 { 315 struct hsi_msg *msg; 316 int lch = -1; 317 318 if (list_empty(queue)) 319 return 0; 320 msg = list_first_entry(queue, struct hsi_msg, link); 321 if (msg->status != HSI_STATUS_QUEUED) 322 return 0; 323 if ((msg->sgt.nents) && (msg->sgt.sgl->length > sizeof(u32))) 324 lch = ssi_claim_lch(msg); 325 if (lch >= 0) 326 return ssi_start_dma(msg, lch); 327 else 328 return ssi_start_pio(msg); 329 } 330 331 static int ssi_async_break(struct hsi_msg *msg) 332 { 333 struct hsi_port *port = hsi_get_port(msg->cl); 334 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 335 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 336 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 337 int err = 0; 338 u32 tmp; 339 340 pm_runtime_get_sync(omap_port->pdev); 341 if (msg->ttype == HSI_MSG_WRITE) { 342 if (omap_port->sst.mode != SSI_MODE_FRAME) { 343 err = -EINVAL; 344 goto out; 345 } 346 writel(1, omap_port->sst_base + SSI_SST_BREAK_REG); 347 msg->status = HSI_STATUS_COMPLETED; 348 msg->complete(msg); 349 } else { 350 if (omap_port->ssr.mode != SSI_MODE_FRAME) { 351 err = -EINVAL; 352 goto out; 353 } 354 spin_lock_bh(&omap_port->lock); 355 tmp = readl(omap_ssi->sys + 356 SSI_MPU_ENABLE_REG(port->num, 0)); 357 writel(tmp | SSI_BREAKDETECTED, 358 omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 359 msg->status = HSI_STATUS_PROCEEDING; 360 list_add_tail(&msg->link, &omap_port->brkqueue); 361 spin_unlock_bh(&omap_port->lock); 362 } 363 out: 364 pm_runtime_put_autosuspend(omap_port->pdev); 365 366 return err; 367 } 368 369 static int ssi_async(struct hsi_msg *msg) 370 { 371 struct hsi_port *port = hsi_get_port(msg->cl); 372 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 373 struct list_head *queue; 374 int err = 0; 375 376 BUG_ON(!msg); 377 378 if (msg->sgt.nents > 1) 379 return -ENOSYS; /* TODO: Add sg support */ 380 381 if (msg->break_frame) 382 return ssi_async_break(msg); 383 384 if (msg->ttype) { 385 BUG_ON(msg->channel >= omap_port->sst.channels); 386 queue = &omap_port->txqueue[msg->channel]; 387 } else { 388 BUG_ON(msg->channel >= omap_port->ssr.channels); 389 queue = &omap_port->rxqueue[msg->channel]; 390 } 391 msg->status = HSI_STATUS_QUEUED; 392 393 pm_runtime_get_sync(omap_port->pdev); 394 spin_lock_bh(&omap_port->lock); 395 list_add_tail(&msg->link, queue); 396 err = ssi_start_transfer(queue); 397 if (err < 0) { 398 list_del(&msg->link); 399 msg->status = HSI_STATUS_ERROR; 400 } 401 spin_unlock_bh(&omap_port->lock); 402 pm_runtime_put_autosuspend(omap_port->pdev); 403 dev_dbg(&port->device, "msg status %d ttype %d ch %d\n", 404 msg->status, msg->ttype, msg->channel); 405 406 return err; 407 } 408 409 static u32 ssi_calculate_div(struct hsi_controller *ssi) 410 { 411 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 412 u32 tx_fckrate = (u32) omap_ssi->fck_rate; 413 414 /* / 2 : SSI TX clock is always half of the SSI functional clock */ 415 tx_fckrate >>= 1; 416 /* Round down when tx_fckrate % omap_ssi->max_speed == 0 */ 417 tx_fckrate--; 418 dev_dbg(&ssi->device, "TX div %d for fck_rate %lu Khz speed %d Kb/s\n", 419 tx_fckrate / omap_ssi->max_speed, omap_ssi->fck_rate, 420 omap_ssi->max_speed); 421 422 return tx_fckrate / omap_ssi->max_speed; 423 } 424 425 static void ssi_flush_queue(struct list_head *queue, struct hsi_client *cl) 426 { 427 struct list_head *node, *tmp; 428 struct hsi_msg *msg; 429 430 list_for_each_safe(node, tmp, queue) { 431 msg = list_entry(node, struct hsi_msg, link); 432 if ((cl) && (cl != msg->cl)) 433 continue; 434 list_del(node); 435 pr_debug("flush queue: ch %d, msg %p len %d type %d ctxt %p\n", 436 msg->channel, msg, msg->sgt.sgl->length, 437 msg->ttype, msg->context); 438 if (msg->destructor) 439 msg->destructor(msg); 440 else 441 hsi_free_msg(msg); 442 } 443 } 444 445 static int ssi_setup(struct hsi_client *cl) 446 { 447 struct hsi_port *port = to_hsi_port(cl->device.parent); 448 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 449 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 450 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 451 void __iomem *sst = omap_port->sst_base; 452 void __iomem *ssr = omap_port->ssr_base; 453 u32 div; 454 int err = 0; 455 456 pm_runtime_get_sync(omap_port->pdev); 457 spin_lock_bh(&omap_port->lock); 458 if (cl->tx_cfg.speed) 459 omap_ssi->max_speed = cl->tx_cfg.speed; 460 div = ssi_calculate_div(ssi); 461 if (div > SSI_MAX_DIVISOR) { 462 dev_err(&cl->device, "Invalid TX speed %d Mb/s (div %d)\n", 463 cl->tx_cfg.speed, div); 464 err = -EINVAL; 465 goto out; 466 } 467 /* Set TX/RX module to sleep to stop TX/RX during cfg update */ 468 writel_relaxed(SSI_MODE_SLEEP, sst + SSI_SST_MODE_REG); 469 writel_relaxed(SSI_MODE_SLEEP, ssr + SSI_SSR_MODE_REG); 470 /* Flush posted write */ 471 readl(ssr + SSI_SSR_MODE_REG); 472 /* TX */ 473 writel_relaxed(31, sst + SSI_SST_FRAMESIZE_REG); 474 writel_relaxed(div, sst + SSI_SST_DIVISOR_REG); 475 writel_relaxed(cl->tx_cfg.num_hw_channels, sst + SSI_SST_CHANNELS_REG); 476 writel_relaxed(cl->tx_cfg.arb_mode, sst + SSI_SST_ARBMODE_REG); 477 writel_relaxed(cl->tx_cfg.mode, sst + SSI_SST_MODE_REG); 478 /* RX */ 479 writel_relaxed(31, ssr + SSI_SSR_FRAMESIZE_REG); 480 writel_relaxed(cl->rx_cfg.num_hw_channels, ssr + SSI_SSR_CHANNELS_REG); 481 writel_relaxed(0, ssr + SSI_SSR_TIMEOUT_REG); 482 /* Cleanup the break queue if we leave FRAME mode */ 483 if ((omap_port->ssr.mode == SSI_MODE_FRAME) && 484 (cl->rx_cfg.mode != SSI_MODE_FRAME)) 485 ssi_flush_queue(&omap_port->brkqueue, cl); 486 writel_relaxed(cl->rx_cfg.mode, ssr + SSI_SSR_MODE_REG); 487 omap_port->channels = max(cl->rx_cfg.num_hw_channels, 488 cl->tx_cfg.num_hw_channels); 489 /* Shadow registering for OFF mode */ 490 /* SST */ 491 omap_port->sst.divisor = div; 492 omap_port->sst.frame_size = 31; 493 omap_port->sst.channels = cl->tx_cfg.num_hw_channels; 494 omap_port->sst.arb_mode = cl->tx_cfg.arb_mode; 495 omap_port->sst.mode = cl->tx_cfg.mode; 496 /* SSR */ 497 omap_port->ssr.frame_size = 31; 498 omap_port->ssr.timeout = 0; 499 omap_port->ssr.channels = cl->rx_cfg.num_hw_channels; 500 omap_port->ssr.mode = cl->rx_cfg.mode; 501 out: 502 spin_unlock_bh(&omap_port->lock); 503 pm_runtime_put_autosuspend(omap_port->pdev); 504 505 return err; 506 } 507 508 static int ssi_flush(struct hsi_client *cl) 509 { 510 struct hsi_port *port = hsi_get_port(cl); 511 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 512 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 513 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 514 struct hsi_msg *msg; 515 void __iomem *sst = omap_port->sst_base; 516 void __iomem *ssr = omap_port->ssr_base; 517 unsigned int i; 518 u32 err; 519 520 pm_runtime_get_sync(omap_port->pdev); 521 spin_lock_bh(&omap_port->lock); 522 523 /* stop all ssi communication */ 524 pinctrl_pm_select_idle_state(omap_port->pdev); 525 udelay(1); /* wait for racing frames */ 526 527 /* Stop all DMA transfers */ 528 for (i = 0; i < SSI_MAX_GDD_LCH; i++) { 529 msg = omap_ssi->gdd_trn[i].msg; 530 if (!msg || (port != hsi_get_port(msg->cl))) 531 continue; 532 writew_relaxed(0, omap_ssi->gdd + SSI_GDD_CCR_REG(i)); 533 if (msg->ttype == HSI_MSG_READ) 534 pm_runtime_put_autosuspend(omap_port->pdev); 535 omap_ssi->gdd_trn[i].msg = NULL; 536 } 537 /* Flush all SST buffers */ 538 writel_relaxed(0, sst + SSI_SST_BUFSTATE_REG); 539 writel_relaxed(0, sst + SSI_SST_TXSTATE_REG); 540 /* Flush all SSR buffers */ 541 writel_relaxed(0, ssr + SSI_SSR_RXSTATE_REG); 542 writel_relaxed(0, ssr + SSI_SSR_BUFSTATE_REG); 543 /* Flush all errors */ 544 err = readl(ssr + SSI_SSR_ERROR_REG); 545 writel_relaxed(err, ssr + SSI_SSR_ERRORACK_REG); 546 /* Flush break */ 547 writel_relaxed(0, ssr + SSI_SSR_BREAK_REG); 548 /* Clear interrupts */ 549 writel_relaxed(0, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 550 writel_relaxed(0xffffff00, 551 omap_ssi->sys + SSI_MPU_STATUS_REG(port->num, 0)); 552 writel_relaxed(0, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 553 writel(0xff, omap_ssi->sys + SSI_GDD_MPU_IRQ_STATUS_REG); 554 /* Dequeue all pending requests */ 555 for (i = 0; i < omap_port->channels; i++) { 556 /* Release write clocks */ 557 if (!list_empty(&omap_port->txqueue[i])) 558 pm_runtime_put_autosuspend(omap_port->pdev); 559 ssi_flush_queue(&omap_port->txqueue[i], NULL); 560 ssi_flush_queue(&omap_port->rxqueue[i], NULL); 561 } 562 ssi_flush_queue(&omap_port->brkqueue, NULL); 563 564 /* Resume SSI communication */ 565 pinctrl_pm_select_default_state(omap_port->pdev); 566 567 spin_unlock_bh(&omap_port->lock); 568 pm_runtime_put_autosuspend(omap_port->pdev); 569 570 return 0; 571 } 572 573 static void start_tx_work(struct work_struct *work) 574 { 575 struct omap_ssi_port *omap_port = 576 container_of(work, struct omap_ssi_port, work); 577 struct hsi_port *port = to_hsi_port(omap_port->dev); 578 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 579 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 580 581 pm_runtime_get_sync(omap_port->pdev); /* Grab clocks */ 582 writel(SSI_WAKE(0), omap_ssi->sys + SSI_SET_WAKE_REG(port->num)); 583 } 584 585 static int ssi_start_tx(struct hsi_client *cl) 586 { 587 struct hsi_port *port = hsi_get_port(cl); 588 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 589 590 dev_dbg(&port->device, "Wake out high %d\n", omap_port->wk_refcount); 591 592 spin_lock_bh(&omap_port->wk_lock); 593 if (omap_port->wk_refcount++) { 594 spin_unlock_bh(&omap_port->wk_lock); 595 return 0; 596 } 597 spin_unlock_bh(&omap_port->wk_lock); 598 599 schedule_work(&omap_port->work); 600 601 return 0; 602 } 603 604 static int ssi_stop_tx(struct hsi_client *cl) 605 { 606 struct hsi_port *port = hsi_get_port(cl); 607 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 608 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 609 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 610 611 dev_dbg(&port->device, "Wake out low %d\n", omap_port->wk_refcount); 612 613 spin_lock_bh(&omap_port->wk_lock); 614 BUG_ON(!omap_port->wk_refcount); 615 if (--omap_port->wk_refcount) { 616 spin_unlock_bh(&omap_port->wk_lock); 617 return 0; 618 } 619 writel(SSI_WAKE(0), omap_ssi->sys + SSI_CLEAR_WAKE_REG(port->num)); 620 spin_unlock_bh(&omap_port->wk_lock); 621 622 pm_runtime_put_autosuspend(omap_port->pdev); /* Release clocks */ 623 624 625 return 0; 626 } 627 628 static void ssi_transfer(struct omap_ssi_port *omap_port, 629 struct list_head *queue) 630 { 631 struct hsi_msg *msg; 632 int err = -1; 633 634 pm_runtime_get(omap_port->pdev); 635 spin_lock_bh(&omap_port->lock); 636 while (err < 0) { 637 err = ssi_start_transfer(queue); 638 if (err < 0) { 639 msg = list_first_entry(queue, struct hsi_msg, link); 640 msg->status = HSI_STATUS_ERROR; 641 msg->actual_len = 0; 642 list_del(&msg->link); 643 spin_unlock_bh(&omap_port->lock); 644 msg->complete(msg); 645 spin_lock_bh(&omap_port->lock); 646 } 647 } 648 spin_unlock_bh(&omap_port->lock); 649 pm_runtime_put_autosuspend(omap_port->pdev); 650 } 651 652 static void ssi_cleanup_queues(struct hsi_client *cl) 653 { 654 struct hsi_port *port = hsi_get_port(cl); 655 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 656 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 657 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 658 struct hsi_msg *msg; 659 unsigned int i; 660 u32 rxbufstate = 0; 661 u32 txbufstate = 0; 662 u32 status = SSI_ERROROCCURED; 663 u32 tmp; 664 665 ssi_flush_queue(&omap_port->brkqueue, cl); 666 if (list_empty(&omap_port->brkqueue)) 667 status |= SSI_BREAKDETECTED; 668 669 for (i = 0; i < omap_port->channels; i++) { 670 if (list_empty(&omap_port->txqueue[i])) 671 continue; 672 msg = list_first_entry(&omap_port->txqueue[i], struct hsi_msg, 673 link); 674 if ((msg->cl == cl) && (msg->status == HSI_STATUS_PROCEEDING)) { 675 txbufstate |= (1 << i); 676 status |= SSI_DATAACCEPT(i); 677 /* Release the clocks writes, also GDD ones */ 678 pm_runtime_put_autosuspend(omap_port->pdev); 679 } 680 ssi_flush_queue(&omap_port->txqueue[i], cl); 681 } 682 for (i = 0; i < omap_port->channels; i++) { 683 if (list_empty(&omap_port->rxqueue[i])) 684 continue; 685 msg = list_first_entry(&omap_port->rxqueue[i], struct hsi_msg, 686 link); 687 if ((msg->cl == cl) && (msg->status == HSI_STATUS_PROCEEDING)) { 688 rxbufstate |= (1 << i); 689 status |= SSI_DATAAVAILABLE(i); 690 } 691 ssi_flush_queue(&omap_port->rxqueue[i], cl); 692 /* Check if we keep the error detection interrupt armed */ 693 if (!list_empty(&omap_port->rxqueue[i])) 694 status &= ~SSI_ERROROCCURED; 695 } 696 /* Cleanup write buffers */ 697 tmp = readl(omap_port->sst_base + SSI_SST_BUFSTATE_REG); 698 tmp &= ~txbufstate; 699 writel_relaxed(tmp, omap_port->sst_base + SSI_SST_BUFSTATE_REG); 700 /* Cleanup read buffers */ 701 tmp = readl(omap_port->ssr_base + SSI_SSR_BUFSTATE_REG); 702 tmp &= ~rxbufstate; 703 writel_relaxed(tmp, omap_port->ssr_base + SSI_SSR_BUFSTATE_REG); 704 /* Disarm and ack pending interrupts */ 705 tmp = readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 706 tmp &= ~status; 707 writel_relaxed(tmp, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 708 writel_relaxed(status, omap_ssi->sys + 709 SSI_MPU_STATUS_REG(port->num, 0)); 710 } 711 712 static void ssi_cleanup_gdd(struct hsi_controller *ssi, struct hsi_client *cl) 713 { 714 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 715 struct hsi_port *port = hsi_get_port(cl); 716 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 717 struct hsi_msg *msg; 718 unsigned int i; 719 u32 val = 0; 720 u32 tmp; 721 722 for (i = 0; i < SSI_MAX_GDD_LCH; i++) { 723 msg = omap_ssi->gdd_trn[i].msg; 724 if ((!msg) || (msg->cl != cl)) 725 continue; 726 writew_relaxed(0, omap_ssi->gdd + SSI_GDD_CCR_REG(i)); 727 val |= (1 << i); 728 /* 729 * Clock references for write will be handled in 730 * ssi_cleanup_queues 731 */ 732 if (msg->ttype == HSI_MSG_READ) { 733 pm_runtime_put_autosuspend(omap_port->pdev); 734 } 735 omap_ssi->gdd_trn[i].msg = NULL; 736 } 737 tmp = readl_relaxed(omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 738 tmp &= ~val; 739 writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 740 writel(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_STATUS_REG); 741 } 742 743 static int ssi_set_port_mode(struct omap_ssi_port *omap_port, u32 mode) 744 { 745 writel(mode, omap_port->sst_base + SSI_SST_MODE_REG); 746 writel(mode, omap_port->ssr_base + SSI_SSR_MODE_REG); 747 /* OCP barrier */ 748 mode = readl(omap_port->ssr_base + SSI_SSR_MODE_REG); 749 750 return 0; 751 } 752 753 static int ssi_release(struct hsi_client *cl) 754 { 755 struct hsi_port *port = hsi_get_port(cl); 756 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 757 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 758 759 pm_runtime_get_sync(omap_port->pdev); 760 spin_lock_bh(&omap_port->lock); 761 /* Stop all the pending DMA requests for that client */ 762 ssi_cleanup_gdd(ssi, cl); 763 /* Now cleanup all the queues */ 764 ssi_cleanup_queues(cl); 765 /* If it is the last client of the port, do extra checks and cleanup */ 766 if (port->claimed <= 1) { 767 /* 768 * Drop the clock reference for the incoming wake line 769 * if it is still kept high by the other side. 770 */ 771 if (test_and_clear_bit(SSI_WAKE_EN, &omap_port->flags)) 772 pm_runtime_put_sync(omap_port->pdev); 773 pm_runtime_get(omap_port->pdev); 774 /* Stop any SSI TX/RX without a client */ 775 ssi_set_port_mode(omap_port, SSI_MODE_SLEEP); 776 omap_port->sst.mode = SSI_MODE_SLEEP; 777 omap_port->ssr.mode = SSI_MODE_SLEEP; 778 pm_runtime_put(omap_port->pdev); 779 WARN_ON(omap_port->wk_refcount != 0); 780 } 781 spin_unlock_bh(&omap_port->lock); 782 pm_runtime_put_sync(omap_port->pdev); 783 784 return 0; 785 } 786 787 788 789 static void ssi_error(struct hsi_port *port) 790 { 791 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 792 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 793 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 794 struct hsi_msg *msg; 795 unsigned int i; 796 u32 err; 797 u32 val; 798 u32 tmp; 799 800 /* ACK error */ 801 err = readl(omap_port->ssr_base + SSI_SSR_ERROR_REG); 802 dev_err(&port->device, "SSI error: 0x%02x\n", err); 803 if (!err) { 804 dev_dbg(&port->device, "spurious SSI error ignored!\n"); 805 return; 806 } 807 spin_lock(&omap_ssi->lock); 808 /* Cancel all GDD read transfers */ 809 for (i = 0, val = 0; i < SSI_MAX_GDD_LCH; i++) { 810 msg = omap_ssi->gdd_trn[i].msg; 811 if ((msg) && (msg->ttype == HSI_MSG_READ)) { 812 writew_relaxed(0, omap_ssi->gdd + SSI_GDD_CCR_REG(i)); 813 val |= (1 << i); 814 omap_ssi->gdd_trn[i].msg = NULL; 815 } 816 } 817 tmp = readl(omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 818 tmp &= ~val; 819 writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG); 820 spin_unlock(&omap_ssi->lock); 821 /* Cancel all PIO read transfers */ 822 spin_lock(&omap_port->lock); 823 tmp = readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 824 tmp &= 0xfeff00ff; /* Disable error & all dataavailable interrupts */ 825 writel_relaxed(tmp, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 826 /* ACK error */ 827 writel_relaxed(err, omap_port->ssr_base + SSI_SSR_ERRORACK_REG); 828 writel_relaxed(SSI_ERROROCCURED, 829 omap_ssi->sys + SSI_MPU_STATUS_REG(port->num, 0)); 830 /* Signal the error all current pending read requests */ 831 for (i = 0; i < omap_port->channels; i++) { 832 if (list_empty(&omap_port->rxqueue[i])) 833 continue; 834 msg = list_first_entry(&omap_port->rxqueue[i], struct hsi_msg, 835 link); 836 list_del(&msg->link); 837 msg->status = HSI_STATUS_ERROR; 838 spin_unlock(&omap_port->lock); 839 msg->complete(msg); 840 /* Now restart queued reads if any */ 841 ssi_transfer(omap_port, &omap_port->rxqueue[i]); 842 spin_lock(&omap_port->lock); 843 } 844 spin_unlock(&omap_port->lock); 845 } 846 847 static void ssi_break_complete(struct hsi_port *port) 848 { 849 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 850 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 851 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 852 struct hsi_msg *msg; 853 struct hsi_msg *tmp; 854 u32 val; 855 856 dev_dbg(&port->device, "HWBREAK received\n"); 857 858 spin_lock(&omap_port->lock); 859 val = readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 860 val &= ~SSI_BREAKDETECTED; 861 writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 862 writel_relaxed(0, omap_port->ssr_base + SSI_SSR_BREAK_REG); 863 writel(SSI_BREAKDETECTED, 864 omap_ssi->sys + SSI_MPU_STATUS_REG(port->num, 0)); 865 spin_unlock(&omap_port->lock); 866 867 list_for_each_entry_safe(msg, tmp, &omap_port->brkqueue, link) { 868 msg->status = HSI_STATUS_COMPLETED; 869 spin_lock(&omap_port->lock); 870 list_del(&msg->link); 871 spin_unlock(&omap_port->lock); 872 msg->complete(msg); 873 } 874 875 } 876 877 static void ssi_pio_complete(struct hsi_port *port, struct list_head *queue) 878 { 879 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 880 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 881 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 882 struct hsi_msg *msg; 883 u32 *buf; 884 u32 reg; 885 u32 val; 886 887 spin_lock_bh(&omap_port->lock); 888 msg = list_first_entry(queue, struct hsi_msg, link); 889 if ((!msg->sgt.nents) || (!msg->sgt.sgl->length)) { 890 msg->actual_len = 0; 891 msg->status = HSI_STATUS_PENDING; 892 } 893 if (msg->ttype == HSI_MSG_WRITE) 894 val = SSI_DATAACCEPT(msg->channel); 895 else 896 val = SSI_DATAAVAILABLE(msg->channel); 897 if (msg->status == HSI_STATUS_PROCEEDING) { 898 buf = sg_virt(msg->sgt.sgl) + msg->actual_len; 899 if (msg->ttype == HSI_MSG_WRITE) 900 writel(*buf, omap_port->sst_base + 901 SSI_SST_BUFFER_CH_REG(msg->channel)); 902 else 903 *buf = readl(omap_port->ssr_base + 904 SSI_SSR_BUFFER_CH_REG(msg->channel)); 905 dev_dbg(&port->device, "ch %d ttype %d 0x%08x\n", msg->channel, 906 msg->ttype, *buf); 907 msg->actual_len += sizeof(*buf); 908 if (msg->actual_len >= msg->sgt.sgl->length) 909 msg->status = HSI_STATUS_COMPLETED; 910 /* 911 * Wait for the last written frame to be really sent before 912 * we call the complete callback 913 */ 914 if ((msg->status == HSI_STATUS_PROCEEDING) || 915 ((msg->status == HSI_STATUS_COMPLETED) && 916 (msg->ttype == HSI_MSG_WRITE))) { 917 writel(val, omap_ssi->sys + 918 SSI_MPU_STATUS_REG(port->num, 0)); 919 spin_unlock_bh(&omap_port->lock); 920 921 return; 922 } 923 924 } 925 /* Transfer completed at this point */ 926 reg = readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 927 if (msg->ttype == HSI_MSG_WRITE) { 928 /* Release clocks for write transfer */ 929 pm_runtime_put_autosuspend(omap_port->pdev); 930 } 931 reg &= ~val; 932 writel_relaxed(reg, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 933 writel_relaxed(val, omap_ssi->sys + SSI_MPU_STATUS_REG(port->num, 0)); 934 list_del(&msg->link); 935 spin_unlock_bh(&omap_port->lock); 936 msg->complete(msg); 937 ssi_transfer(omap_port, queue); 938 } 939 940 static irqreturn_t ssi_pio_thread(int irq, void *ssi_port) 941 { 942 struct hsi_port *port = (struct hsi_port *)ssi_port; 943 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 944 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 945 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 946 void __iomem *sys = omap_ssi->sys; 947 unsigned int ch; 948 u32 status_reg; 949 950 pm_runtime_get_sync(omap_port->pdev); 951 952 do { 953 status_reg = readl(sys + SSI_MPU_STATUS_REG(port->num, 0)); 954 status_reg &= readl(sys + SSI_MPU_ENABLE_REG(port->num, 0)); 955 956 for (ch = 0; ch < omap_port->channels; ch++) { 957 if (status_reg & SSI_DATAACCEPT(ch)) 958 ssi_pio_complete(port, &omap_port->txqueue[ch]); 959 if (status_reg & SSI_DATAAVAILABLE(ch)) 960 ssi_pio_complete(port, &omap_port->rxqueue[ch]); 961 } 962 if (status_reg & SSI_BREAKDETECTED) 963 ssi_break_complete(port); 964 if (status_reg & SSI_ERROROCCURED) 965 ssi_error(port); 966 967 status_reg = readl(sys + SSI_MPU_STATUS_REG(port->num, 0)); 968 status_reg &= readl(sys + SSI_MPU_ENABLE_REG(port->num, 0)); 969 970 /* TODO: sleep if we retry? */ 971 } while (status_reg); 972 973 pm_runtime_put_autosuspend(omap_port->pdev); 974 975 return IRQ_HANDLED; 976 } 977 978 static irqreturn_t ssi_wake_thread(int irq __maybe_unused, void *ssi_port) 979 { 980 struct hsi_port *port = (struct hsi_port *)ssi_port; 981 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 982 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 983 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 984 985 if (ssi_wakein(port)) { 986 /** 987 * We can have a quick High-Low-High transition in the line. 988 * In such a case if we have long interrupt latencies, 989 * we can miss the low event or get twice a high event. 990 * This workaround will avoid breaking the clock reference 991 * count when such a situation ocurrs. 992 */ 993 if (!test_and_set_bit(SSI_WAKE_EN, &omap_port->flags)) 994 pm_runtime_get_sync(omap_port->pdev); 995 dev_dbg(&ssi->device, "Wake in high\n"); 996 if (omap_port->wktest) { /* FIXME: HACK ! To be removed */ 997 writel(SSI_WAKE(0), 998 omap_ssi->sys + SSI_SET_WAKE_REG(port->num)); 999 } 1000 hsi_event(port, HSI_EVENT_START_RX); 1001 } else { 1002 dev_dbg(&ssi->device, "Wake in low\n"); 1003 if (omap_port->wktest) { /* FIXME: HACK ! To be removed */ 1004 writel(SSI_WAKE(0), 1005 omap_ssi->sys + SSI_CLEAR_WAKE_REG(port->num)); 1006 } 1007 hsi_event(port, HSI_EVENT_STOP_RX); 1008 if (test_and_clear_bit(SSI_WAKE_EN, &omap_port->flags)) { 1009 pm_runtime_put_autosuspend(omap_port->pdev); 1010 } 1011 } 1012 1013 return IRQ_HANDLED; 1014 } 1015 1016 static int ssi_port_irq(struct hsi_port *port, struct platform_device *pd) 1017 { 1018 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 1019 int err; 1020 1021 err = platform_get_irq(pd, 0); 1022 if (err < 0) 1023 return err; 1024 omap_port->irq = err; 1025 err = devm_request_threaded_irq(&port->device, omap_port->irq, NULL, 1026 ssi_pio_thread, IRQF_ONESHOT, "SSI PORT", port); 1027 return err; 1028 } 1029 1030 static int ssi_wake_irq(struct hsi_port *port, struct platform_device *pd) 1031 { 1032 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 1033 int cawake_irq; 1034 int err; 1035 1036 if (!omap_port->wake_gpio) { 1037 omap_port->wake_irq = -1; 1038 return 0; 1039 } 1040 1041 cawake_irq = gpiod_to_irq(omap_port->wake_gpio); 1042 omap_port->wake_irq = cawake_irq; 1043 1044 err = devm_request_threaded_irq(&port->device, cawake_irq, NULL, 1045 ssi_wake_thread, 1046 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1047 "SSI cawake", port); 1048 err = enable_irq_wake(cawake_irq); 1049 if (err < 0) 1050 dev_err(&port->device, "Enable wake on the wakeline in irq %d failed %d\n", 1051 cawake_irq, err); 1052 1053 return err; 1054 } 1055 1056 static void ssi_queues_init(struct omap_ssi_port *omap_port) 1057 { 1058 unsigned int ch; 1059 1060 for (ch = 0; ch < SSI_MAX_CHANNELS; ch++) { 1061 INIT_LIST_HEAD(&omap_port->txqueue[ch]); 1062 INIT_LIST_HEAD(&omap_port->rxqueue[ch]); 1063 } 1064 INIT_LIST_HEAD(&omap_port->brkqueue); 1065 } 1066 1067 static int ssi_port_get_iomem(struct platform_device *pd, 1068 const char *name, void __iomem **pbase, dma_addr_t *phy) 1069 { 1070 struct hsi_port *port = platform_get_drvdata(pd); 1071 struct resource *mem; 1072 struct resource *ioarea; 1073 void __iomem *base; 1074 1075 mem = platform_get_resource_byname(pd, IORESOURCE_MEM, name); 1076 if (!mem) { 1077 dev_err(&pd->dev, "IO memory region missing (%s)\n", name); 1078 return -ENXIO; 1079 } 1080 ioarea = devm_request_mem_region(&port->device, mem->start, 1081 resource_size(mem), dev_name(&pd->dev)); 1082 if (!ioarea) { 1083 dev_err(&pd->dev, "%s IO memory region request failed\n", 1084 mem->name); 1085 return -ENXIO; 1086 } 1087 base = devm_ioremap(&port->device, mem->start, resource_size(mem)); 1088 if (!base) { 1089 dev_err(&pd->dev, "%s IO remap failed\n", mem->name); 1090 return -ENXIO; 1091 } 1092 *pbase = base; 1093 1094 if (phy) 1095 *phy = mem->start; 1096 1097 return 0; 1098 } 1099 1100 static int ssi_port_probe(struct platform_device *pd) 1101 { 1102 struct device_node *np = pd->dev.of_node; 1103 struct hsi_port *port; 1104 struct omap_ssi_port *omap_port; 1105 struct hsi_controller *ssi = dev_get_drvdata(pd->dev.parent); 1106 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 1107 struct gpio_desc *cawake_gpio = NULL; 1108 u32 port_id; 1109 int err; 1110 1111 dev_dbg(&pd->dev, "init ssi port...\n"); 1112 1113 if (!omap_ssi->port) { 1114 dev_err(&pd->dev, "ssi controller not initialized!\n"); 1115 err = -ENODEV; 1116 goto error; 1117 } 1118 1119 /* get id of first uninitialized port in controller */ 1120 for (port_id = 0; port_id < ssi->num_ports && omap_ssi->port[port_id]; 1121 port_id++) 1122 ; 1123 1124 if (port_id >= ssi->num_ports) { 1125 dev_err(&pd->dev, "port id out of range!\n"); 1126 err = -ENODEV; 1127 goto error; 1128 } 1129 1130 port = ssi->port[port_id]; 1131 1132 if (!np) { 1133 dev_err(&pd->dev, "missing device tree data\n"); 1134 err = -EINVAL; 1135 goto error; 1136 } 1137 1138 cawake_gpio = devm_gpiod_get(&pd->dev, "ti,ssi-cawake", GPIOD_IN); 1139 if (IS_ERR(cawake_gpio)) { 1140 err = PTR_ERR(cawake_gpio); 1141 dev_err(&pd->dev, "couldn't get cawake gpio (err=%d)!\n", err); 1142 goto error; 1143 } 1144 1145 omap_port = devm_kzalloc(&port->device, sizeof(*omap_port), GFP_KERNEL); 1146 if (!omap_port) { 1147 err = -ENOMEM; 1148 goto error; 1149 } 1150 omap_port->wake_gpio = cawake_gpio; 1151 omap_port->pdev = &pd->dev; 1152 omap_port->port_id = port_id; 1153 1154 INIT_DEFERRABLE_WORK(&omap_port->errqueue_work, ssi_process_errqueue); 1155 INIT_WORK(&omap_port->work, start_tx_work); 1156 1157 /* initialize HSI port */ 1158 port->async = ssi_async; 1159 port->setup = ssi_setup; 1160 port->flush = ssi_flush; 1161 port->start_tx = ssi_start_tx; 1162 port->stop_tx = ssi_stop_tx; 1163 port->release = ssi_release; 1164 hsi_port_set_drvdata(port, omap_port); 1165 omap_ssi->port[port_id] = omap_port; 1166 1167 platform_set_drvdata(pd, port); 1168 1169 err = ssi_port_get_iomem(pd, "tx", &omap_port->sst_base, 1170 &omap_port->sst_dma); 1171 if (err < 0) 1172 goto error; 1173 err = ssi_port_get_iomem(pd, "rx", &omap_port->ssr_base, 1174 &omap_port->ssr_dma); 1175 if (err < 0) 1176 goto error; 1177 1178 err = ssi_port_irq(port, pd); 1179 if (err < 0) 1180 goto error; 1181 err = ssi_wake_irq(port, pd); 1182 if (err < 0) 1183 goto error; 1184 1185 ssi_queues_init(omap_port); 1186 spin_lock_init(&omap_port->lock); 1187 spin_lock_init(&omap_port->wk_lock); 1188 omap_port->dev = &port->device; 1189 1190 pm_runtime_use_autosuspend(omap_port->pdev); 1191 pm_runtime_set_autosuspend_delay(omap_port->pdev, 250); 1192 pm_runtime_enable(omap_port->pdev); 1193 1194 #ifdef CONFIG_DEBUG_FS 1195 ssi_debug_add_port(omap_port, omap_ssi->dir); 1196 #endif 1197 1198 hsi_add_clients_from_dt(port, np); 1199 1200 dev_info(&pd->dev, "ssi port %u successfully initialized\n", port_id); 1201 1202 return 0; 1203 1204 error: 1205 return err; 1206 } 1207 1208 static void ssi_port_remove(struct platform_device *pd) 1209 { 1210 struct hsi_port *port = platform_get_drvdata(pd); 1211 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 1212 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 1213 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 1214 1215 #ifdef CONFIG_DEBUG_FS 1216 ssi_debug_remove_port(port); 1217 #endif 1218 1219 cancel_delayed_work_sync(&omap_port->errqueue_work); 1220 1221 hsi_port_unregister_clients(port); 1222 1223 port->async = hsi_dummy_msg; 1224 port->setup = hsi_dummy_cl; 1225 port->flush = hsi_dummy_cl; 1226 port->start_tx = hsi_dummy_cl; 1227 port->stop_tx = hsi_dummy_cl; 1228 port->release = hsi_dummy_cl; 1229 1230 omap_ssi->port[omap_port->port_id] = NULL; 1231 platform_set_drvdata(pd, NULL); 1232 1233 pm_runtime_dont_use_autosuspend(&pd->dev); 1234 pm_runtime_disable(&pd->dev); 1235 } 1236 1237 static int ssi_restore_divisor(struct omap_ssi_port *omap_port) 1238 { 1239 writel_relaxed(omap_port->sst.divisor, 1240 omap_port->sst_base + SSI_SST_DIVISOR_REG); 1241 1242 return 0; 1243 } 1244 1245 void omap_ssi_port_update_fclk(struct hsi_controller *ssi, 1246 struct omap_ssi_port *omap_port) 1247 { 1248 /* update divisor */ 1249 u32 div = ssi_calculate_div(ssi); 1250 omap_port->sst.divisor = div; 1251 ssi_restore_divisor(omap_port); 1252 } 1253 1254 #ifdef CONFIG_PM 1255 static int ssi_save_port_ctx(struct omap_ssi_port *omap_port) 1256 { 1257 struct hsi_port *port = to_hsi_port(omap_port->dev); 1258 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 1259 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 1260 1261 omap_port->sys_mpu_enable = readl(omap_ssi->sys + 1262 SSI_MPU_ENABLE_REG(port->num, 0)); 1263 1264 return 0; 1265 } 1266 1267 static int ssi_restore_port_ctx(struct omap_ssi_port *omap_port) 1268 { 1269 struct hsi_port *port = to_hsi_port(omap_port->dev); 1270 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 1271 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 1272 void __iomem *base; 1273 1274 writel_relaxed(omap_port->sys_mpu_enable, 1275 omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); 1276 1277 /* SST context */ 1278 base = omap_port->sst_base; 1279 writel_relaxed(omap_port->sst.frame_size, base + SSI_SST_FRAMESIZE_REG); 1280 writel_relaxed(omap_port->sst.channels, base + SSI_SST_CHANNELS_REG); 1281 writel_relaxed(omap_port->sst.arb_mode, base + SSI_SST_ARBMODE_REG); 1282 1283 /* SSR context */ 1284 base = omap_port->ssr_base; 1285 writel_relaxed(omap_port->ssr.frame_size, base + SSI_SSR_FRAMESIZE_REG); 1286 writel_relaxed(omap_port->ssr.channels, base + SSI_SSR_CHANNELS_REG); 1287 writel_relaxed(omap_port->ssr.timeout, base + SSI_SSR_TIMEOUT_REG); 1288 1289 return 0; 1290 } 1291 1292 static int ssi_restore_port_mode(struct omap_ssi_port *omap_port) 1293 { 1294 writel_relaxed(omap_port->sst.mode, 1295 omap_port->sst_base + SSI_SST_MODE_REG); 1296 writel_relaxed(omap_port->ssr.mode, 1297 omap_port->ssr_base + SSI_SSR_MODE_REG); 1298 /* OCP barrier */ 1299 readl(omap_port->ssr_base + SSI_SSR_MODE_REG); 1300 1301 return 0; 1302 } 1303 1304 static int omap_ssi_port_runtime_suspend(struct device *dev) 1305 { 1306 struct hsi_port *port = dev_get_drvdata(dev); 1307 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 1308 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 1309 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 1310 1311 dev_dbg(dev, "port runtime suspend!\n"); 1312 1313 ssi_set_port_mode(omap_port, SSI_MODE_SLEEP); 1314 if (omap_ssi->get_loss) 1315 omap_port->loss_count = 1316 omap_ssi->get_loss(ssi->device.parent); 1317 ssi_save_port_ctx(omap_port); 1318 1319 return 0; 1320 } 1321 1322 static int omap_ssi_port_runtime_resume(struct device *dev) 1323 { 1324 struct hsi_port *port = dev_get_drvdata(dev); 1325 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); 1326 struct hsi_controller *ssi = to_hsi_controller(port->device.parent); 1327 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); 1328 1329 dev_dbg(dev, "port runtime resume!\n"); 1330 1331 if ((omap_ssi->get_loss) && (omap_port->loss_count == 1332 omap_ssi->get_loss(ssi->device.parent))) 1333 goto mode; /* We always need to restore the mode & TX divisor */ 1334 1335 ssi_restore_port_ctx(omap_port); 1336 1337 mode: 1338 ssi_restore_divisor(omap_port); 1339 ssi_restore_port_mode(omap_port); 1340 1341 return 0; 1342 } 1343 1344 static const struct dev_pm_ops omap_ssi_port_pm_ops = { 1345 SET_RUNTIME_PM_OPS(omap_ssi_port_runtime_suspend, 1346 omap_ssi_port_runtime_resume, NULL) 1347 }; 1348 1349 #define DEV_PM_OPS (&omap_ssi_port_pm_ops) 1350 #else 1351 #define DEV_PM_OPS NULL 1352 #endif 1353 1354 1355 #ifdef CONFIG_OF 1356 static const struct of_device_id omap_ssi_port_of_match[] = { 1357 { .compatible = "ti,omap3-ssi-port", }, 1358 {}, 1359 }; 1360 MODULE_DEVICE_TABLE(of, omap_ssi_port_of_match); 1361 #else 1362 #define omap_ssi_port_of_match NULL 1363 #endif 1364 1365 struct platform_driver ssi_port_pdriver = { 1366 .probe = ssi_port_probe, 1367 .remove = ssi_port_remove, 1368 .driver = { 1369 .name = "omap_ssi_port", 1370 .of_match_table = omap_ssi_port_of_match, 1371 .pm = DEV_PM_OPS, 1372 }, 1373 }; 1374