1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2024 Intel Corporation */ 3 4 #ifndef _QUICKSPI_DEV_H_ 5 #define _QUICKSPI_DEV_H_ 6 7 #include <linux/bits.h> 8 #include <linux/hid-over-spi.h> 9 #include <linux/sizes.h> 10 #include <linux/wait.h> 11 #include <linux/workqueue.h> 12 13 #include "quickspi-protocol.h" 14 15 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT1 0x7E49 16 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT2 0x7E4B 17 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT1 0xA849 18 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT2 0xA84B 19 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT1 0xE349 20 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT2 0xE34B 21 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT1 0xE449 22 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT2 0xE44B 23 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT1 0x4D49 24 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT2 0x4D4B 25 #define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT1 0x7749 26 #define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT2 0x774B 27 #define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT1 0xD349 28 #define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT2 0xD34B 29 30 /* HIDSPI special ACPI parameters DSM methods */ 31 #define ACPI_QUICKSPI_REVISION_NUM 2 32 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_HDR_ADDR 1 33 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_BDY_ADDR 2 34 #define ACPI_QUICKSPI_FUNC_NUM_OUTPUT_REP_ADDR 3 35 #define ACPI_QUICKSPI_FUNC_NUM_READ_OPCODE 4 36 #define ACPI_QUICKSPI_FUNC_NUM_WRITE_OPCODE 5 37 #define ACPI_QUICKSPI_FUNC_NUM_IO_MODE 6 38 39 /* QickSPI device special ACPI parameters DSM methods */ 40 #define ACPI_QUICKSPI_FUNC_NUM_CONNECTION_SPEED 1 41 #define ACPI_QUICKSPI_FUNC_NUM_LIMIT_PACKET_SIZE 2 42 #define ACPI_QUICKSPI_FUNC_NUM_PERFORMANCE_LIMIT 3 43 44 /* Platform special ACPI parameters DSM methods */ 45 #define ACPI_QUICKSPI_FUNC_NUM_ACTIVE_LTR 1 46 #define ACPI_QUICKSPI_FUNC_NUM_LP_LTR 2 47 48 #define SPI_WRITE_IO_MODE BIT(13) 49 #define SPI_IO_MODE_OPCODE GENMASK(15, 14) 50 #define PERFORMANCE_LIMITATION GENMASK(15, 0) 51 52 /* Packet size value, the unit is 16 bytes */ 53 #define DEFAULT_MIN_PACKET_SIZE_VALUE 4 54 #define MAX_PACKET_SIZE_VALUE_MTL 128 55 #define MAX_PACKET_SIZE_VALUE_LNL 256 56 57 /* 58 * THC uses runtime auto suspend to dynamically switch between THC active LTR 59 * and low power LTR to save CPU power. 60 * Default value is 5000ms, that means if no touch event in this time, THC will 61 * change to low power LTR mode. 62 */ 63 #define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000 64 65 enum quickspi_dev_state { 66 QUICKSPI_NONE, 67 QUICKSPI_INITIATED, 68 QUICKSPI_RESETING, 69 QUICKSPI_RESET, 70 QUICKSPI_ENABLED, 71 QUICKSPI_DISABLED, 72 }; 73 74 /** 75 * struct quickspi_driver_data - Driver specific data for quickspi device 76 * @max_packet_size_value: identify max packet size, unit is 16 bytes 77 */ 78 struct quickspi_driver_data { 79 u32 max_packet_size_value; 80 }; 81 82 struct device; 83 struct pci_dev; 84 struct thc_device; 85 struct hid_device; 86 struct acpi_device; 87 88 /** 89 * struct quickspi_device - THC QuickSpi device struct 90 * @dev: point to kernel device 91 * @pdev: point to PCI device 92 * @thc_hw: point to THC device 93 * @hid_dev: point to hid device 94 * @acpi_dev: point to ACPI device 95 * @driver_data: point to quickspi specific driver data 96 * @state: THC SPI device state 97 * @mem_addr: MMIO memory address 98 * @dev_desc: device descriptor for HIDSPI protocol 99 * @input_report_hdr_addr: device input report header address 100 * @input_report_bdy_addr: device input report body address 101 * @output_report_bdy_addr: device output report address 102 * @spi_freq_val: device supported max SPI frequnecy, in Hz 103 * @spi_read_io_mode: device supported SPI read io mode 104 * @spi_write_io_mode: device supported SPI write io mode 105 * @spi_read_opcode: device read opcode 106 * @spi_write_opcode: device write opcode 107 * @limit_packet_size: 1 - limit read/write packet to 64Bytes 108 * 0 - device no packet size limiation for read/write 109 * @performance_limit: delay time, in ms. 110 * if device has performance limitation, must give a delay 111 * before write operation after a read operation. 112 * @active_ltr_val: THC active LTR value 113 * @low_power_ltr_val: THC low power LTR value 114 * @report_descriptor: store a copy of device report descriptor 115 * @input_buf: store a copy of latest input report data 116 * @report_buf: store a copy of latest input/output report packet from set/get feature 117 * @report_len: the length of input/output report packet 118 * @reset_ack_wq: workqueue for waiting reset response from device 119 * @reset_ack: indicate reset response received or not 120 * @nondma_int_received_wq: workqueue for waiting THC non-DMA interrupt 121 * @nondma_int_received: indicate THC non-DMA interrupt received or not 122 * @report_desc_got_wq: workqueue for waiting device report descriptor 123 * @report_desc_got: indicate device report descritor received or not 124 * @set_power_on_wq: workqueue for waiting set power on response from device 125 * @set_power_on: indicate set power on response received or not 126 * @get_feature_cmpl_wq: workqueue for waiting get feature response from device 127 * @get_feature_cmpl: indicate get feature received or not 128 * @set_feature_cmpl_wq: workqueue for waiting set feature to device 129 * @set_feature_cmpl: indicate set feature send complete or not 130 * @recover_work: Work structure for recovery 131 * @recovery_disabled: Whether recovery work is blocked during teardown 132 */ 133 struct quickspi_device { 134 struct device *dev; 135 struct pci_dev *pdev; 136 struct thc_device *thc_hw; 137 struct hid_device *hid_dev; 138 struct acpi_device *acpi_dev; 139 struct quickspi_driver_data *driver_data; 140 enum quickspi_dev_state state; 141 142 void __iomem *mem_addr; 143 144 struct hidspi_dev_descriptor dev_desc; 145 u32 input_report_hdr_addr; 146 u32 input_report_bdy_addr; 147 u32 output_report_addr; 148 u32 spi_freq_val; 149 u32 spi_read_io_mode; 150 u32 spi_write_io_mode; 151 u32 spi_read_opcode; 152 u32 spi_write_opcode; 153 u32 limit_packet_size; 154 u32 spi_packet_size; 155 u32 performance_limit; 156 157 u32 active_ltr_val; 158 u32 low_power_ltr_val; 159 160 u8 *report_descriptor; 161 u8 *input_buf; 162 u8 *report_buf; 163 u32 report_buf_size; 164 u32 report_len; 165 166 wait_queue_head_t reset_ack_wq; 167 bool reset_ack; 168 169 wait_queue_head_t nondma_int_received_wq; 170 bool nondma_int_received; 171 172 wait_queue_head_t report_desc_got_wq; 173 bool report_desc_got; 174 175 wait_queue_head_t get_report_cmpl_wq; 176 bool get_report_cmpl; 177 178 wait_queue_head_t set_report_cmpl_wq; 179 bool set_report_cmpl; 180 181 struct work_struct recover_work; 182 bool recovery_disabled; 183 }; 184 185 #endif /* _QUICKSPI_DEV_H_ */ 186