1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2024 Intel Corporation */ 3 4 #ifndef _QUICKSPI_DEV_H_ 5 #define _QUICKSPI_DEV_H_ 6 7 #include <linux/bits.h> 8 #include <linux/hid-over-spi.h> 9 #include <linux/sizes.h> 10 #include <linux/wait.h> 11 12 #include "quickspi-protocol.h" 13 14 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT1 0x7E49 15 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT2 0x7E4B 16 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT1 0xA849 17 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT2 0xA84B 18 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT1 0xE349 19 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT2 0xE34B 20 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT1 0xE449 21 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT2 0xE44B 22 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT1 0x4D49 23 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT2 0x4D4B 24 25 /* HIDSPI special ACPI parameters DSM methods */ 26 #define ACPI_QUICKSPI_REVISION_NUM 2 27 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_HDR_ADDR 1 28 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_BDY_ADDR 2 29 #define ACPI_QUICKSPI_FUNC_NUM_OUTPUT_REP_ADDR 3 30 #define ACPI_QUICKSPI_FUNC_NUM_READ_OPCODE 4 31 #define ACPI_QUICKSPI_FUNC_NUM_WRITE_OPCODE 5 32 #define ACPI_QUICKSPI_FUNC_NUM_IO_MODE 6 33 34 /* QickSPI device special ACPI parameters DSM methods */ 35 #define ACPI_QUICKSPI_FUNC_NUM_CONNECTION_SPEED 1 36 #define ACPI_QUICKSPI_FUNC_NUM_LIMIT_PACKET_SIZE 2 37 #define ACPI_QUICKSPI_FUNC_NUM_PERFORMANCE_LIMIT 3 38 39 /* Platform special ACPI parameters DSM methods */ 40 #define ACPI_QUICKSPI_FUNC_NUM_ACTIVE_LTR 1 41 #define ACPI_QUICKSPI_FUNC_NUM_LP_LTR 2 42 43 #define SPI_WRITE_IO_MODE BIT(13) 44 #define SPI_IO_MODE_OPCODE GENMASK(15, 14) 45 #define PERFORMANCE_LIMITATION GENMASK(15, 0) 46 47 /* Packet size value, the unit is 16 bytes */ 48 #define DEFAULT_MIN_PACKET_SIZE_VALUE 4 49 #define MAX_PACKET_SIZE_VALUE_MTL 128 50 #define MAX_PACKET_SIZE_VALUE_LNL 256 51 52 /* 53 * THC uses runtime auto suspend to dynamically switch between THC active LTR 54 * and low power LTR to save CPU power. 55 * Default value is 5000ms, that means if no touch event in this time, THC will 56 * change to low power LTR mode. 57 */ 58 #define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000 59 60 enum quickspi_dev_state { 61 QUICKSPI_NONE, 62 QUICKSPI_INITIATED, 63 QUICKSPI_RESETING, 64 QUICKSPI_RESET, 65 QUICKSPI_ENABLED, 66 QUICKSPI_DISABLED, 67 }; 68 69 /** 70 * struct quickspi_driver_data - Driver specific data for quickspi device 71 * @max_packet_size_value: identify max packet size, unit is 16 bytes 72 */ 73 struct quickspi_driver_data { 74 u32 max_packet_size_value; 75 }; 76 77 struct device; 78 struct pci_dev; 79 struct thc_device; 80 struct hid_device; 81 struct acpi_device; 82 83 /** 84 * struct quickspi_device - THC QuickSpi device struct 85 * @dev: point to kernel device 86 * @pdev: point to PCI device 87 * @thc_hw: point to THC device 88 * @hid_dev: point to hid device 89 * @acpi_dev: point to ACPI device 90 * @driver_data: point to quickspi specific driver data 91 * @state: THC SPI device state 92 * @mem_addr: MMIO memory address 93 * @dev_desc: device descriptor for HIDSPI protocol 94 * @input_report_hdr_addr: device input report header address 95 * @input_report_bdy_addr: device input report body address 96 * @output_report_bdy_addr: device output report address 97 * @spi_freq_val: device supported max SPI frequnecy, in Hz 98 * @spi_read_io_mode: device supported SPI read io mode 99 * @spi_write_io_mode: device supported SPI write io mode 100 * @spi_read_opcode: device read opcode 101 * @spi_write_opcode: device write opcode 102 * @limit_packet_size: 1 - limit read/write packet to 64Bytes 103 * 0 - device no packet size limiation for read/write 104 * @performance_limit: delay time, in ms. 105 * if device has performance limitation, must give a delay 106 * before write operation after a read operation. 107 * @active_ltr_val: THC active LTR value 108 * @low_power_ltr_val: THC low power LTR value 109 * @report_descriptor: store a copy of device report descriptor 110 * @input_buf: store a copy of latest input report data 111 * @report_buf: store a copy of latest input/output report packet from set/get feature 112 * @report_len: the length of input/output report packet 113 * @reset_ack_wq: workqueue for waiting reset response from device 114 * @reset_ack: indicate reset response received or not 115 * @nondma_int_received_wq: workqueue for waiting THC non-DMA interrupt 116 * @nondma_int_received: indicate THC non-DMA interrupt received or not 117 * @report_desc_got_wq: workqueue for waiting device report descriptor 118 * @report_desc_got: indicate device report descritor received or not 119 * @set_power_on_wq: workqueue for waiting set power on response from device 120 * @set_power_on: indicate set power on response received or not 121 * @get_feature_cmpl_wq: workqueue for waiting get feature response from device 122 * @get_feature_cmpl: indicate get feature received or not 123 * @set_feature_cmpl_wq: workqueue for waiting set feature to device 124 * @set_feature_cmpl: indicate set feature send complete or not 125 */ 126 struct quickspi_device { 127 struct device *dev; 128 struct pci_dev *pdev; 129 struct thc_device *thc_hw; 130 struct hid_device *hid_dev; 131 struct acpi_device *acpi_dev; 132 struct quickspi_driver_data *driver_data; 133 enum quickspi_dev_state state; 134 135 void __iomem *mem_addr; 136 137 struct hidspi_dev_descriptor dev_desc; 138 u32 input_report_hdr_addr; 139 u32 input_report_bdy_addr; 140 u32 output_report_addr; 141 u32 spi_freq_val; 142 u32 spi_read_io_mode; 143 u32 spi_write_io_mode; 144 u32 spi_read_opcode; 145 u32 spi_write_opcode; 146 u32 limit_packet_size; 147 u32 spi_packet_size; 148 u32 performance_limit; 149 150 u32 active_ltr_val; 151 u32 low_power_ltr_val; 152 153 u8 *report_descriptor; 154 u8 *input_buf; 155 u8 *report_buf; 156 u32 report_len; 157 158 wait_queue_head_t reset_ack_wq; 159 bool reset_ack; 160 161 wait_queue_head_t nondma_int_received_wq; 162 bool nondma_int_received; 163 164 wait_queue_head_t report_desc_got_wq; 165 bool report_desc_got; 166 167 wait_queue_head_t get_report_cmpl_wq; 168 bool get_report_cmpl; 169 170 wait_queue_head_t set_report_cmpl_wq; 171 bool set_report_cmpl; 172 }; 173 174 #endif /* _QUICKSPI_DEV_H_ */ 175