1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2024 Intel Corporation */ 3 4 #ifndef _QUICKI2C_DEV_H_ 5 #define _QUICKI2C_DEV_H_ 6 7 #include <linux/hid-over-i2c.h> 8 #include <linux/workqueue.h> 9 10 #include "intel-thc-dev.h" 11 12 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT1 0xA848 13 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT2 0xA84A 14 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT1 0xE348 15 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT2 0xE34A 16 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT1 0xE448 17 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT2 0xE44A 18 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT1 0x4D48 19 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT2 0x4D4A 20 #define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_I2C_PORT1 0xD348 21 #define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_I2C_PORT2 0xD34A 22 23 /* Packet size value, the unit is 16 bytes */ 24 #define MAX_PACKET_SIZE_VALUE_LNL 256 25 26 /* HIDI2C special ACPI parameters DSD name */ 27 #define QUICKI2C_ACPI_METHOD_NAME_ICRS "ICRS" 28 #define QUICKI2C_ACPI_METHOD_NAME_ISUB "ISUB" 29 30 /* HIDI2C special ACPI parameters DSM methods */ 31 #define QUICKI2C_ACPI_REVISION_NUM 1 32 #define QUICKI2C_ACPI_FUNC_NUM_HID_DESC_ADDR 1 33 #define QUICKI2C_ACPI_FUNC_NUM_ACTIVE_LTR_VAL 1 34 #define QUICKI2C_ACPI_FUNC_NUM_LP_LTR_VAL 2 35 36 #define QUICKI2C_SUBIP_STANDARD_MODE_MAX_SPEED 100000 37 #define QUICKI2C_SUBIP_FAST_MODE_MAX_SPEED 400000 38 #define QUICKI2C_SUBIP_FASTPLUS_MODE_MAX_SPEED 1000000 39 #define QUICKI2C_SUBIP_HIGH_SPEED_MODE_MAX_SPEED 3400000 40 41 #define QUICKI2C_DEFAULT_ACTIVE_LTR_VALUE 5 42 #define QUICKI2C_DEFAULT_LP_LTR_VALUE 500 43 #define QUICKI2C_RPM_TIMEOUT_MS 500 44 45 /* PTL Max packet size detection capability is 255 Bytes */ 46 #define MAX_RX_DETECT_SIZE_PTL 255 47 /* NVL Max packet size detection capability is 64K Bytes */ 48 #define MAX_RX_DETECT_SIZE_NVL 65535 49 /* Max interrupt delay capability is 2.56ms */ 50 #define MAX_RX_INTERRUPT_DELAY 256 51 52 /* Default interrupt delay is 1ms, suitable for most devices */ 53 #define DEFAULT_INTERRUPT_DELAY_US (1 * USEC_PER_MSEC) 54 55 /* 56 * THC uses runtime auto suspend to dynamically switch between THC active LTR 57 * and low power LTR to save CPU power. 58 * Default value is 5000ms, that means if no touch event in this time, THC will 59 * change to low power LTR mode. 60 */ 61 #define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000 62 63 enum quicki2c_dev_state { 64 QUICKI2C_NONE, 65 QUICKI2C_RESETING, 66 QUICKI2C_RESETED, 67 QUICKI2C_INITED, 68 QUICKI2C_ENABLED, 69 QUICKI2C_DISABLED, 70 }; 71 72 enum { 73 HIDI2C_ADDRESSING_MODE_7BIT, 74 HIDI2C_ADDRESSING_MODE_10BIT, 75 }; 76 77 /** 78 * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters 79 * @device_address: I2C device slave address 80 * @connection_speed: I2C device expected connection speed 81 * @addressing_mode: I2C device slave address mode, 7bit or 10bit 82 * 83 * Those properties get from QUICKI2C_ACPI_METHOD_NAME_ICRS method, used for 84 * Bus parameter. 85 */ 86 struct quicki2c_subip_acpi_parameter { 87 u16 device_address; 88 u64 connection_speed; 89 u8 addressing_mode; 90 u8 reserved; 91 } __packed; 92 93 /** 94 * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters 95 * @SMHX: Standard Mode (100 kbit/s) Serial Clock Line HIGH Period 96 * @SMLX: Standard Mode (100 kbit/s) Serial Clock Line LOW Period 97 * @SMTD: Standard Mode (100 kbit/s) Serial Data Line Transmit Hold Period 98 * @SMRD: Standard Mode (100 kbit/s) Serial Data Receive Hold Period 99 * @FMHX: Fast Mode (400 kbit/s) Serial Clock Line HIGH Period 100 * @FMLX: Fast Mode (400 kbit/s) Serial Clock Line LOW Period 101 * @FMTD: Fast Mode (400 kbit/s) Serial Data Line Transmit Hold Period 102 * @FMRD: Fast Mode (400 kbit/s) Serial Data Line Receive Hold Period 103 * @FMSL: Maximum length (in ic_clk_cycles) of suppressed spikes 104 * in Standard Mode, Fast Mode and Fast Mode Plus 105 * @FPHX: Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period 106 * @FPLX: Fast Mode Plus (1Mbit/sec) Serial Clock Line LOW Period 107 * @FPTD: Fast Mode Plus (1Mbit/sec) Serial Data Line Transmit HOLD Period 108 * @FPRD: Fast Mode Plus (1Mbit/sec) Serial Data Line Receive HOLD Period 109 * @HMHX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line HIGH Period 110 * @HMLX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line LOW Period 111 * @HMTD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Transmit HOLD Period 112 * @HMRD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Receive HOLD Period 113 * @HMSL: Maximum length (in ic_clk_cycles) of suppressed spikes in High Speed Mode 114 * @FSEN: Maximum Frame Size Feature Enable Control 115 * @FSVL: Maximum Frame Size Value (unit in Bytes) 116 * @INDE: Interrupt Delay Feature Enable Control 117 * @INDV: Interrupt Delay Value (unit in 10 us) 118 * 119 * Those properties get from QUICKI2C_ACPI_METHOD_NAME_ISUB method, used for 120 * I2C timing configure. 121 */ 122 struct quicki2c_subip_acpi_config { 123 u64 SMHX; 124 u64 SMLX; 125 u64 SMTD; 126 u64 SMRD; 127 128 u64 FMHX; 129 u64 FMLX; 130 u64 FMTD; 131 u64 FMRD; 132 u64 FMSL; 133 134 u64 FPHX; 135 u64 FPLX; 136 u64 FPTD; 137 u64 FPRD; 138 139 u64 HMHX; 140 u64 HMLX; 141 u64 HMTD; 142 u64 HMRD; 143 u64 HMSL; 144 145 u64 FSEN; 146 u64 FSVL; 147 u64 INDE; 148 u64 INDV; 149 u8 reserved; 150 }; 151 152 /** 153 * struct quicki2c_ddata - Driver specific data for quicki2c device 154 * @max_detect_size: Identify max packet size detect for rx 155 * @interrupt_delay: Identify max interrupt detect delay for rx 156 */ 157 struct quicki2c_ddata { 158 u32 max_detect_size; 159 u32 max_interrupt_delay; 160 }; 161 162 struct device; 163 struct pci_dev; 164 struct hid_device; 165 struct acpi_device; 166 167 /** 168 * struct quicki2c_device - THC QuickI2C device struct 169 * @dev: Point to kernel device 170 * @pdev: Point to PCI device 171 * @thc_hw: Point to THC device 172 * @hid_dev: Point to HID device 173 * @acpi_dev: Point to ACPI device 174 * @ddata: Point to QuickI2C platform specific driver data 175 * @state: THC I2C device state 176 * @mem_addr: MMIO memory address 177 * @dev_desc: Device descriptor for HIDI2C protocol 178 * @i2c_config: I2C bus configuration 179 * @hid_desc_addr: Register address for retrieve HID device descriptor 180 * @active_ltr_val: THC active LTR value 181 * @low_power_ltr_val: THC low power LTR value 182 * @report_descriptor: Store a copy of device report descriptor 183 * @input_buf: Store a copy of latest input report data 184 * @report_buf: Store a copy of latest input/output report packet from set/get feature 185 * @report_len: The length of input/output report packet 186 * @reset_ack_wq: Workqueue for waiting reset response from device 187 * @reset_ack: Indicate reset response received or not 188 * @i2c_max_frame_size_enable: Indicate max frame size feature enabled or not 189 * @i2c_max_frame_size: Max RX frame size (unit in Bytes) 190 * @i2c_int_delay_enable: Indicate interrupt delay feature enabled or not 191 * @i2c_int_delay: Interrupt detection delay value (unit in 10 us) 192 * @recover_work: Work structure for recovery 193 * @recovery_disabled: Whether recovery work is blocked during teardown 194 */ 195 struct quicki2c_device { 196 struct device *dev; 197 struct pci_dev *pdev; 198 struct thc_device *thc_hw; 199 struct hid_device *hid_dev; 200 struct acpi_device *acpi_dev; 201 const struct quicki2c_ddata *ddata; 202 enum quicki2c_dev_state state; 203 204 void __iomem *mem_addr; 205 206 struct hidi2c_dev_descriptor dev_desc; 207 struct thc_i2c_config i2c_config; 208 u16 hid_desc_addr; 209 210 u32 active_ltr_val; 211 u32 low_power_ltr_val; 212 213 u8 *report_descriptor; 214 u8 *input_buf; 215 u8 *report_buf; 216 size_t report_len; 217 218 wait_queue_head_t reset_ack_wq; 219 bool reset_ack; 220 221 u32 i2c_max_frame_size_enable; 222 u32 i2c_max_frame_size; 223 u32 i2c_int_delay_enable; 224 u32 i2c_int_delay; 225 226 struct work_struct recover_work; 227 bool recovery_disabled; 228 }; 229 230 #endif /* _QUICKI2C_DEV_H_ */ 231