1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Most ISHTP provider device and ISHTP logic declarations 4 * 5 * Copyright (c) 2003-2016, Intel Corporation. 6 */ 7 8 #ifndef _ISHTP_DEV_H_ 9 #define _ISHTP_DEV_H_ 10 11 #include <linux/types.h> 12 #include <linux/spinlock.h> 13 #include <linux/intel-ish-client-if.h> 14 #include "bus.h" 15 #include "hbm.h" 16 17 #define IPC_PAYLOAD_SIZE 128 18 #define ISHTP_RD_MSG_BUF_SIZE IPC_PAYLOAD_SIZE 19 #define IPC_FULL_MSG_SIZE 132 20 21 /* Number of messages to be held in ISR->BH FIFO */ 22 #define RD_INT_FIFO_SIZE 64 23 24 /* 25 * Number of IPC messages to be held in Tx FIFO, to be sent by ISR - 26 * Tx complete interrupt or RX_COMPLETE handler 27 */ 28 #define IPC_TX_FIFO_SIZE 512 29 30 /* 31 * Number of Maximum ISHTP Clients 32 */ 33 #define ISHTP_CLIENTS_MAX 256 34 35 /* 36 * Number of File descriptors/handles 37 * that can be opened to the driver. 38 * 39 * Limit to 255: 256 Total Clients 40 * minus internal client for ISHTP Bus Messages 41 */ 42 #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1) 43 44 /* Internal Clients Number */ 45 #define ISHTP_HOST_CLIENT_ID_ANY (-1) 46 #define ISHTP_HBM_HOST_CLIENT_ID 0 47 48 #define MAX_DMA_DELAY 20 49 50 /* 300ms to get resume response */ 51 #define WAIT_FOR_RESUME_ACK_MS 300 52 53 /* ISHTP device states */ 54 enum ishtp_dev_state { 55 ISHTP_DEV_INITIALIZING = 0, 56 ISHTP_DEV_INIT_CLIENTS, 57 ISHTP_DEV_ENABLED, 58 ISHTP_DEV_RESETTING, 59 ISHTP_DEV_DISABLED, 60 ISHTP_DEV_POWER_DOWN, 61 ISHTP_DEV_POWER_UP 62 }; 63 64 struct ishtp_cl; 65 66 /** 67 * struct ishtp_fw_client - representation of fw client 68 * 69 * @props - client properties 70 * @client_id - fw client id 71 */ 72 struct ishtp_fw_client { 73 struct ishtp_client_properties props; 74 uint8_t client_id; 75 }; 76 77 /* 78 * Control info for IPC messages ISHTP/IPC sending FIFO - 79 * list with inline data buffer 80 * This structure will be filled with parameters submitted 81 * by the caller glue layer 82 * 'buf' may be pointing to the external buffer or to 'inline_data' 83 * 'offset' will be initialized to 0 by submitting 84 * 85 * 'ipc_send_compl' is intended for use by clients that send fragmented 86 * messages. When a fragment is sent down to IPC msg regs, 87 * it will be called. 88 * If it has more fragments to send, it will do it. With last fragment 89 * it will send appropriate ISHTP "message-complete" flag. 90 * It will remove the outstanding message 91 * (mark outstanding buffer as available). 92 * If counting flow control is in work and there are more flow control 93 * credits, it can put the next client message queued in cl. 94 * structure for IPC processing. 95 * 96 */ 97 struct wr_msg_ctl_info { 98 /* Will be called with 'ipc_send_compl_prm' as parameter */ 99 void (*ipc_send_compl)(void *); 100 101 void *ipc_send_compl_prm; 102 size_t length; 103 struct list_head link; 104 unsigned char inline_data[IPC_FULL_MSG_SIZE]; 105 }; 106 107 /* 108 * The ISHTP layer talks to hardware IPC message using the following 109 * callbacks 110 */ 111 struct ishtp_hw_ops { 112 int (*hw_reset)(struct ishtp_device *dev); 113 int (*ipc_reset)(struct ishtp_device *dev); 114 uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length, 115 int busy); 116 int (*write)(struct ishtp_device *dev, 117 void (*ipc_send_compl)(void *), void *ipc_send_compl_prm, 118 unsigned char *msg, int length); 119 uint32_t (*ishtp_read_hdr)(const struct ishtp_device *dev); 120 int (*ishtp_read)(struct ishtp_device *dev, unsigned char *buffer, 121 unsigned long buffer_length); 122 uint32_t (*get_fw_status)(struct ishtp_device *dev); 123 void (*sync_fw_clock)(struct ishtp_device *dev); 124 bool (*dma_no_cache_snooping)(struct ishtp_device *dev); 125 }; 126 127 /** 128 * struct ishtp_driver_data - Driver-specific data for ISHTP devices 129 * 130 * This structure holds driver-specific data that can be associated with each 131 * ISHTP device instance. It allows for the storage of data that is unique to 132 * a particular driver or hardware variant. 133 * 134 * @fw_generation: The generation name associated with a specific hardware 135 * variant of the Intel Integrated Sensor Hub (ISH). This allows 136 * the driver to load the correct firmware based on the device's 137 * hardware variant. For example, "lnlm" for the Lunar Lake-M 138 * platform. The generation name must not exceed 8 characters 139 * in length. 140 */ 141 struct ishtp_driver_data { 142 char *fw_generation; 143 }; 144 145 struct ish_version { 146 u16 major; 147 u16 minor; 148 u16 hotfix; 149 u16 build; 150 }; 151 152 /** 153 * struct ishtp_device - ISHTP private device struct 154 */ 155 struct ishtp_device { 156 struct device *devc; /* pointer to lowest device */ 157 struct pci_dev *pdev; /* PCI device to get device ids */ 158 struct ishtp_driver_data *driver_data; /* pointer to driver-specific data */ 159 160 /* waitq for waiting for suspend response */ 161 wait_queue_head_t suspend_wait; 162 bool suspend_flag; /* Suspend is active */ 163 164 /* waitq for waiting for resume response */ 165 wait_queue_head_t resume_wait; 166 bool resume_flag; /*Resume is active */ 167 168 /* 169 * lock for the device, for everything that doesn't have 170 * a dedicated spinlock 171 */ 172 spinlock_t device_lock; 173 174 bool recvd_hw_ready; 175 struct hbm_version version; 176 int transfer_path; /* Choice of transfer path: IPC or DMA */ 177 178 /* work structure for scheduling firmware loading tasks */ 179 struct work_struct work_fw_loader; 180 /* waitq for waiting for command response from the firmware loader */ 181 wait_queue_head_t wait_loader_recvd_msg; 182 /* indicating whether a message from the firmware loader has been received */ 183 bool fw_loader_received; 184 /* pointer to a buffer for receiving messages from the firmware loader */ 185 void *fw_loader_rx_buf; 186 /* size of the buffer pointed to by fw_loader_rx_buf */ 187 int fw_loader_rx_size; 188 189 /* ishtp device states */ 190 enum ishtp_dev_state dev_state; 191 enum ishtp_hbm_state hbm_state; 192 193 /* driver read queue */ 194 struct ishtp_cl_rb read_list; 195 spinlock_t read_list_spinlock; 196 197 /* list of ishtp_cl's */ 198 struct list_head cl_list; 199 spinlock_t cl_list_lock; 200 long open_handle_count; 201 202 /* List of bus devices */ 203 struct list_head device_list; 204 spinlock_t device_list_lock; 205 206 /* waiting queues for receive message from FW */ 207 wait_queue_head_t wait_hw_ready; 208 wait_queue_head_t wait_hbm_recvd_msg; 209 210 /* FIFO for input messages for BH processing */ 211 unsigned char rd_msg_fifo[RD_INT_FIFO_SIZE * IPC_PAYLOAD_SIZE]; 212 unsigned int rd_msg_fifo_head, rd_msg_fifo_tail; 213 spinlock_t rd_msg_spinlock; 214 struct work_struct bh_hbm_work; 215 216 /* IPC write queue */ 217 struct list_head wr_processing_list, wr_free_list; 218 /* For both processing list and free list */ 219 spinlock_t wr_processing_spinlock; 220 221 struct ishtp_fw_client *fw_clients; /*Note:memory has to be allocated*/ 222 DECLARE_BITMAP(fw_clients_map, ISHTP_CLIENTS_MAX); 223 DECLARE_BITMAP(host_clients_map, ISHTP_CLIENTS_MAX); 224 uint8_t fw_clients_num; 225 uint8_t fw_client_presentation_num; 226 uint8_t fw_client_index; 227 spinlock_t fw_clients_lock; 228 229 /* TX DMA buffers and slots */ 230 int ishtp_host_dma_enabled; 231 void *ishtp_host_dma_tx_buf; 232 unsigned int ishtp_host_dma_tx_buf_size; 233 uint64_t ishtp_host_dma_tx_buf_phys; 234 int ishtp_dma_num_slots; 235 236 /* map of 4k blocks in Tx dma buf: 0-free, 1-used */ 237 uint8_t *ishtp_dma_tx_map; 238 spinlock_t ishtp_dma_tx_lock; 239 240 /* RX DMA buffers and slots */ 241 void *ishtp_host_dma_rx_buf; 242 unsigned int ishtp_host_dma_rx_buf_size; 243 uint64_t ishtp_host_dma_rx_buf_phys; 244 245 /* Dump to trace buffers if enabled*/ 246 ishtp_print_log print_log; 247 248 /* Base version of Intel's released firmware */ 249 struct ish_version base_ver; 250 /* Vendor-customized project version */ 251 struct ish_version prj_ver; 252 253 /* Debug stats */ 254 unsigned int ipc_rx_cnt; 255 unsigned long long ipc_rx_bytes_cnt; 256 unsigned int ipc_tx_cnt; 257 unsigned long long ipc_tx_bytes_cnt; 258 259 /* Time of the last clock sync */ 260 unsigned long prev_sync; 261 const struct ishtp_hw_ops *ops; 262 size_t mtu; 263 uint32_t ishtp_msg_hdr; 264 char hw[] __aligned(sizeof(void *)); 265 }; 266 267 static inline unsigned long ishtp_secs_to_jiffies(unsigned long sec) 268 { 269 return msecs_to_jiffies(sec * MSEC_PER_SEC); 270 } 271 272 /* 273 * Register Access Function 274 */ 275 static inline int ish_ipc_reset(struct ishtp_device *dev) 276 { 277 return dev->ops->ipc_reset(dev); 278 } 279 280 /* Exported function */ 281 void ishtp_device_init(struct ishtp_device *dev); 282 int ishtp_start(struct ishtp_device *dev); 283 284 #endif /*_ISHTP_DEV_H_*/ 285