1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * H/W layer of ISHTP provider device (ISH) 4 * 5 * Copyright (c) 2014-2016, Intel Corporation. 6 */ 7 8 #include <linux/devm-helpers.h> 9 #include <linux/sched.h> 10 #include <linux/spinlock.h> 11 #include <linux/delay.h> 12 #include <linux/jiffies.h> 13 #include "client.h" 14 #include "hw-ish.h" 15 #include "hbm.h" 16 17 /* For FW reset flow */ 18 static struct work_struct fw_reset_work; 19 static struct ishtp_device *ishtp_dev; 20 21 /** 22 * ish_reg_read() - Read register 23 * @dev: ISHTP device pointer 24 * @offset: Register offset 25 * 26 * Read 32 bit register at a given offset 27 * 28 * Return: Read register value 29 */ 30 static inline uint32_t ish_reg_read(const struct ishtp_device *dev, 31 unsigned long offset) 32 { 33 struct ish_hw *hw = to_ish_hw(dev); 34 35 return readl(hw->mem_addr + offset); 36 } 37 38 /** 39 * ish_reg_write() - Write register 40 * @dev: ISHTP device pointer 41 * @offset: Register offset 42 * @value: Value to write 43 * 44 * Writes 32 bit register at a give offset 45 */ 46 static inline void ish_reg_write(struct ishtp_device *dev, 47 unsigned long offset, 48 uint32_t value) 49 { 50 struct ish_hw *hw = to_ish_hw(dev); 51 52 writel(value, hw->mem_addr + offset); 53 } 54 55 /** 56 * _ish_read_fw_sts_reg() - Read FW status register 57 * @dev: ISHTP device pointer 58 * 59 * Read FW status register 60 * 61 * Return: Read register value 62 */ 63 static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev) 64 { 65 return ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); 66 } 67 68 /** 69 * check_generated_interrupt() - Check if ISH interrupt 70 * @dev: ISHTP device pointer 71 * 72 * Check if an interrupt was generated for ISH 73 * 74 * Return: Read true or false 75 */ 76 static bool check_generated_interrupt(struct ishtp_device *dev) 77 { 78 bool interrupt_generated = true; 79 uint32_t pisr_val = 0; 80 81 if (dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_CHV) { 82 pisr_val = ish_reg_read(dev, IPC_REG_PISR_CHV_AB); 83 interrupt_generated = 84 IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val); 85 } else { 86 pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT); 87 interrupt_generated = !!pisr_val; 88 /* only busy-clear bit is RW, others are RO */ 89 if (pisr_val) 90 ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val); 91 } 92 93 return interrupt_generated; 94 } 95 96 /** 97 * ish_is_input_ready() - Check if FW ready for RX 98 * @dev: ISHTP device pointer 99 * 100 * Check if ISH FW is ready for receiving data 101 * 102 * Return: Read true or false 103 */ 104 static bool ish_is_input_ready(struct ishtp_device *dev) 105 { 106 uint32_t doorbell_val; 107 108 doorbell_val = ish_reg_read(dev, IPC_REG_HOST2ISH_DRBL); 109 return !IPC_IS_BUSY(doorbell_val); 110 } 111 112 /** 113 * set_host_ready() - Indicate host ready 114 * @dev: ISHTP device pointer 115 * 116 * Set host ready indication to FW 117 */ 118 static void set_host_ready(struct ishtp_device *dev) 119 { 120 if (dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_CHV) { 121 if (dev->pdev->revision == REVISION_ID_CHT_A0 || 122 (dev->pdev->revision & REVISION_ID_SI_MASK) == 123 REVISION_ID_CHT_Ax_SI) 124 ish_reg_write(dev, IPC_REG_HOST_COMM, 0x81); 125 else if (dev->pdev->revision == REVISION_ID_CHT_B0 || 126 (dev->pdev->revision & REVISION_ID_SI_MASK) == 127 REVISION_ID_CHT_Bx_SI || 128 (dev->pdev->revision & REVISION_ID_SI_MASK) == 129 REVISION_ID_CHT_Kx_SI || 130 (dev->pdev->revision & REVISION_ID_SI_MASK) == 131 REVISION_ID_CHT_Dx_SI) { 132 uint32_t host_comm_val; 133 134 host_comm_val = ish_reg_read(dev, IPC_REG_HOST_COMM); 135 host_comm_val |= IPC_HOSTCOMM_INT_EN_BIT_CHV_AB | 0x81; 136 ish_reg_write(dev, IPC_REG_HOST_COMM, host_comm_val); 137 } 138 } else { 139 uint32_t host_pimr_val; 140 141 host_pimr_val = ish_reg_read(dev, IPC_REG_PIMR_BXT); 142 host_pimr_val |= IPC_PIMR_INT_EN_BIT_BXT; 143 /* 144 * disable interrupt generated instead of 145 * RX_complete_msg 146 */ 147 host_pimr_val &= ~IPC_HOST2ISH_BUSYCLEAR_MASK_BIT; 148 149 ish_reg_write(dev, IPC_REG_PIMR_BXT, host_pimr_val); 150 } 151 } 152 153 /** 154 * ishtp_fw_is_ready() - Check if FW ready 155 * @dev: ISHTP device pointer 156 * 157 * Check if ISH FW is ready 158 * 159 * Return: Read true or false 160 */ 161 static bool ishtp_fw_is_ready(struct ishtp_device *dev) 162 { 163 uint32_t ish_status = _ish_read_fw_sts_reg(dev); 164 165 return IPC_IS_ISH_ILUP(ish_status) && 166 IPC_IS_ISH_ISHTP_READY(ish_status); 167 } 168 169 /** 170 * ish_set_host_rdy() - Indicate host ready 171 * @dev: ISHTP device pointer 172 * 173 * Set host ready indication to FW 174 */ 175 static void ish_set_host_rdy(struct ishtp_device *dev) 176 { 177 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); 178 179 IPC_SET_HOST_READY(host_status); 180 ish_reg_write(dev, IPC_REG_HOST_COMM, host_status); 181 } 182 183 /** 184 * ish_clr_host_rdy() - Indicate host not ready 185 * @dev: ISHTP device pointer 186 * 187 * Send host not ready indication to FW 188 */ 189 static void ish_clr_host_rdy(struct ishtp_device *dev) 190 { 191 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); 192 193 IPC_CLEAR_HOST_READY(host_status); 194 ish_reg_write(dev, IPC_REG_HOST_COMM, host_status); 195 } 196 197 static bool ish_chk_host_rdy(struct ishtp_device *dev) 198 { 199 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); 200 201 return (host_status & IPC_HOSTCOMM_READY_BIT); 202 } 203 204 /** 205 * ish_set_host_ready() - reconfig ipc host registers 206 * @dev: ishtp device pointer 207 * 208 * Set host to ready state 209 * This API is called in some case: 210 * fw is still on, but ipc is powered down. 211 * such as OOB case. 212 * 213 * Return: 0 for success else error fault code 214 */ 215 void ish_set_host_ready(struct ishtp_device *dev) 216 { 217 if (ish_chk_host_rdy(dev)) 218 return; 219 220 ish_set_host_rdy(dev); 221 set_host_ready(dev); 222 } 223 224 /** 225 * _ishtp_read_hdr() - Read message header 226 * @dev: ISHTP device pointer 227 * 228 * Read header of 32bit length 229 * 230 * Return: Read register value 231 */ 232 static uint32_t _ishtp_read_hdr(const struct ishtp_device *dev) 233 { 234 return ish_reg_read(dev, IPC_REG_ISH2HOST_MSG); 235 } 236 237 /** 238 * _ishtp_read - Read message 239 * @dev: ISHTP device pointer 240 * @buffer: message buffer 241 * @buffer_length: length of message buffer 242 * 243 * Read message from FW 244 * 245 * Return: Always 0 246 */ 247 static int _ishtp_read(struct ishtp_device *dev, unsigned char *buffer, 248 unsigned long buffer_length) 249 { 250 uint32_t i; 251 uint32_t *r_buf = (uint32_t *)buffer; 252 uint32_t msg_offs; 253 254 msg_offs = IPC_REG_ISH2HOST_MSG + sizeof(struct ishtp_msg_hdr); 255 for (i = 0; i < buffer_length; i += sizeof(uint32_t)) 256 *r_buf++ = ish_reg_read(dev, msg_offs + i); 257 258 return 0; 259 } 260 261 /** 262 * write_ipc_from_queue() - try to write ipc msg from Tx queue to device 263 * @dev: ishtp device pointer 264 * 265 * Check if DRBL is cleared. if it is - write the first IPC msg, then call 266 * the callback function (unless it's NULL) 267 * 268 * Return: 0 for success else failure code 269 */ 270 static int write_ipc_from_queue(struct ishtp_device *dev) 271 { 272 struct wr_msg_ctl_info *ipc_link; 273 unsigned long length; 274 unsigned long rem; 275 unsigned long flags; 276 uint32_t doorbell_val; 277 uint32_t *r_buf; 278 uint32_t reg_addr; 279 int i; 280 void (*ipc_send_compl)(void *); 281 void *ipc_send_compl_prm; 282 283 if (dev->dev_state == ISHTP_DEV_DISABLED) 284 return -EINVAL; 285 286 spin_lock_irqsave(&dev->wr_processing_spinlock, flags); 287 if (!ish_is_input_ready(dev)) { 288 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); 289 return -EBUSY; 290 } 291 292 /* 293 * if tx send list is empty - return 0; 294 * may happen, as RX_COMPLETE handler doesn't check list emptiness. 295 */ 296 if (list_empty(&dev->wr_processing_list)) { 297 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); 298 return 0; 299 } 300 301 ipc_link = list_first_entry(&dev->wr_processing_list, 302 struct wr_msg_ctl_info, link); 303 /* first 4 bytes of the data is the doorbell value (IPC header) */ 304 length = ipc_link->length - sizeof(uint32_t); 305 doorbell_val = *(uint32_t *)ipc_link->inline_data; 306 r_buf = (uint32_t *)(ipc_link->inline_data + sizeof(uint32_t)); 307 308 /* If sending MNG_SYNC_FW_CLOCK, update clock again */ 309 if (IPC_HEADER_GET_PROTOCOL(doorbell_val) == IPC_PROTOCOL_MNG && 310 IPC_HEADER_GET_MNG_CMD(doorbell_val) == MNG_SYNC_FW_CLOCK) { 311 uint64_t usec_system, usec_utc; 312 struct ipc_time_update_msg time_update; 313 struct time_sync_format ts_format; 314 315 usec_system = ktime_to_us(ktime_get_boottime()); 316 usec_utc = ktime_to_us(ktime_get_real()); 317 ts_format.ts1_source = HOST_SYSTEM_TIME_USEC; 318 ts_format.ts2_source = HOST_UTC_TIME_USEC; 319 ts_format.reserved = 0; 320 321 time_update.primary_host_time = usec_system; 322 time_update.secondary_host_time = usec_utc; 323 time_update.sync_info = ts_format; 324 325 memcpy(r_buf, &time_update, 326 sizeof(struct ipc_time_update_msg)); 327 } 328 329 for (i = 0, reg_addr = IPC_REG_HOST2ISH_MSG; i < length >> 2; i++, 330 reg_addr += 4) 331 ish_reg_write(dev, reg_addr, r_buf[i]); 332 333 rem = length & 0x3; 334 if (rem > 0) { 335 uint32_t reg = 0; 336 337 memcpy(®, &r_buf[length >> 2], rem); 338 ish_reg_write(dev, reg_addr, reg); 339 } 340 ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, doorbell_val); 341 342 /* Flush writes to msg registers and doorbell */ 343 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); 344 345 /* Update IPC counters */ 346 ++dev->ipc_tx_cnt; 347 dev->ipc_tx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val); 348 349 ipc_send_compl = ipc_link->ipc_send_compl; 350 ipc_send_compl_prm = ipc_link->ipc_send_compl_prm; 351 list_del_init(&ipc_link->link); 352 list_add(&ipc_link->link, &dev->wr_free_list); 353 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); 354 355 /* 356 * callback will be called out of spinlock, 357 * after ipc_link returned to free list 358 */ 359 if (ipc_send_compl) 360 ipc_send_compl(ipc_send_compl_prm); 361 362 return 0; 363 } 364 365 /** 366 * write_ipc_to_queue() - write ipc msg to Tx queue 367 * @dev: ishtp device instance 368 * @ipc_send_compl: Send complete callback 369 * @ipc_send_compl_prm: Parameter to send in complete callback 370 * @msg: Pointer to message 371 * @length: Length of message 372 * 373 * Recived msg with IPC (and upper protocol) header and add it to the device 374 * Tx-to-write list then try to send the first IPC waiting msg 375 * (if DRBL is cleared) 376 * This function returns negative value for failure (means free list 377 * is empty, or msg too long) and 0 for success. 378 * 379 * Return: 0 for success else failure code 380 */ 381 static int write_ipc_to_queue(struct ishtp_device *dev, 382 void (*ipc_send_compl)(void *), void *ipc_send_compl_prm, 383 unsigned char *msg, int length) 384 { 385 struct wr_msg_ctl_info *ipc_link; 386 unsigned long flags; 387 388 if (length > IPC_FULL_MSG_SIZE) 389 return -EMSGSIZE; 390 391 spin_lock_irqsave(&dev->wr_processing_spinlock, flags); 392 if (list_empty(&dev->wr_free_list)) { 393 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); 394 return -ENOMEM; 395 } 396 ipc_link = list_first_entry(&dev->wr_free_list, 397 struct wr_msg_ctl_info, link); 398 list_del_init(&ipc_link->link); 399 400 ipc_link->ipc_send_compl = ipc_send_compl; 401 ipc_link->ipc_send_compl_prm = ipc_send_compl_prm; 402 ipc_link->length = length; 403 memcpy(ipc_link->inline_data, msg, length); 404 405 list_add_tail(&ipc_link->link, &dev->wr_processing_list); 406 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); 407 408 write_ipc_from_queue(dev); 409 410 return 0; 411 } 412 413 /** 414 * ipc_send_mng_msg() - Send management message 415 * @dev: ishtp device instance 416 * @msg_code: Message code 417 * @msg: Pointer to message 418 * @size: Length of message 419 * 420 * Send management message to FW 421 * 422 * Return: 0 for success else failure code 423 */ 424 static int ipc_send_mng_msg(struct ishtp_device *dev, uint32_t msg_code, 425 void *msg, size_t size) 426 { 427 unsigned char ipc_msg[IPC_FULL_MSG_SIZE]; 428 uint32_t drbl_val = IPC_BUILD_MNG_MSG(msg_code, size); 429 430 memcpy(ipc_msg, &drbl_val, sizeof(uint32_t)); 431 memcpy(ipc_msg + sizeof(uint32_t), msg, size); 432 return write_ipc_to_queue(dev, NULL, NULL, ipc_msg, 433 sizeof(uint32_t) + size); 434 } 435 436 #define WAIT_FOR_FW_RDY 0x1 437 #define WAIT_FOR_INPUT_RDY 0x2 438 439 /** 440 * timed_wait_for_timeout() - wait special event with timeout 441 * @dev: ISHTP device pointer 442 * @condition: indicate the condition for waiting 443 * @timeinc: time slice for every wait cycle, in ms 444 * @timeout: time in ms for timeout 445 * 446 * This function will check special event to be ready in a loop, the loop 447 * period is specificd in timeinc. Wait timeout will causes failure. 448 * 449 * Return: 0 for success else failure code 450 */ 451 static int timed_wait_for_timeout(struct ishtp_device *dev, int condition, 452 unsigned int timeinc, unsigned int timeout) 453 { 454 bool complete = false; 455 int ret; 456 457 do { 458 if (condition == WAIT_FOR_FW_RDY) { 459 complete = ishtp_fw_is_ready(dev); 460 } else if (condition == WAIT_FOR_INPUT_RDY) { 461 complete = ish_is_input_ready(dev); 462 } else { 463 ret = -EINVAL; 464 goto out; 465 } 466 467 if (!complete) { 468 unsigned long left_time; 469 470 left_time = msleep_interruptible(timeinc); 471 timeout -= (timeinc - left_time); 472 } 473 } while (!complete && timeout > 0); 474 475 if (complete) 476 ret = 0; 477 else 478 ret = -EBUSY; 479 480 out: 481 return ret; 482 } 483 484 #define TIME_SLICE_FOR_FW_RDY_MS 100 485 #define TIME_SLICE_FOR_INPUT_RDY_MS 100 486 #define TIMEOUT_FOR_FW_RDY_MS 2000 487 #define TIMEOUT_FOR_INPUT_RDY_MS 2000 488 489 /** 490 * ish_fw_reset_handler() - FW reset handler 491 * @dev: ishtp device pointer 492 * 493 * Handle FW reset 494 * 495 * Return: 0 for success else failure code 496 */ 497 static int ish_fw_reset_handler(struct ishtp_device *dev) 498 { 499 uint32_t reset_id; 500 unsigned long flags; 501 502 /* Read reset ID */ 503 reset_id = ish_reg_read(dev, IPC_REG_ISH2HOST_MSG) & 0xFFFF; 504 505 /* Clear IPC output queue */ 506 spin_lock_irqsave(&dev->wr_processing_spinlock, flags); 507 list_splice_init(&dev->wr_processing_list, &dev->wr_free_list); 508 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); 509 510 /* ISHTP notification in IPC_RESET */ 511 ishtp_reset_handler(dev); 512 513 if (!ish_is_input_ready(dev)) 514 timed_wait_for_timeout(dev, WAIT_FOR_INPUT_RDY, 515 TIME_SLICE_FOR_INPUT_RDY_MS, TIMEOUT_FOR_INPUT_RDY_MS); 516 517 /* ISH FW is dead */ 518 if (!ish_is_input_ready(dev)) 519 return -EPIPE; 520 521 /* Send clock sync at once after reset */ 522 ishtp_dev->prev_sync = 0; 523 524 /* 525 * Set HOST2ISH.ILUP. Apparently we need this BEFORE sending 526 * RESET_NOTIFY_ACK - FW will be checking for it 527 */ 528 ish_set_host_rdy(dev); 529 /* Send RESET_NOTIFY_ACK (with reset_id) */ 530 ipc_send_mng_msg(dev, MNG_RESET_NOTIFY_ACK, &reset_id, 531 sizeof(uint32_t)); 532 533 /* Wait for ISH FW'es ILUP and ISHTP_READY */ 534 timed_wait_for_timeout(dev, WAIT_FOR_FW_RDY, 535 TIME_SLICE_FOR_FW_RDY_MS, TIMEOUT_FOR_FW_RDY_MS); 536 if (!ishtp_fw_is_ready(dev)) { 537 /* ISH FW is dead */ 538 uint32_t ish_status; 539 540 ish_status = _ish_read_fw_sts_reg(dev); 541 dev_err(dev->devc, 542 "[ishtp-ish]: completed reset, ISH is dead (FWSTS = %08X)\n", 543 ish_status); 544 return -ENODEV; 545 } 546 return 0; 547 } 548 549 #define TIMEOUT_FOR_HW_RDY_MS 300 550 551 /** 552 * fw_reset_work_fn() - FW reset worker function 553 * @work: Work item 554 * 555 * Call ish_fw_reset_handler to complete FW reset 556 */ 557 static void fw_reset_work_fn(struct work_struct *work) 558 { 559 int rv; 560 561 rv = ish_fw_reset_handler(ishtp_dev); 562 if (!rv) { 563 /* ISH is ILUP & ISHTP-ready. Restart ISHTP */ 564 msleep_interruptible(TIMEOUT_FOR_HW_RDY_MS); 565 ishtp_dev->recvd_hw_ready = 1; 566 wake_up_interruptible(&ishtp_dev->wait_hw_ready); 567 568 /* ISHTP notification in IPC_RESET sequence completion */ 569 if (!work_pending(work)) 570 ishtp_reset_compl_handler(ishtp_dev); 571 } else 572 dev_err(ishtp_dev->devc, "[ishtp-ish]: FW reset failed (%d)\n", 573 rv); 574 } 575 576 /** 577 * _ish_sync_fw_clock() -Sync FW clock with the OS clock 578 * @dev: ishtp device pointer 579 * 580 * Sync FW and OS time 581 */ 582 static void _ish_sync_fw_clock(struct ishtp_device *dev) 583 { 584 struct ipc_time_update_msg time = {}; 585 586 if (dev->prev_sync && time_before(jiffies, dev->prev_sync + 20 * HZ)) 587 return; 588 589 dev->prev_sync = jiffies; 590 /* The fields of time would be updated while sending message */ 591 ipc_send_mng_msg(dev, MNG_SYNC_FW_CLOCK, &time, sizeof(time)); 592 } 593 594 /** 595 * recv_ipc() - Receive and process IPC management messages 596 * @dev: ishtp device instance 597 * @doorbell_val: doorbell value 598 * 599 * This function runs in ISR context. 600 * NOTE: Any other mng command than reset_notify and reset_notify_ack 601 * won't wake BH handler 602 */ 603 static void recv_ipc(struct ishtp_device *dev, uint32_t doorbell_val) 604 { 605 uint32_t mng_cmd; 606 607 mng_cmd = IPC_HEADER_GET_MNG_CMD(doorbell_val); 608 609 switch (mng_cmd) { 610 default: 611 break; 612 613 case MNG_RX_CMPL_INDICATION: 614 if (dev->suspend_flag) { 615 dev->suspend_flag = 0; 616 wake_up_interruptible(&dev->suspend_wait); 617 } 618 if (dev->resume_flag) { 619 dev->resume_flag = 0; 620 wake_up_interruptible(&dev->resume_wait); 621 } 622 623 write_ipc_from_queue(dev); 624 break; 625 626 case MNG_RESET_NOTIFY: 627 if (!ishtp_dev) { 628 ishtp_dev = dev; 629 } 630 schedule_work(&fw_reset_work); 631 break; 632 633 case MNG_RESET_NOTIFY_ACK: 634 dev->recvd_hw_ready = 1; 635 wake_up_interruptible(&dev->wait_hw_ready); 636 break; 637 } 638 } 639 640 /** 641 * ish_irq_handler() - ISH IRQ handler 642 * @irq: irq number 643 * @dev_id: ishtp device pointer 644 * 645 * ISH IRQ handler. If interrupt is generated and is for ISH it will process 646 * the interrupt. 647 */ 648 irqreturn_t ish_irq_handler(int irq, void *dev_id) 649 { 650 struct ishtp_device *dev = dev_id; 651 uint32_t doorbell_val; 652 bool interrupt_generated; 653 654 /* Check that it's interrupt from ISH (may be shared) */ 655 interrupt_generated = check_generated_interrupt(dev); 656 657 if (!interrupt_generated) 658 return IRQ_NONE; 659 660 doorbell_val = ish_reg_read(dev, IPC_REG_ISH2HOST_DRBL); 661 if (!IPC_IS_BUSY(doorbell_val)) 662 return IRQ_HANDLED; 663 664 if (dev->dev_state == ISHTP_DEV_DISABLED) 665 return IRQ_HANDLED; 666 667 /* Sanity check: IPC dgram length in header */ 668 if (IPC_HEADER_GET_LENGTH(doorbell_val) > IPC_PAYLOAD_SIZE) { 669 dev_err(dev->devc, 670 "IPC hdr - bad length: %u; dropped\n", 671 (unsigned int)IPC_HEADER_GET_LENGTH(doorbell_val)); 672 goto eoi; 673 } 674 675 switch (IPC_HEADER_GET_PROTOCOL(doorbell_val)) { 676 default: 677 break; 678 case IPC_PROTOCOL_MNG: 679 recv_ipc(dev, doorbell_val); 680 break; 681 case IPC_PROTOCOL_ISHTP: 682 ishtp_recv(dev); 683 break; 684 } 685 686 eoi: 687 /* Update IPC counters */ 688 ++dev->ipc_rx_cnt; 689 dev->ipc_rx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val); 690 691 ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0); 692 /* Flush write to doorbell */ 693 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); 694 695 return IRQ_HANDLED; 696 } 697 698 /** 699 * ish_disable_dma() - disable dma communication between host and ISHFW 700 * @dev: ishtp device pointer 701 * 702 * Clear the dma enable bit and wait for dma inactive. 703 * 704 * Return: 0 for success else error code. 705 */ 706 int ish_disable_dma(struct ishtp_device *dev) 707 { 708 unsigned int dma_delay; 709 710 /* Clear the dma enable bit */ 711 ish_reg_write(dev, IPC_REG_ISH_RMP2, 0); 712 713 /* wait for dma inactive */ 714 for (dma_delay = 0; dma_delay < MAX_DMA_DELAY && 715 _ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA); 716 dma_delay += 5) 717 mdelay(5); 718 719 if (dma_delay >= MAX_DMA_DELAY) { 720 dev_err(dev->devc, 721 "Wait for DMA inactive timeout\n"); 722 return -EBUSY; 723 } 724 725 return 0; 726 } 727 728 /** 729 * ish_wakeup() - wakeup ishfw from waiting-for-host state 730 * @dev: ishtp device pointer 731 * 732 * Set the dma enable bit and send a void message to FW, 733 * it wil wakeup FW from waiting-for-host state. 734 */ 735 static void ish_wakeup(struct ishtp_device *dev) 736 { 737 /* Set dma enable bit */ 738 ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED); 739 740 /* 741 * Send 0 IPC message so that ISH FW wakes up if it was already 742 * asleep. 743 */ 744 ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT); 745 746 /* Flush writes to doorbell and REMAP2 */ 747 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); 748 } 749 750 /** 751 * _ish_hw_reset() - HW reset 752 * @dev: ishtp device pointer 753 * 754 * Reset ISH HW to recover if any error 755 * 756 * Return: 0 for success else error fault code 757 */ 758 static int _ish_hw_reset(struct ishtp_device *dev) 759 { 760 struct pci_dev *pdev = dev->pdev; 761 int rv; 762 uint16_t csr; 763 764 if (!pdev) 765 return -ENODEV; 766 767 rv = pci_reset_function(pdev); 768 if (!rv) 769 dev->dev_state = ISHTP_DEV_RESETTING; 770 771 if (!pdev->pm_cap) { 772 dev_err(&pdev->dev, "Can't reset - no PM caps\n"); 773 return -EINVAL; 774 } 775 776 /* Disable dma communication between FW and host */ 777 if (ish_disable_dma(dev)) { 778 dev_err(&pdev->dev, 779 "Can't reset - stuck with DMA in-progress\n"); 780 return -EBUSY; 781 } 782 783 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &csr); 784 785 csr &= ~PCI_PM_CTRL_STATE_MASK; 786 csr |= PCI_D3hot; 787 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr); 788 789 mdelay(pdev->d3hot_delay); 790 791 csr &= ~PCI_PM_CTRL_STATE_MASK; 792 csr |= PCI_D0; 793 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr); 794 795 /* Now we can enable ISH DMA operation and wakeup ISHFW */ 796 ish_wakeup(dev); 797 798 return 0; 799 } 800 801 /** 802 * _ish_ipc_reset() - IPC reset 803 * @dev: ishtp device pointer 804 * 805 * Resets host and fw IPC and upper layers 806 * 807 * Return: 0 for success else error fault code 808 */ 809 static int _ish_ipc_reset(struct ishtp_device *dev) 810 { 811 struct ipc_rst_payload_type ipc_mng_msg; 812 int rv = 0; 813 814 ipc_mng_msg.reset_id = 1; 815 ipc_mng_msg.reserved = 0; 816 817 set_host_ready(dev); 818 819 /* Clear the incoming doorbell */ 820 ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0); 821 /* Flush write to doorbell */ 822 ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); 823 824 dev->recvd_hw_ready = 0; 825 826 /* send message */ 827 rv = ipc_send_mng_msg(dev, MNG_RESET_NOTIFY, &ipc_mng_msg, 828 sizeof(struct ipc_rst_payload_type)); 829 if (rv) { 830 dev_err(dev->devc, "Failed to send IPC MNG_RESET_NOTIFY\n"); 831 return rv; 832 } 833 834 wait_event_interruptible_timeout(dev->wait_hw_ready, 835 dev->recvd_hw_ready, 2 * HZ); 836 if (!dev->recvd_hw_ready) { 837 dev_err(dev->devc, "Timed out waiting for HW ready\n"); 838 rv = -ENODEV; 839 } 840 841 return rv; 842 } 843 844 /** 845 * ish_hw_start() -Start ISH HW 846 * @dev: ishtp device pointer 847 * 848 * Set host to ready state and wait for FW reset 849 * 850 * Return: 0 for success else error fault code 851 */ 852 int ish_hw_start(struct ishtp_device *dev) 853 { 854 ish_set_host_rdy(dev); 855 856 set_host_ready(dev); 857 858 /* After that we can enable ISH DMA operation and wakeup ISHFW */ 859 ish_wakeup(dev); 860 861 /* wait for FW-initiated reset flow */ 862 if (!dev->recvd_hw_ready) 863 wait_event_interruptible_timeout(dev->wait_hw_ready, 864 dev->recvd_hw_ready, 865 10 * HZ); 866 867 if (!dev->recvd_hw_ready) { 868 dev_err(dev->devc, 869 "[ishtp-ish]: Timed out waiting for FW-initiated reset\n"); 870 return -ENODEV; 871 } 872 873 return 0; 874 } 875 876 /** 877 * ish_ipc_get_header() -Get doorbell value 878 * @dev: ishtp device pointer 879 * @length: length of message 880 * @busy: busy status 881 * 882 * Get door bell value from message header 883 * 884 * Return: door bell value 885 */ 886 static uint32_t ish_ipc_get_header(struct ishtp_device *dev, int length, 887 int busy) 888 { 889 uint32_t drbl_val; 890 891 drbl_val = IPC_BUILD_HEADER(length, IPC_PROTOCOL_ISHTP, busy); 892 893 return drbl_val; 894 } 895 896 /** 897 * _dma_no_cache_snooping() 898 * 899 * Check on current platform, DMA supports cache snooping or not. 900 * This callback is used to notify uplayer driver if manully cache 901 * flush is needed when do DMA operation. 902 * 903 * Please pay attention to this callback implementation, if declare 904 * having cache snooping on a cache snooping not supported platform 905 * will cause uplayer driver receiving mismatched data; and if 906 * declare no cache snooping on a cache snooping supported platform 907 * will cause cache be flushed twice and performance hit. 908 * 909 * @dev: ishtp device pointer 910 * 911 * Return: false - has cache snooping capability 912 * true - no cache snooping, need manually cache flush 913 */ 914 static bool _dma_no_cache_snooping(struct ishtp_device *dev) 915 { 916 return (dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_EHL_Ax || 917 dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_TGL_LP || 918 dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_TGL_H || 919 dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_ADL_S || 920 dev->pdev->device == PCI_DEVICE_ID_INTEL_ISH_ADL_P); 921 } 922 923 static const struct ishtp_hw_ops ish_hw_ops = { 924 .hw_reset = _ish_hw_reset, 925 .ipc_reset = _ish_ipc_reset, 926 .ipc_get_header = ish_ipc_get_header, 927 .ishtp_read = _ishtp_read, 928 .write = write_ipc_to_queue, 929 .get_fw_status = _ish_read_fw_sts_reg, 930 .sync_fw_clock = _ish_sync_fw_clock, 931 .ishtp_read_hdr = _ishtp_read_hdr, 932 .dma_no_cache_snooping = _dma_no_cache_snooping 933 }; 934 935 /** 936 * ish_dev_init() -Initialize ISH devoce 937 * @pdev: PCI device 938 * 939 * Allocate ISHTP device and initialize IPC processing 940 * 941 * Return: ISHTP device instance on success else NULL 942 */ 943 struct ishtp_device *ish_dev_init(struct pci_dev *pdev) 944 { 945 struct ishtp_device *dev; 946 int i; 947 int ret; 948 949 dev = devm_kzalloc(&pdev->dev, 950 sizeof(struct ishtp_device) + sizeof(struct ish_hw), 951 GFP_KERNEL); 952 if (!dev) 953 return NULL; 954 955 dev->devc = &pdev->dev; 956 ishtp_device_init(dev); 957 958 init_waitqueue_head(&dev->wait_hw_ready); 959 960 spin_lock_init(&dev->wr_processing_spinlock); 961 962 /* Init IPC processing and free lists */ 963 INIT_LIST_HEAD(&dev->wr_processing_list); 964 INIT_LIST_HEAD(&dev->wr_free_list); 965 for (i = 0; i < IPC_TX_FIFO_SIZE; i++) { 966 struct wr_msg_ctl_info *tx_buf; 967 968 tx_buf = devm_kzalloc(&pdev->dev, 969 sizeof(struct wr_msg_ctl_info), 970 GFP_KERNEL); 971 if (!tx_buf) { 972 /* 973 * IPC buffers may be limited or not available 974 * at all - although this shouldn't happen 975 */ 976 dev_err(dev->devc, 977 "[ishtp-ish]: failure in Tx FIFO allocations (%d)\n", 978 i); 979 break; 980 } 981 list_add_tail(&tx_buf->link, &dev->wr_free_list); 982 } 983 984 ret = devm_work_autocancel(&pdev->dev, &fw_reset_work, fw_reset_work_fn); 985 if (ret) { 986 dev_err(dev->devc, "Failed to initialise FW reset work\n"); 987 return NULL; 988 } 989 990 dev->ops = &ish_hw_ops; 991 dev->mtu = IPC_PAYLOAD_SIZE - sizeof(struct ishtp_msg_hdr); 992 return dev; 993 } 994 995 /** 996 * ish_device_disable() - Disable ISH device 997 * @dev: ISHTP device pointer 998 * 999 * Disable ISH by clearing host ready to inform firmware. 1000 */ 1001 void ish_device_disable(struct ishtp_device *dev) 1002 { 1003 struct pci_dev *pdev = dev->pdev; 1004 1005 if (!pdev) 1006 return; 1007 1008 /* Disable dma communication between FW and host */ 1009 if (ish_disable_dma(dev)) { 1010 dev_err(&pdev->dev, 1011 "Can't reset - stuck with DMA in-progress\n"); 1012 return; 1013 } 1014 1015 /* Put ISH to D3hot state for power saving */ 1016 pci_set_power_state(pdev, PCI_D3hot); 1017 1018 dev->dev_state = ISHTP_DEV_DISABLED; 1019 ish_clr_host_rdy(dev); 1020 } 1021