1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * H/W layer of ISHTP provider device (ISH) 4 * 5 * Copyright (c) 2014-2016, Intel Corporation. 6 */ 7 8 #ifndef _ISHTP_HW_ISH_H_ 9 #define _ISHTP_HW_ISH_H_ 10 11 #include <linux/pci.h> 12 #include <linux/interrupt.h> 13 #include "hw-ish-regs.h" 14 #include "ishtp-dev.h" 15 16 #define PCI_DEVICE_ID_INTEL_ISH_CHV 0x22D8 17 #define PCI_DEVICE_ID_INTEL_ISH_BXT_Ax 0x0AA2 18 #define PCI_DEVICE_ID_INTEL_ISH_BXT_Bx 0x1AA2 19 #define PCI_DEVICE_ID_INTEL_ISH_APL_Ax 0x5AA2 20 #define PCI_DEVICE_ID_INTEL_ISH_SPT_Ax 0x9D35 21 #define PCI_DEVICE_ID_INTEL_ISH_CNL_Ax 0x9DFC 22 #define PCI_DEVICE_ID_INTEL_ISH_GLK_Ax 0x31A2 23 #define PCI_DEVICE_ID_INTEL_ISH_CNL_H 0xA37C 24 #define PCI_DEVICE_ID_INTEL_ISH_ICL_MOBILE 0x34FC 25 #define PCI_DEVICE_ID_INTEL_ISH_SPT_H 0xA135 26 #define PCI_DEVICE_ID_INTEL_ISH_CML_LP 0x02FC 27 #define PCI_DEVICE_ID_INTEL_ISH_CMP_H 0x06FC 28 #define PCI_DEVICE_ID_INTEL_ISH_EHL_Ax 0x4BB3 29 #define PCI_DEVICE_ID_INTEL_ISH_TGL_LP 0xA0FC 30 #define PCI_DEVICE_ID_INTEL_ISH_TGL_H 0x43FC 31 #define PCI_DEVICE_ID_INTEL_ISH_ADL_S 0x7AF8 32 #define PCI_DEVICE_ID_INTEL_ISH_ADL_P 0x51FC 33 #define PCI_DEVICE_ID_INTEL_ISH_ADL_N 0x54FC 34 #define PCI_DEVICE_ID_INTEL_ISH_RPL_S 0x7A78 35 #define PCI_DEVICE_ID_INTEL_ISH_MTL_P 0x7E45 36 #define PCI_DEVICE_ID_INTEL_ISH_ARL_H 0x7745 37 #define PCI_DEVICE_ID_INTEL_ISH_ARL_S 0x7F78 38 39 #define REVISION_ID_CHT_A0 0x6 40 #define REVISION_ID_CHT_Ax_SI 0x0 41 #define REVISION_ID_CHT_Bx_SI 0x10 42 #define REVISION_ID_CHT_Kx_SI 0x20 43 #define REVISION_ID_CHT_Dx_SI 0x30 44 #define REVISION_ID_CHT_B0 0xB0 45 #define REVISION_ID_SI_MASK 0x70 46 47 struct ipc_rst_payload_type { 48 uint16_t reset_id; 49 uint16_t reserved; 50 }; 51 52 struct time_sync_format { 53 uint8_t ts1_source; 54 uint8_t ts2_source; 55 uint16_t reserved; 56 } __packed; 57 58 struct ipc_time_update_msg { 59 uint64_t primary_host_time; 60 struct time_sync_format sync_info; 61 uint64_t secondary_host_time; 62 } __packed; 63 64 enum { 65 HOST_UTC_TIME_USEC = 0, 66 HOST_SYSTEM_TIME_USEC = 1 67 }; 68 69 struct ish_hw { 70 void __iomem *mem_addr; 71 }; 72 73 /* 74 * ISH FW status type 75 */ 76 enum { 77 FWSTS_AFTER_RESET = 0, 78 FWSTS_WAIT_FOR_HOST = 4, 79 FWSTS_START_KERNEL_DMA = 5, 80 FWSTS_FW_IS_RUNNING = 7, 81 FWSTS_SENSOR_APP_LOADED = 8, 82 FWSTS_SENSOR_APP_RUNNING = 15 83 }; 84 85 #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw) 86 87 irqreturn_t ish_irq_handler(int irq, void *dev_id); 88 struct ishtp_device *ish_dev_init(struct pci_dev *pdev); 89 int ish_hw_start(struct ishtp_device *dev); 90 void ish_device_disable(struct ishtp_device *dev); 91 int ish_disable_dma(struct ishtp_device *dev); 92 void ish_set_host_ready(struct ishtp_device *dev); 93 94 #endif /* _ISHTP_HW_ISH_H_ */ 95