1*6947f312SBasavaraj Natikar /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*6947f312SBasavaraj Natikar /* 3*6947f312SBasavaraj Natikar * AMD MP2 common macros and structures 4*6947f312SBasavaraj Natikar * 5*6947f312SBasavaraj Natikar * Copyright (c) 2022, Advanced Micro Devices, Inc. 6*6947f312SBasavaraj Natikar * All Rights Reserved. 7*6947f312SBasavaraj Natikar * 8*6947f312SBasavaraj Natikar * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com> 9*6947f312SBasavaraj Natikar */ 10*6947f312SBasavaraj Natikar #ifndef AMD_SFH_COMMON_H 11*6947f312SBasavaraj Natikar #define AMD_SFH_COMMON_H 12*6947f312SBasavaraj Natikar 13*6947f312SBasavaraj Natikar #include <linux/pci.h> 14*6947f312SBasavaraj Natikar #include "amd_sfh_hid.h" 15*6947f312SBasavaraj Natikar 16*6947f312SBasavaraj Natikar #define PCI_DEVICE_ID_AMD_MP2 0x15E4 17*6947f312SBasavaraj Natikar 18*6947f312SBasavaraj Natikar #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4)) 19*6947f312SBasavaraj Natikar #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4)) 20*6947f312SBasavaraj Natikar 21*6947f312SBasavaraj Natikar #define SENSOR_ENABLED 4 22*6947f312SBasavaraj Natikar #define SENSOR_DISABLED 5 23*6947f312SBasavaraj Natikar 24*6947f312SBasavaraj Natikar #define AMD_SFH_IDLE_LOOP 200 25*6947f312SBasavaraj Natikar 26*6947f312SBasavaraj Natikar enum cmd_id { 27*6947f312SBasavaraj Natikar NO_OP, 28*6947f312SBasavaraj Natikar ENABLE_SENSOR, 29*6947f312SBasavaraj Natikar DISABLE_SENSOR, 30*6947f312SBasavaraj Natikar STOP_ALL_SENSORS = 8, 31*6947f312SBasavaraj Natikar }; 32*6947f312SBasavaraj Natikar 33*6947f312SBasavaraj Natikar struct amd_mp2_sensor_info { 34*6947f312SBasavaraj Natikar u8 sensor_idx; 35*6947f312SBasavaraj Natikar u32 period; 36*6947f312SBasavaraj Natikar dma_addr_t dma_address; 37*6947f312SBasavaraj Natikar }; 38*6947f312SBasavaraj Natikar 39*6947f312SBasavaraj Natikar struct amd_mp2_dev { 40*6947f312SBasavaraj Natikar struct pci_dev *pdev; 41*6947f312SBasavaraj Natikar struct amdtp_cl_data *cl_data; 42*6947f312SBasavaraj Natikar void __iomem *mmio; 43*6947f312SBasavaraj Natikar const struct amd_mp2_ops *mp2_ops; 44*6947f312SBasavaraj Natikar struct amd_input_data in_data; 45*6947f312SBasavaraj Natikar /* mp2 active control status */ 46*6947f312SBasavaraj Natikar u32 mp2_acs; 47*6947f312SBasavaraj Natikar }; 48*6947f312SBasavaraj Natikar 49*6947f312SBasavaraj Natikar struct amd_mp2_ops { 50*6947f312SBasavaraj Natikar void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info); 51*6947f312SBasavaraj Natikar void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx); 52*6947f312SBasavaraj Natikar void (*stop_all)(struct amd_mp2_dev *privdata); 53*6947f312SBasavaraj Natikar int (*response)(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts); 54*6947f312SBasavaraj Natikar void (*clear_intr)(struct amd_mp2_dev *privdata); 55*6947f312SBasavaraj Natikar int (*init_intr)(struct amd_mp2_dev *privdata); 56*6947f312SBasavaraj Natikar int (*discovery_status)(struct amd_mp2_dev *privdata); 57*6947f312SBasavaraj Natikar }; 58*6947f312SBasavaraj Natikar 59*6947f312SBasavaraj Natikar #endif 60