xref: /linux/drivers/hid/amd-sfh-hid/amd_sfh_common.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
16947f312SBasavaraj Natikar /* SPDX-License-Identifier: GPL-2.0-or-later */
26947f312SBasavaraj Natikar /*
36947f312SBasavaraj Natikar  * AMD MP2 common macros and structures
46947f312SBasavaraj Natikar  *
56947f312SBasavaraj Natikar  * Copyright (c) 2022, Advanced Micro Devices, Inc.
66947f312SBasavaraj Natikar  * All Rights Reserved.
76947f312SBasavaraj Natikar  *
86947f312SBasavaraj Natikar  * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
96947f312SBasavaraj Natikar  */
106947f312SBasavaraj Natikar #ifndef AMD_SFH_COMMON_H
116947f312SBasavaraj Natikar #define AMD_SFH_COMMON_H
126947f312SBasavaraj Natikar 
136947f312SBasavaraj Natikar #include <linux/pci.h>
146947f312SBasavaraj Natikar #include "amd_sfh_hid.h"
156947f312SBasavaraj Natikar 
166947f312SBasavaraj Natikar #define PCI_DEVICE_ID_AMD_MP2		0x15E4
1793ce5e02SBasavaraj Natikar #define PCI_DEVICE_ID_AMD_MP2_1_1	0x164A
186947f312SBasavaraj Natikar 
196947f312SBasavaraj Natikar #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4))
206947f312SBasavaraj Natikar #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4))
216947f312SBasavaraj Natikar 
22*6296562fSBasavaraj Natikar #define AMD_C2P_MSG_V1(regno) (0x10900 + ((regno) * 4))
23*6296562fSBasavaraj Natikar #define AMD_P2C_MSG_V1(regno) (0x10500 + ((regno) * 4))
24*6296562fSBasavaraj Natikar 
256947f312SBasavaraj Natikar #define SENSOR_ENABLED			4
266947f312SBasavaraj Natikar #define SENSOR_DISABLED			5
276947f312SBasavaraj Natikar 
286947f312SBasavaraj Natikar #define AMD_SFH_IDLE_LOOP		200
296947f312SBasavaraj Natikar 
306947f312SBasavaraj Natikar enum cmd_id {
316947f312SBasavaraj Natikar 	NO_OP,
326947f312SBasavaraj Natikar 	ENABLE_SENSOR,
336947f312SBasavaraj Natikar 	DISABLE_SENSOR,
346947f312SBasavaraj Natikar 	STOP_ALL_SENSORS = 8,
356947f312SBasavaraj Natikar };
366947f312SBasavaraj Natikar 
376947f312SBasavaraj Natikar struct amd_mp2_sensor_info {
386947f312SBasavaraj Natikar 	u8 sensor_idx;
396947f312SBasavaraj Natikar 	u32 period;
406947f312SBasavaraj Natikar 	dma_addr_t dma_address;
416947f312SBasavaraj Natikar };
426947f312SBasavaraj Natikar 
43b5b0774dSBasavaraj Natikar struct sfh_dev_status {
44b5b0774dSBasavaraj Natikar 	bool is_hpd_present;
45584f35a3SBasavaraj Natikar 	bool is_als_present;
46b5b0774dSBasavaraj Natikar };
47b5b0774dSBasavaraj Natikar 
486947f312SBasavaraj Natikar struct amd_mp2_dev {
496947f312SBasavaraj Natikar 	struct pci_dev *pdev;
506947f312SBasavaraj Natikar 	struct amdtp_cl_data *cl_data;
516947f312SBasavaraj Natikar 	void __iomem *mmio;
5293ce5e02SBasavaraj Natikar 	void __iomem *vsbase;
5393ce5e02SBasavaraj Natikar 	const struct amd_sfh1_1_ops *sfh1_1_ops;
54786aa1b9SBasavaraj Natikar 	struct amd_mp2_ops *mp2_ops;
556947f312SBasavaraj Natikar 	struct amd_input_data in_data;
566947f312SBasavaraj Natikar 	/* mp2 active control status */
576947f312SBasavaraj Natikar 	u32 mp2_acs;
58b5b0774dSBasavaraj Natikar 	struct sfh_dev_status dev_en;
592105e8e0SBasavaraj Natikar 	struct work_struct work;
602105e8e0SBasavaraj Natikar 	u8 init_done;
61*6296562fSBasavaraj Natikar 	u8 rver;
626947f312SBasavaraj Natikar };
636947f312SBasavaraj Natikar 
646947f312SBasavaraj Natikar struct amd_mp2_ops {
656947f312SBasavaraj Natikar 	void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
666947f312SBasavaraj Natikar 	void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx);
676947f312SBasavaraj Natikar 	void (*stop_all)(struct amd_mp2_dev *privdata);
686947f312SBasavaraj Natikar 	int (*response)(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts);
696947f312SBasavaraj Natikar 	void (*clear_intr)(struct amd_mp2_dev *privdata);
706947f312SBasavaraj Natikar 	int (*init_intr)(struct amd_mp2_dev *privdata);
716947f312SBasavaraj Natikar 	int (*discovery_status)(struct amd_mp2_dev *privdata);
729acadc72SBasavaraj Natikar 	void (*suspend)(struct amd_mp2_dev *mp2);
739acadc72SBasavaraj Natikar 	void (*resume)(struct amd_mp2_dev *mp2);
74722658f8SBasavaraj Natikar 	void (*remove)(void *privdata);
75786aa1b9SBasavaraj Natikar 	int (*get_rep_desc)(int sensor_idx, u8 rep_desc[]);
76786aa1b9SBasavaraj Natikar 	u32 (*get_desc_sz)(int sensor_idx, int descriptor_name);
77786aa1b9SBasavaraj Natikar 	u8 (*get_feat_rep)(int sensor_idx, int report_id, u8 *feature_report);
78786aa1b9SBasavaraj Natikar 	u8 (*get_in_rep)(u8 current_index, int sensor_idx, int report_id,
79786aa1b9SBasavaraj Natikar 			 struct amd_input_data *in_data);
806947f312SBasavaraj Natikar };
816947f312SBasavaraj Natikar 
82e7f535eaSBasavaraj Natikar void amd_sfh_work(struct work_struct *work);
83e7f535eaSBasavaraj Natikar void amd_sfh_work_buffer(struct work_struct *work);
84014730c4SBasavaraj Natikar void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata);
85014730c4SBasavaraj Natikar int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata);
86014730c4SBasavaraj Natikar void amd_sfh_clear_intr(struct amd_mp2_dev *privdata);
87014730c4SBasavaraj Natikar int amd_sfh_irq_init(struct amd_mp2_dev *privdata);
88*6296562fSBasavaraj Natikar 
amd_get_c2p_val(struct amd_mp2_dev * mp2,u32 idx)89*6296562fSBasavaraj Natikar static inline u64 amd_get_c2p_val(struct amd_mp2_dev *mp2, u32 idx)
90*6296562fSBasavaraj Natikar {
91*6296562fSBasavaraj Natikar 	return mp2->rver == 1 ? AMD_C2P_MSG_V1(idx) :  AMD_C2P_MSG(idx);
92*6296562fSBasavaraj Natikar }
93*6296562fSBasavaraj Natikar 
amd_get_p2c_val(struct amd_mp2_dev * mp2,u32 idx)94*6296562fSBasavaraj Natikar static inline u64 amd_get_p2c_val(struct amd_mp2_dev *mp2, u32 idx)
95*6296562fSBasavaraj Natikar {
96*6296562fSBasavaraj Natikar 	return mp2->rver == 1 ? AMD_P2C_MSG_V1(idx) :  AMD_P2C_MSG(idx);
97*6296562fSBasavaraj Natikar }
986947f312SBasavaraj Natikar #endif
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