1 // SPDX-License-Identifier: GPL-2.0 2 3 //! GSP Sequencer implementation for Pre-hopper GSP boot sequence. 4 5 use core::array; 6 7 use kernel::{ 8 device, 9 io::{ 10 poll::read_poll_timeout, 11 Io, // 12 }, 13 prelude::*, 14 sync::aref::ARef, 15 time::{ 16 delay::fsleep, 17 Delta, // 18 }, 19 transmute::FromBytes, // 20 }; 21 22 use crate::{ 23 driver::Bar0, 24 falcon::{ 25 gsp::Gsp, 26 sec2::Sec2, 27 Falcon, // 28 }, 29 gsp::{ 30 cmdq::{ 31 Cmdq, 32 MessageFromGsp, // 33 }, 34 fw, 35 }, 36 num::FromSafeCast, 37 sbuffer::SBufferIter, 38 }; 39 40 /// GSP Sequencer information containing the command sequence and data. 41 struct GspSequence { 42 /// Current command index for error reporting. 43 cmd_index: u32, 44 /// Command data buffer containing the sequence of commands. 45 cmd_data: KVec<u8>, 46 } 47 48 impl MessageFromGsp for GspSequence { 49 const FUNCTION: fw::MsgFunction = fw::MsgFunction::GspRunCpuSequencer; 50 type InitError = Error; 51 type Message = fw::RunCpuSequencer; 52 53 fn read( 54 msg: &Self::Message, 55 sbuffer: &mut SBufferIter<array::IntoIter<&[u8], 2>>, 56 ) -> Result<Self, Self::InitError> { 57 let cmd_data = sbuffer.flush_into_kvec(GFP_KERNEL)?; 58 Ok(GspSequence { 59 cmd_index: msg.cmd_index(), 60 cmd_data, 61 }) 62 } 63 } 64 65 const CMD_SIZE: usize = size_of::<fw::SequencerBufferCmd>(); 66 67 /// GSP Sequencer Command types with payload data. 68 /// Commands have an opcode and an opcode-dependent struct. 69 #[allow(clippy::enum_variant_names)] 70 #[derive(Debug)] 71 pub(crate) enum GspSeqCmd { 72 RegWrite(fw::RegWritePayload), 73 RegModify(fw::RegModifyPayload), 74 RegPoll(fw::RegPollPayload), 75 DelayUs(fw::DelayUsPayload), 76 RegStore(fw::RegStorePayload), 77 CoreReset, 78 CoreStart, 79 CoreWaitForHalt, 80 CoreResume, 81 } 82 83 impl GspSeqCmd { 84 /// Creates a new `GspSeqCmd` from raw data returning the command and its size in bytes. 85 pub(crate) fn new(data: &[u8], dev: &device::Device) -> Result<(Self, usize)> { 86 let fw_cmd = fw::SequencerBufferCmd::from_bytes(data).ok_or(EINVAL)?; 87 let opcode_size = core::mem::size_of::<u32>(); 88 89 let (cmd, size) = match fw_cmd.opcode()? { 90 fw::SeqBufOpcode::RegWrite => { 91 let payload = fw_cmd.reg_write_payload()?; 92 let size = opcode_size + size_of_val(&payload); 93 (GspSeqCmd::RegWrite(payload), size) 94 } 95 fw::SeqBufOpcode::RegModify => { 96 let payload = fw_cmd.reg_modify_payload()?; 97 let size = opcode_size + size_of_val(&payload); 98 (GspSeqCmd::RegModify(payload), size) 99 } 100 fw::SeqBufOpcode::RegPoll => { 101 let payload = fw_cmd.reg_poll_payload()?; 102 let size = opcode_size + size_of_val(&payload); 103 (GspSeqCmd::RegPoll(payload), size) 104 } 105 fw::SeqBufOpcode::DelayUs => { 106 let payload = fw_cmd.delay_us_payload()?; 107 let size = opcode_size + size_of_val(&payload); 108 (GspSeqCmd::DelayUs(payload), size) 109 } 110 fw::SeqBufOpcode::RegStore => { 111 let payload = fw_cmd.reg_store_payload()?; 112 let size = opcode_size + size_of_val(&payload); 113 (GspSeqCmd::RegStore(payload), size) 114 } 115 fw::SeqBufOpcode::CoreReset => (GspSeqCmd::CoreReset, opcode_size), 116 fw::SeqBufOpcode::CoreStart => (GspSeqCmd::CoreStart, opcode_size), 117 fw::SeqBufOpcode::CoreWaitForHalt => (GspSeqCmd::CoreWaitForHalt, opcode_size), 118 fw::SeqBufOpcode::CoreResume => (GspSeqCmd::CoreResume, opcode_size), 119 }; 120 121 if data.len() < size { 122 dev_err!(dev, "Data is not enough for command\n"); 123 return Err(EINVAL); 124 } 125 126 Ok((cmd, size)) 127 } 128 } 129 130 /// GSP Sequencer for executing firmware commands during boot. 131 pub(crate) struct GspSequencer<'a> { 132 /// Sequencer information with command data. 133 seq_info: GspSequence, 134 /// `Bar0` for register access. 135 bar: &'a Bar0, 136 /// SEC2 falcon for core operations. 137 sec2_falcon: &'a Falcon<Sec2>, 138 /// GSP falcon for core operations. 139 gsp_falcon: &'a Falcon<Gsp>, 140 /// LibOS DMA handle address. 141 libos_dma_handle: u64, 142 /// Bootloader application version. 143 bootloader_app_version: u32, 144 /// Device for logging. 145 dev: ARef<device::Device>, 146 } 147 148 impl fw::RegWritePayload { 149 fn run(&self, sequencer: &GspSequencer<'_>) -> Result { 150 let addr = usize::from_safe_cast(self.addr()); 151 152 sequencer.bar.try_write32(self.val(), addr) 153 } 154 } 155 156 impl fw::RegModifyPayload { 157 fn run(&self, sequencer: &GspSequencer<'_>) -> Result { 158 let addr = usize::from_safe_cast(self.addr()); 159 160 sequencer.bar.try_read32(addr).and_then(|val| { 161 sequencer 162 .bar 163 .try_write32((val & !self.mask()) | self.val(), addr) 164 }) 165 } 166 } 167 168 impl fw::RegPollPayload { 169 fn run(&self, sequencer: &GspSequencer<'_>) -> Result { 170 let addr = usize::from_safe_cast(self.addr()); 171 172 // Default timeout to 4 seconds. 173 let timeout_us = if self.timeout() == 0 { 174 4_000_000 175 } else { 176 i64::from(self.timeout()) 177 }; 178 179 // First read. 180 sequencer.bar.try_read32(addr)?; 181 182 // Poll the requested register with requested timeout. 183 read_poll_timeout( 184 || sequencer.bar.try_read32(addr), 185 |current| (current & self.mask()) == self.val(), 186 Delta::ZERO, 187 Delta::from_micros(timeout_us), 188 ) 189 .map(|_| ()) 190 } 191 } 192 193 impl fw::DelayUsPayload { 194 fn run(&self, _sequencer: &GspSequencer<'_>) -> Result { 195 fsleep(Delta::from_micros(i64::from(self.val()))); 196 Ok(()) 197 } 198 } 199 200 impl fw::RegStorePayload { 201 fn run(&self, sequencer: &GspSequencer<'_>) -> Result { 202 let addr = usize::from_safe_cast(self.addr()); 203 204 sequencer.bar.try_read32(addr).map(|_| ()) 205 } 206 } 207 208 impl GspSeqCmd { 209 fn run(&self, seq: &GspSequencer<'_>) -> Result { 210 match self { 211 GspSeqCmd::RegWrite(cmd) => cmd.run(seq), 212 GspSeqCmd::RegModify(cmd) => cmd.run(seq), 213 GspSeqCmd::RegPoll(cmd) => cmd.run(seq), 214 GspSeqCmd::DelayUs(cmd) => cmd.run(seq), 215 GspSeqCmd::RegStore(cmd) => cmd.run(seq), 216 GspSeqCmd::CoreReset => { 217 seq.gsp_falcon.reset(seq.bar)?; 218 seq.gsp_falcon.dma_reset(seq.bar); 219 Ok(()) 220 } 221 GspSeqCmd::CoreStart => { 222 seq.gsp_falcon.start(seq.bar)?; 223 Ok(()) 224 } 225 GspSeqCmd::CoreWaitForHalt => { 226 seq.gsp_falcon.wait_till_halted(seq.bar)?; 227 Ok(()) 228 } 229 GspSeqCmd::CoreResume => { 230 // At this point, 'SEC2-RTOS' has been loaded into SEC2 by the sequencer 231 // but neither SEC2-RTOS nor GSP-RM is running yet. This part of the 232 // sequencer will start both. 233 234 // Reset the GSP to prepare it for resuming. 235 seq.gsp_falcon.reset(seq.bar)?; 236 237 // Write the libOS DMA handle to GSP mailboxes. 238 seq.gsp_falcon.write_mailboxes( 239 seq.bar, 240 Some(seq.libos_dma_handle as u32), 241 Some((seq.libos_dma_handle >> 32) as u32), 242 ); 243 244 // Start the SEC2 falcon which will trigger GSP-RM to resume on the GSP. 245 seq.sec2_falcon.start(seq.bar)?; 246 247 // Poll until GSP-RM reload/resume has completed (up to 2 seconds). 248 seq.gsp_falcon 249 .check_reload_completed(seq.bar, Delta::from_secs(2))?; 250 251 // Verify SEC2 completed successfully by checking its mailbox for errors. 252 let mbox0 = seq.sec2_falcon.read_mailbox0(seq.bar); 253 if mbox0 != 0 { 254 dev_err!(seq.dev, "Sequencer: sec2 errors: {:?}\n", mbox0); 255 return Err(EIO); 256 } 257 258 // Configure GSP with the bootloader version. 259 seq.gsp_falcon 260 .write_os_version(seq.bar, seq.bootloader_app_version); 261 262 // Verify the GSP's RISC-V core is active indicating successful GSP boot. 263 if !seq.gsp_falcon.is_riscv_active(seq.bar) { 264 dev_err!(seq.dev, "Sequencer: RISC-V core is not active\n"); 265 return Err(EIO); 266 } 267 Ok(()) 268 } 269 } 270 } 271 } 272 273 /// Iterator over GSP sequencer commands. 274 pub(crate) struct GspSeqIter<'a> { 275 /// Command data buffer. 276 cmd_data: &'a [u8], 277 /// Current position in the buffer. 278 current_offset: usize, 279 /// Total number of commands to process. 280 total_cmds: u32, 281 /// Number of commands processed so far. 282 cmds_processed: u32, 283 /// Device for logging. 284 dev: ARef<device::Device>, 285 } 286 287 impl<'a> Iterator for GspSeqIter<'a> { 288 type Item = Result<GspSeqCmd>; 289 290 fn next(&mut self) -> Option<Self::Item> { 291 // Stop if we've processed all commands or reached the end of data. 292 if self.cmds_processed >= self.total_cmds || self.current_offset >= self.cmd_data.len() { 293 return None; 294 } 295 296 // Check if we have enough data for opcode. 297 if self.current_offset + core::mem::size_of::<u32>() > self.cmd_data.len() { 298 return Some(Err(EIO)); 299 } 300 301 let offset = self.current_offset; 302 303 // Handle command creation based on available data, 304 // zero-pad if necessary (since last command may not be full size). 305 let mut buffer = [0u8; CMD_SIZE]; 306 let copy_len = if offset + CMD_SIZE <= self.cmd_data.len() { 307 CMD_SIZE 308 } else { 309 self.cmd_data.len() - offset 310 }; 311 buffer[..copy_len].copy_from_slice(&self.cmd_data[offset..offset + copy_len]); 312 let cmd_result = GspSeqCmd::new(&buffer, &self.dev); 313 314 cmd_result.map_or_else( 315 |_err| { 316 dev_err!(self.dev, "Error parsing command at offset {}\n", offset); 317 None 318 }, 319 |(cmd, size)| { 320 self.current_offset += size; 321 self.cmds_processed += 1; 322 Some(Ok(cmd)) 323 }, 324 ) 325 } 326 } 327 328 impl<'a> GspSequencer<'a> { 329 fn iter(&self) -> GspSeqIter<'_> { 330 let cmd_data = &self.seq_info.cmd_data[..]; 331 332 GspSeqIter { 333 cmd_data, 334 current_offset: 0, 335 total_cmds: self.seq_info.cmd_index, 336 cmds_processed: 0, 337 dev: self.dev.clone(), 338 } 339 } 340 } 341 342 /// Parameters for running the GSP sequencer. 343 pub(crate) struct GspSequencerParams<'a> { 344 /// Bootloader application version. 345 pub(crate) bootloader_app_version: u32, 346 /// LibOS DMA handle address. 347 pub(crate) libos_dma_handle: u64, 348 /// GSP falcon for core operations. 349 pub(crate) gsp_falcon: &'a Falcon<Gsp>, 350 /// SEC2 falcon for core operations. 351 pub(crate) sec2_falcon: &'a Falcon<Sec2>, 352 /// Device for logging. 353 pub(crate) dev: ARef<device::Device>, 354 /// BAR0 for register access. 355 pub(crate) bar: &'a Bar0, 356 } 357 358 impl<'a> GspSequencer<'a> { 359 pub(crate) fn run(cmdq: &Cmdq, params: GspSequencerParams<'a>) -> Result { 360 let seq_info = loop { 361 match cmdq.receive_msg::<GspSequence>(Cmdq::RECEIVE_TIMEOUT) { 362 Ok(seq_info) => break seq_info, 363 Err(ERANGE) => continue, 364 Err(e) => return Err(e), 365 } 366 }; 367 368 let sequencer = GspSequencer { 369 seq_info, 370 bar: params.bar, 371 sec2_falcon: params.sec2_falcon, 372 gsp_falcon: params.gsp_falcon, 373 libos_dma_handle: params.libos_dma_handle, 374 bootloader_app_version: params.bootloader_app_version, 375 dev: params.dev, 376 }; 377 378 dev_dbg!(sequencer.dev, "Running CPU Sequencer commands\n"); 379 380 for cmd_result in sequencer.iter() { 381 match cmd_result { 382 Ok(cmd) => cmd.run(&sequencer)?, 383 Err(e) => { 384 dev_err!( 385 sequencer.dev, 386 "Error running command at index {}\n", 387 sequencer.seq_info.cmd_index 388 ); 389 return Err(e); 390 } 391 } 392 } 393 394 dev_dbg!( 395 sequencer.dev, 396 "CPU Sequencer commands completed successfully\n" 397 ); 398 Ok(()) 399 } 400 } 401