1 // SPDX-License-Identifier: GPL-2.0 2 // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 4 use kernel::{ 5 io::Io, 6 prelude::*, 7 sizes::*, // 8 }; 9 10 use crate::{ 11 driver::Bar0, 12 fb::hal::FbHal, 13 regs, // 14 }; 15 16 /// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`, 17 /// to be used by HALs. 18 pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8; 19 20 pub(super) fn read_sysmem_flush_page_gm107(bar: Bar0<'_>) -> u64 { 21 u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT 22 } 23 24 pub(super) fn write_sysmem_flush_page_gm107(bar: Bar0<'_>, addr: u64) -> Result { 25 // Check that the address doesn't overflow the receiving 32-bit register. 26 u32::try_from(addr >> FLUSH_SYSMEM_ADDR_SHIFT) 27 .map_err(|_| EINVAL) 28 .map(|addr| { 29 bar.write_reg(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed().with_adr_39_08(addr)) 30 }) 31 } 32 33 pub(super) fn display_enabled_gm107(bar: Bar0<'_>) -> bool { 34 !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY) 35 .display_disabled() 36 } 37 38 pub(super) fn vidmem_size_gp102(bar: Bar0<'_>) -> u64 { 39 bar.read(regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE) 40 .usable_fb_size() 41 } 42 43 pub(super) const fn pmu_reserved_size_tu102() -> u32 { 44 0 45 } 46 47 pub(super) const fn non_wpr_heap_size_tu102() -> u32 { 48 u32::SZ_1M 49 } 50 51 pub(super) const fn frts_size_tu102() -> u64 { 52 u64::SZ_1M 53 } 54 55 struct Tu102; 56 57 impl FbHal for Tu102 { 58 fn read_sysmem_flush_page(&self, bar: Bar0<'_>) -> u64 { 59 read_sysmem_flush_page_gm107(bar) 60 } 61 62 fn write_sysmem_flush_page(&self, bar: Bar0<'_>, addr: u64) -> Result { 63 write_sysmem_flush_page_gm107(bar, addr) 64 } 65 66 fn supports_display(&self, bar: Bar0<'_>) -> bool { 67 display_enabled_gm107(bar) 68 } 69 70 fn vidmem_size(&self, bar: Bar0<'_>) -> u64 { 71 vidmem_size_gp102(bar) 72 } 73 74 fn pmu_reserved_size(&self) -> u32 { 75 pmu_reserved_size_tu102() 76 } 77 78 fn non_wpr_heap_size(&self) -> u32 { 79 non_wpr_heap_size_tu102() 80 } 81 82 fn frts_size(&self) -> u64 { 83 frts_size_tu102() 84 } 85 } 86 87 const TU102: Tu102 = Tu102; 88 pub(super) const TU102_HAL: &dyn FbHal = &TU102; 89