1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 io::Io, 5 prelude::*, 6 sizes::*, // 7 }; 8 9 use crate::{ 10 driver::Bar0, 11 fb::hal::FbHal, 12 regs, // 13 }; 14 15 /// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`, 16 /// to be used by HALs. 17 pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8; 18 19 pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 { 20 u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT 21 } 22 23 pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result { 24 // Check that the address doesn't overflow the receiving 32-bit register. 25 u32::try_from(addr >> FLUSH_SYSMEM_ADDR_SHIFT) 26 .map_err(|_| EINVAL) 27 .map(|addr| { 28 bar.write_reg(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed().with_adr_39_08(addr)) 29 }) 30 } 31 32 pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool { 33 !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY) 34 .display_disabled() 35 } 36 37 pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { 38 bar.read(regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE) 39 .usable_fb_size() 40 } 41 42 pub(super) const fn frts_size_tu102() -> u64 { 43 u64::SZ_1M 44 } 45 46 struct Tu102; 47 48 impl FbHal for Tu102 { 49 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { 50 read_sysmem_flush_page_gm107(bar) 51 } 52 53 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { 54 write_sysmem_flush_page_gm107(bar, addr) 55 } 56 57 fn supports_display(&self, bar: &Bar0) -> bool { 58 display_enabled_gm107(bar) 59 } 60 61 fn vidmem_size(&self, bar: &Bar0) -> u64 { 62 vidmem_size_gp102(bar) 63 } 64 65 fn frts_size(&self) -> u64 { 66 frts_size_tu102() 67 } 68 } 69 70 const TU102: Tu102 = Tu102; 71 pub(super) const TU102_HAL: &dyn FbHal = &TU102; 72