1 // SPDX-License-Identifier: GPL-2.0 2 // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 4 use kernel::{ 5 io::Io, 6 prelude::*, 7 sizes::*, // 8 }; 9 10 use crate::{ 11 driver::Bar0, 12 fb::{ 13 hal::FbHal, 14 regs, // 15 }, 16 }; 17 18 /// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`, 19 /// to be used by HALs. 20 pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8; 21 22 pub(super) fn read_sysmem_flush_page_gm107(bar: Bar0<'_>) -> u64 { 23 u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT 24 } 25 26 pub(super) fn write_sysmem_flush_page_gm107(bar: Bar0<'_>, addr: u64) -> Result { 27 // Check that the address doesn't overflow the receiving 32-bit register. 28 u32::try_from(addr >> FLUSH_SYSMEM_ADDR_SHIFT) 29 .map_err(|_| EINVAL) 30 .map(|addr| { 31 bar.write_reg(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed().with_adr_39_08(addr)) 32 }) 33 } 34 35 pub(super) fn display_enabled_gm107(bar: Bar0<'_>) -> bool { 36 !bar.read(crate::regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY) 37 .display_disabled() 38 } 39 40 pub(super) fn vidmem_size_gp102(bar: Bar0<'_>) -> u64 { 41 bar.read(regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE) 42 .usable_fb_size() 43 } 44 45 pub(super) const fn pmu_reserved_size_tu102() -> u32 { 46 0 47 } 48 49 pub(super) const fn non_wpr_heap_size_tu102() -> u64 { 50 u64::SZ_1M 51 } 52 53 pub(super) const fn frts_size_tu102() -> u64 { 54 u64::SZ_1M 55 } 56 57 struct Tu102; 58 59 impl FbHal for Tu102 { 60 fn read_sysmem_flush_page(&self, bar: Bar0<'_>) -> u64 { 61 read_sysmem_flush_page_gm107(bar) 62 } 63 64 fn write_sysmem_flush_page(&self, bar: Bar0<'_>, addr: u64) -> Result { 65 write_sysmem_flush_page_gm107(bar, addr) 66 } 67 68 fn supports_display(&self, bar: Bar0<'_>) -> bool { 69 display_enabled_gm107(bar) 70 } 71 72 fn vidmem_size(&self, bar: Bar0<'_>) -> u64 { 73 vidmem_size_gp102(bar) 74 } 75 76 fn pmu_reserved_size(&self) -> u32 { 77 pmu_reserved_size_tu102() 78 } 79 80 fn non_wpr_heap_size(&self) -> u64 { 81 non_wpr_heap_size_tu102() 82 } 83 84 fn frts_size(&self) -> u64 { 85 frts_size_tu102() 86 } 87 } 88 89 const TU102: Tu102 = Tu102; 90 pub(super) const TU102_HAL: &dyn FbHal = &TU102; 91