1 // SPDX-License-Identifier: GPL-2.0 2 3 struct Ga100; 4 5 use kernel::prelude::*; 6 7 use crate::driver::Bar0; 8 use crate::fb::hal::FbHal; 9 use crate::regs; 10 11 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; 12 13 pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { 14 u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT 15 | u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40()) 16 << FLUSH_SYSMEM_ADDR_SHIFT_HI 17 } 18 19 pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { 20 regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::default() 21 .set_adr_63_40((addr >> FLUSH_SYSMEM_ADDR_SHIFT_HI) as u32) 22 .write(bar); 23 regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default() 24 .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32) 25 .write(bar); 26 } 27 28 pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { 29 !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled() 30 } 31 32 /// Shift applied to the sysmem address before it is written into 33 /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`, 34 const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 = 40; 35 36 impl FbHal for Ga100 { 37 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { 38 read_sysmem_flush_page_ga100(bar) 39 } 40 41 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { 42 write_sysmem_flush_page_ga100(bar, addr); 43 44 Ok(()) 45 } 46 47 fn supports_display(&self, bar: &Bar0) -> bool { 48 display_enabled_ga100(bar) 49 } 50 51 fn vidmem_size(&self, bar: &Bar0) -> u64 { 52 super::tu102::vidmem_size_gp102(bar) 53 } 54 } 55 56 const GA100: Ga100 = Ga100; 57 pub(super) const GA100_HAL: &dyn FbHal = &GA100; 58