1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 io::Io, 5 num::Bounded, 6 prelude::*, // 7 }; 8 9 use crate::{ 10 driver::Bar0, 11 fb::hal::FbHal, 12 regs, // 13 }; 14 15 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; 16 17 struct Ga100; 18 19 pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { 20 u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT 21 | u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI).adr_63_40()) 22 << FLUSH_SYSMEM_ADDR_SHIFT_HI 23 } 24 25 pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { 26 bar.write_reg( 27 regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::zeroed().with_adr_63_40( 28 Bounded::<u64, _>::from(addr) 29 .shr::<FLUSH_SYSMEM_ADDR_SHIFT_HI, _>() 30 .cast(), 31 ), 32 ); 33 34 bar.write_reg( 35 regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed() 36 // CAST: `as u32` is used on purpose since we want to strip the upper bits that have 37 // been written to `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`. 38 .with_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32), 39 ); 40 } 41 42 pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { 43 !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY) 44 .display_disabled() 45 } 46 47 /// Shift applied to the sysmem address before it is written into 48 /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`, 49 const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 = 40; 50 51 impl FbHal for Ga100 { 52 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { 53 read_sysmem_flush_page_ga100(bar) 54 } 55 56 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { 57 write_sysmem_flush_page_ga100(bar, addr); 58 59 Ok(()) 60 } 61 62 fn supports_display(&self, bar: &Bar0) -> bool { 63 display_enabled_ga100(bar) 64 } 65 66 fn vidmem_size(&self, bar: &Bar0) -> u64 { 67 super::tu102::vidmem_size_gp102(bar) 68 } 69 } 70 71 const GA100: Ga100 = Ga100; 72 pub(super) const GA100_HAL: &dyn FbHal = &GA100; 73