1 // SPDX-License-Identifier: GPL-2.0 2 // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 4 use kernel::prelude::*; 5 6 use crate::{ 7 driver::Bar0, 8 gpu::{ 9 Architecture, 10 Chipset, // 11 }, 12 }; 13 14 mod ga100; 15 mod ga102; 16 mod gb100; 17 mod tu102; 18 19 pub(crate) trait FbHal { 20 /// Returns the address of the currently-registered sysmem flush page. 21 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64; 22 23 /// Register `addr` as the address of the sysmem flush page. 24 /// 25 /// This might fail if the address is too large for the receiving register. 26 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result; 27 28 /// Returns `true` is display is supported. 29 fn supports_display(&self, bar: &Bar0) -> bool; 30 31 /// Returns the VRAM size, in bytes. 32 fn vidmem_size(&self, bar: &Bar0) -> u64; 33 34 /// Returns the amount of VRAM to reserve for the PMU. 35 fn pmu_reserved_size(&self) -> u32; 36 37 /// Returns the FRTS size, in bytes. 38 fn frts_size(&self) -> u64; 39 } 40 41 /// Returns the HAL corresponding to `chipset`. 42 pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { 43 match chipset.arch() { 44 Architecture::Turing => tu102::TU102_HAL, 45 Architecture::Ampere if chipset == Chipset::GA100 => ga100::GA100_HAL, 46 Architecture::Ampere | Architecture::Ada | Architecture::Hopper => ga102::GA102_HAL, 47 Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => gb100::GB100_HAL, 48 } 49 } 50