1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 io::{ 5 poll::read_poll_timeout, 6 register::{ 7 RegisterBase, 8 WithBase, // 9 }, 10 Io, 11 }, 12 prelude::*, 13 time::Delta, // 14 }; 15 16 use crate::{ 17 driver::Bar0, 18 falcon::{ 19 Falcon, 20 FalconEngine, 21 PFalcon2Base, 22 PFalconBase, // 23 }, 24 regs, 25 }; 26 27 /// Type specifying the `Gsp` falcon engine. Cannot be instantiated. 28 pub(crate) struct Gsp(()); 29 30 impl RegisterBase<PFalconBase> for Gsp { 31 const BASE: usize = 0x00110000; 32 } 33 34 impl RegisterBase<PFalcon2Base> for Gsp { 35 const BASE: usize = 0x00111000; 36 } 37 38 impl FalconEngine for Gsp {} 39 40 impl Falcon<Gsp> { 41 /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to 42 /// allow GSP to signal CPU for processing new messages in message queue. 43 pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { 44 bar.write( 45 WithBase::of::<Gsp>(), 46 regs::NV_PFALCON_FALCON_IRQSCLR::zeroed().with_swgen0(true), 47 ); 48 } 49 50 /// Checks if GSP reload/resume has completed during the boot process. 51 pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> { 52 read_poll_timeout( 53 || Ok(bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)), 54 |val| val.boot_stage_3_handoff(), 55 Delta::ZERO, 56 timeout, 57 ) 58 .map(|_| true) 59 } 60 } 61