1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 io::poll::read_poll_timeout, 5 prelude::*, 6 time::Delta, // 7 }; 8 9 use crate::{ 10 driver::Bar0, 11 falcon::{ 12 Falcon, 13 FalconEngine, 14 PFalcon2Base, 15 PFalconBase, // 16 }, 17 regs::{ 18 self, 19 macros::RegisterBase, // 20 }, 21 }; 22 23 /// Type specifying the `Gsp` falcon engine. Cannot be instantiated. 24 pub(crate) struct Gsp(()); 25 26 impl RegisterBase<PFalconBase> for Gsp { 27 const BASE: usize = 0x00110000; 28 } 29 30 impl RegisterBase<PFalcon2Base> for Gsp { 31 const BASE: usize = 0x00111000; 32 } 33 34 impl FalconEngine for Gsp { 35 const ID: Self = Gsp(()); 36 } 37 38 impl Falcon<Gsp> { 39 /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to 40 /// allow GSP to signal CPU for processing new messages in message queue. 41 pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { 42 regs::NV_PFALCON_FALCON_IRQSCLR::default() 43 .set_swgen0(true) 44 .write(bar, &Gsp::ID); 45 } 46 47 /// Checks if GSP reload/resume has completed during the boot process. 48 pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> { 49 read_poll_timeout( 50 || Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)), 51 |val| val.boot_stage_3_handoff(), 52 Delta::ZERO, 53 timeout, 54 ) 55 .map(|_| true) 56 } 57 } 58