1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 auxiliary, 5 device::Core, 6 devres::Devres, 7 dma::Device, 8 dma::DmaMask, 9 pci, 10 pci::{ 11 Class, 12 ClassMask, 13 Vendor, // 14 }, 15 prelude::*, 16 sizes::SZ_16M, 17 sync::{ 18 atomic::{ 19 Atomic, 20 Relaxed, // 21 }, 22 Arc, 23 }, 24 }; 25 26 use crate::gpu::Gpu; 27 28 /// Counter for generating unique auxiliary device IDs. 29 static AUXILIARY_ID_COUNTER: Atomic<u32> = Atomic::new(0); 30 31 #[pin_data] 32 pub(crate) struct NovaCore { 33 #[pin] 34 pub(crate) gpu: Gpu, 35 _reg: Devres<auxiliary::Registration<()>>, 36 } 37 38 pub(crate) struct NovaCoreDriver; 39 40 const BAR0_SIZE: usize = SZ_16M; 41 42 // For now we only support Ampere which can use up to 47-bit DMA addresses. 43 // 44 // TODO: Add an abstraction for this to support newer GPUs which may support 45 // larger DMA addresses. Limiting these GPUs to smaller address widths won't 46 // have any adverse affects, unless installed on systems which require larger 47 // DMA addresses. These systems should be quite rare. 48 const GPU_DMA_BITS: u32 = 47; 49 50 pub(crate) type Bar0 = pci::Bar<'static, BAR0_SIZE>; 51 52 kernel::pci_device_table!( 53 PCI_TABLE, 54 MODULE_PCI_TABLE, 55 <NovaCoreDriver as pci::Driver>::IdInfo, 56 [ 57 // Modern NVIDIA GPUs will show up as either VGA or 3D controllers. 58 ( 59 pci::DeviceId::from_class_and_vendor( 60 Class::DISPLAY_VGA, 61 ClassMask::ClassSubclass, 62 Vendor::NVIDIA 63 ), 64 () 65 ), 66 ( 67 pci::DeviceId::from_class_and_vendor( 68 Class::DISPLAY_3D, 69 ClassMask::ClassSubclass, 70 Vendor::NVIDIA 71 ), 72 () 73 ), 74 ] 75 ); 76 77 impl pci::Driver for NovaCoreDriver { 78 type IdInfo = (); 79 type Data<'bound> = NovaCore; 80 const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE; 81 82 fn probe<'bound>( 83 pdev: &'bound pci::Device<Core<'_>>, 84 _info: &'bound Self::IdInfo, 85 ) -> impl PinInit<NovaCore, Error> + 'bound { 86 pin_init::pin_init_scope(move || { 87 dev_dbg!(pdev, "Probe Nova Core GPU driver.\n"); 88 89 pdev.enable_device_mem()?; 90 pdev.set_master(); 91 92 // SAFETY: No concurrent DMA allocations or mappings can be made because 93 // the device is still being probed and therefore isn't being used by 94 // other threads of execution. 95 unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<GPU_DMA_BITS>())? }; 96 97 let bar = Arc::new( 98 pdev.iomap_region_sized::<BAR0_SIZE>(0, c"nova-core/bar0")? 99 .into_devres()?, 100 GFP_KERNEL, 101 )?; 102 103 Ok(try_pin_init!(NovaCore { 104 gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref())?), 105 _reg: auxiliary::Registration::new( 106 pdev.as_ref(), 107 c"nova-drm", 108 // TODO[XARR]: Use XArray or perhaps IDA for proper ID allocation/recycling. For 109 // now, use a simple atomic counter that never recycles IDs. 110 AUXILIARY_ID_COUNTER.fetch_add(1, Relaxed), 111 crate::MODULE_NAME, 112 (), 113 )?, 114 })) 115 }) 116 } 117 118 fn unbind<'bound>(pdev: &'bound pci::Device<Core<'_>>, this: Pin<&NovaCore>) { 119 this.gpu.unbind(pdev.as_ref()); 120 } 121 } 122