1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 auxiliary, 5 device::Core, 6 dma::Device, 7 dma::DmaMask, 8 pci, 9 pci::{ 10 Class, 11 ClassMask, 12 Vendor, // 13 }, 14 prelude::*, 15 sizes::SZ_16M, 16 sync::atomic::{ 17 Atomic, 18 Relaxed, // 19 }, 20 types::ForLt, 21 }; 22 23 use crate::gpu::Gpu; 24 25 /// Counter for generating unique auxiliary device IDs. 26 static AUXILIARY_ID_COUNTER: Atomic<u32> = Atomic::new(0); 27 28 #[pin_data] 29 pub(crate) struct NovaCore<'bound> { 30 #[pin] 31 pub(crate) gpu: Gpu<'bound>, 32 bar: pci::Bar<'bound, BAR0_SIZE>, 33 #[allow(clippy::type_complexity)] 34 _reg: auxiliary::Registration<'bound, ForLt!(())>, 35 } 36 37 pub(crate) struct NovaCoreDriver; 38 39 const BAR0_SIZE: usize = SZ_16M; 40 41 // For now we only support Ampere which can use up to 47-bit DMA addresses. 42 // 43 // TODO: Add an abstraction for this to support newer GPUs which may support 44 // larger DMA addresses. Limiting these GPUs to smaller address widths won't 45 // have any adverse affects, unless installed on systems which require larger 46 // DMA addresses. These systems should be quite rare. 47 const GPU_DMA_BITS: u32 = 47; 48 49 pub(crate) type Bar0 = kernel::io::Mmio<BAR0_SIZE>; 50 51 kernel::pci_device_table!( 52 PCI_TABLE, 53 MODULE_PCI_TABLE, 54 <NovaCoreDriver as pci::Driver>::IdInfo, 55 [ 56 // Modern NVIDIA GPUs will show up as either VGA or 3D controllers. 57 ( 58 pci::DeviceId::from_class_and_vendor( 59 Class::DISPLAY_VGA, 60 ClassMask::ClassSubclass, 61 Vendor::NVIDIA 62 ), 63 () 64 ), 65 ( 66 pci::DeviceId::from_class_and_vendor( 67 Class::DISPLAY_3D, 68 ClassMask::ClassSubclass, 69 Vendor::NVIDIA 70 ), 71 () 72 ), 73 ] 74 ); 75 76 impl pci::Driver for NovaCoreDriver { 77 type IdInfo = (); 78 type Data<'bound> = NovaCore<'bound>; 79 const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE; 80 81 fn probe<'bound>( 82 pdev: &'bound pci::Device<Core<'_>>, 83 _info: &'bound Self::IdInfo, 84 ) -> impl PinInit<Self::Data<'bound>, Error> + 'bound { 85 pin_init::pin_init_scope(move || { 86 dev_dbg!(pdev, "Probe Nova Core GPU driver.\n"); 87 88 pdev.enable_device_mem()?; 89 pdev.set_master(); 90 91 // SAFETY: No concurrent DMA allocations or mappings can be made because 92 // the device is still being probed and therefore isn't being used by 93 // other threads of execution. 94 unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<GPU_DMA_BITS>())? }; 95 96 Ok(try_pin_init!(NovaCore { 97 bar: pdev.iomap_region_sized::<BAR0_SIZE>(0, c"nova-core/bar0")?, 98 // TODO: Use `&bar` self-referential pin-init syntax once available. 99 // 100 // SAFETY: `bar` is initialized before this expression is evaluated 101 // (`try_pin_init!()` initializes fields in declaration order), lives at a pinned 102 // stable address, and is dropped after `gpu` (struct field drop order). 103 gpu <- Gpu::new(pdev, unsafe { &*core::ptr::from_ref(bar) }), 104 _reg: auxiliary::Registration::new( 105 pdev.as_ref(), 106 c"nova-drm", 107 // TODO[XARR]: Use XArray or perhaps IDA for proper ID allocation/recycling. For 108 // now, use a simple atomic counter that never recycles IDs. 109 AUXILIARY_ID_COUNTER.fetch_add(1, Relaxed), 110 crate::MODULE_NAME, 111 (), 112 )?, 113 })) 114 }) 115 } 116 } 117