1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 auxiliary, 5 device::Core, 6 devres::Devres, 7 dma::Device, 8 dma::DmaMask, 9 pci, 10 pci::{ 11 Class, 12 ClassMask, 13 Vendor, // 14 }, 15 prelude::*, 16 sizes::SZ_16M, 17 sync::{ 18 atomic::{ 19 Atomic, 20 Relaxed, // 21 }, 22 Arc, 23 }, 24 }; 25 26 use crate::gpu::Gpu; 27 28 /// Counter for generating unique auxiliary device IDs. 29 static AUXILIARY_ID_COUNTER: Atomic<u32> = Atomic::new(0); 30 31 #[pin_data] 32 pub(crate) struct NovaCore { 33 #[pin] 34 pub(crate) gpu: Gpu, 35 _reg: Devres<auxiliary::Registration<()>>, 36 } 37 38 const BAR0_SIZE: usize = SZ_16M; 39 40 // For now we only support Ampere which can use up to 47-bit DMA addresses. 41 // 42 // TODO: Add an abstraction for this to support newer GPUs which may support 43 // larger DMA addresses. Limiting these GPUs to smaller address widths won't 44 // have any adverse affects, unless installed on systems which require larger 45 // DMA addresses. These systems should be quite rare. 46 const GPU_DMA_BITS: u32 = 47; 47 48 pub(crate) type Bar0 = pci::Bar<BAR0_SIZE>; 49 50 kernel::pci_device_table!( 51 PCI_TABLE, 52 MODULE_PCI_TABLE, 53 <NovaCore as pci::Driver>::IdInfo, 54 [ 55 // Modern NVIDIA GPUs will show up as either VGA or 3D controllers. 56 ( 57 pci::DeviceId::from_class_and_vendor( 58 Class::DISPLAY_VGA, 59 ClassMask::ClassSubclass, 60 Vendor::NVIDIA 61 ), 62 () 63 ), 64 ( 65 pci::DeviceId::from_class_and_vendor( 66 Class::DISPLAY_3D, 67 ClassMask::ClassSubclass, 68 Vendor::NVIDIA 69 ), 70 () 71 ), 72 ] 73 ); 74 75 impl pci::Driver for NovaCore { 76 type IdInfo = (); 77 type Data = Self; 78 const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE; 79 80 fn probe(pdev: &pci::Device<Core<'_>>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> { 81 pin_init::pin_init_scope(move || { 82 dev_dbg!(pdev, "Probe Nova Core GPU driver.\n"); 83 84 pdev.enable_device_mem()?; 85 pdev.set_master(); 86 87 // SAFETY: No concurrent DMA allocations or mappings can be made because 88 // the device is still being probed and therefore isn't being used by 89 // other threads of execution. 90 unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<GPU_DMA_BITS>())? }; 91 92 let bar = Arc::pin_init( 93 pdev.iomap_region_sized::<BAR0_SIZE>(0, c"nova-core/bar0"), 94 GFP_KERNEL, 95 )?; 96 97 Ok(try_pin_init!(Self { 98 gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref())?), 99 _reg: auxiliary::Registration::new( 100 pdev.as_ref(), 101 c"nova-drm", 102 // TODO[XARR]: Use XArray or perhaps IDA for proper ID allocation/recycling. For 103 // now, use a simple atomic counter that never recycles IDs. 104 AUXILIARY_ID_COUNTER.fetch_add(1, Relaxed), 105 crate::MODULE_NAME, 106 (), 107 )?, 108 })) 109 }) 110 } 111 112 fn unbind(pdev: &pci::Device<Core<'_>>, this: Pin<&Self>) { 113 this.gpu.unbind(pdev.as_ref()); 114 } 115 } 116