1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 5 */ 6 #include <linux/export.h> 7 #include <linux/module.h> 8 #include <linux/types.h> 9 #include <linux/errno.h> 10 #include <linux/io.h> 11 #include <linux/err.h> 12 #include <linux/platform_device.h> 13 14 #include <video/imx-ipu-v3.h> 15 #include "ipu-prv.h" 16 17 struct ipu_di { 18 void __iomem *base; 19 int id; 20 u32 module; 21 struct clk *clk_di; /* display input clock */ 22 struct clk *clk_ipu; /* IPU bus clock */ 23 struct clk *clk_di_pixel; /* resulting pixel clock */ 24 bool inuse; 25 struct ipu_soc *ipu; 26 }; 27 28 static DEFINE_MUTEX(di_mutex); 29 30 struct di_sync_config { 31 int run_count; 32 int run_src; 33 int offset_count; 34 int offset_src; 35 int repeat_count; 36 int cnt_clr_src; 37 int cnt_polarity_gen_en; 38 int cnt_polarity_clr_src; 39 int cnt_polarity_trigger_src; 40 int cnt_up; 41 int cnt_down; 42 }; 43 44 enum di_pins { 45 DI_PIN11 = 0, 46 DI_PIN12 = 1, 47 DI_PIN13 = 2, 48 DI_PIN14 = 3, 49 DI_PIN15 = 4, 50 DI_PIN16 = 5, 51 DI_PIN17 = 6, 52 DI_PIN_CS = 7, 53 54 DI_PIN_SER_CLK = 0, 55 DI_PIN_SER_RS = 1, 56 }; 57 58 enum di_sync_wave { 59 DI_SYNC_NONE = 0, 60 DI_SYNC_CLK = 1, 61 DI_SYNC_INT_HSYNC = 2, 62 DI_SYNC_HSYNC = 3, 63 DI_SYNC_VSYNC = 4, 64 DI_SYNC_DE = 6, 65 66 DI_SYNC_CNT1 = 2, /* counter >= 2 only */ 67 DI_SYNC_CNT4 = 5, /* counter >= 5 only */ 68 DI_SYNC_CNT5 = 6, /* counter >= 6 only */ 69 }; 70 71 #define SYNC_WAVE 0 72 73 #define DI_GENERAL 0x0000 74 #define DI_BS_CLKGEN0 0x0004 75 #define DI_BS_CLKGEN1 0x0008 76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1)) 77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1)) 78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2)) 79 #define DI_SYNC_AS_GEN 0x0054 80 #define DI_DW_GEN(gen) (0x0058 + 4 * (gen)) 81 #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set))) 82 #define DI_SER_CONF 0x015c 83 #define DI_SSC 0x0160 84 #define DI_POL 0x0164 85 #define DI_AW0 0x0168 86 #define DI_AW1 0x016c 87 #define DI_SCR_CONF 0x0170 88 #define DI_STAT 0x0174 89 90 #define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19) 91 #define DI_SW_GEN0_RUN_SRC(x) ((x) << 16) 92 #define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3) 93 #define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0) 94 95 #define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29) 96 #define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25) 97 #define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12) 98 #define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9) 99 #define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16) 100 #define DI_SW_GEN1_CNT_UP(x) (x) 101 #define DI_SW_GEN1_AUTO_RELOAD (0x10000000) 102 103 #define DI_DW_GEN_ACCESS_SIZE_OFFSET 24 104 #define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16 105 106 #define DI_GEN_POLARITY_1 (1 << 0) 107 #define DI_GEN_POLARITY_2 (1 << 1) 108 #define DI_GEN_POLARITY_3 (1 << 2) 109 #define DI_GEN_POLARITY_4 (1 << 3) 110 #define DI_GEN_POLARITY_5 (1 << 4) 111 #define DI_GEN_POLARITY_6 (1 << 5) 112 #define DI_GEN_POLARITY_7 (1 << 6) 113 #define DI_GEN_POLARITY_8 (1 << 7) 114 #define DI_GEN_POLARITY_DISP_CLK (1 << 17) 115 #define DI_GEN_DI_CLK_EXT (1 << 20) 116 #define DI_GEN_DI_VSYNC_EXT (1 << 21) 117 118 #define DI_POL_DRDY_DATA_POLARITY (1 << 7) 119 #define DI_POL_DRDY_POLARITY_15 (1 << 4) 120 121 #define DI_VSYNC_SEL_OFFSET 13 122 123 static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset) 124 { 125 return readl(di->base + offset); 126 } 127 128 static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset) 129 { 130 writel(value, di->base + offset); 131 } 132 133 static void ipu_di_data_wave_config(struct ipu_di *di, 134 int wave_gen, 135 int access_size, int component_size) 136 { 137 u32 reg; 138 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | 139 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); 140 ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); 141 } 142 143 static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin, 144 int set, int up, int down) 145 { 146 u32 reg; 147 148 reg = ipu_di_read(di, DI_DW_GEN(wave_gen)); 149 reg &= ~(0x3 << (di_pin * 2)); 150 reg |= set << (di_pin * 2); 151 ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); 152 153 ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set)); 154 } 155 156 static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config, 157 int start, int count) 158 { 159 u32 reg; 160 int i; 161 162 for (i = 0; i < count; i++) { 163 struct di_sync_config *c = &config[i]; 164 int wave_gen = start + i + 1; 165 166 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || 167 (c->repeat_count >= 0x1000) || 168 (c->cnt_up >= 0x400) || 169 (c->cnt_down >= 0x400)) { 170 dev_err(di->ipu->dev, "DI%d counters out of range.\n", 171 di->id); 172 return; 173 } 174 175 reg = DI_SW_GEN0_RUN_COUNT(c->run_count) | 176 DI_SW_GEN0_RUN_SRC(c->run_src) | 177 DI_SW_GEN0_OFFSET_COUNT(c->offset_count) | 178 DI_SW_GEN0_OFFSET_SRC(c->offset_src); 179 ipu_di_write(di, reg, DI_SW_GEN0(wave_gen)); 180 181 reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) | 182 DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) | 183 DI_SW_GEN1_CNT_POL_TRIGGER_SRC( 184 c->cnt_polarity_trigger_src) | 185 DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) | 186 DI_SW_GEN1_CNT_DOWN(c->cnt_down) | 187 DI_SW_GEN1_CNT_UP(c->cnt_up); 188 189 /* Enable auto reload */ 190 if (c->repeat_count == 0) 191 reg |= DI_SW_GEN1_AUTO_RELOAD; 192 193 ipu_di_write(di, reg, DI_SW_GEN1(wave_gen)); 194 195 reg = ipu_di_read(di, DI_STP_REP(wave_gen)); 196 reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1))); 197 reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1)); 198 ipu_di_write(di, reg, DI_STP_REP(wave_gen)); 199 } 200 } 201 202 static void ipu_di_sync_config_interlaced(struct ipu_di *di, 203 struct ipu_di_signal_cfg *sig) 204 { 205 u32 h_total = sig->mode.hactive + sig->mode.hsync_len + 206 sig->mode.hback_porch + sig->mode.hfront_porch; 207 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + 208 sig->mode.vback_porch + sig->mode.vfront_porch; 209 struct di_sync_config cfg[] = { 210 { 211 /* 1: internal VSYNC for each frame */ 212 .run_count = v_total * 2 - 1, 213 .run_src = 3, /* == counter 7 */ 214 }, { 215 /* PIN2: HSYNC waveform */ 216 .run_count = h_total - 1, 217 .run_src = DI_SYNC_CLK, 218 .cnt_polarity_gen_en = 1, 219 .cnt_polarity_trigger_src = DI_SYNC_CLK, 220 .cnt_down = sig->mode.hsync_len * 2, 221 }, { 222 /* PIN3: VSYNC waveform */ 223 .run_count = v_total - 1, 224 .run_src = 4, /* == counter 7 */ 225 .cnt_polarity_gen_en = 1, 226 .cnt_polarity_trigger_src = 4, /* == counter 7 */ 227 .cnt_down = sig->mode.vsync_len * 2, 228 .cnt_clr_src = DI_SYNC_CNT1, 229 }, { 230 /* 4: Field */ 231 .run_count = v_total / 2, 232 .run_src = DI_SYNC_HSYNC, 233 .offset_count = h_total / 2, 234 .offset_src = DI_SYNC_CLK, 235 .repeat_count = 2, 236 .cnt_clr_src = DI_SYNC_CNT1, 237 }, { 238 /* 5: Active lines */ 239 .run_src = DI_SYNC_HSYNC, 240 .offset_count = (sig->mode.vsync_len + 241 sig->mode.vback_porch) / 2, 242 .offset_src = DI_SYNC_HSYNC, 243 .repeat_count = sig->mode.vactive / 2, 244 .cnt_clr_src = DI_SYNC_CNT4, 245 }, { 246 /* 6: Active pixel, referenced by DC */ 247 .run_src = DI_SYNC_CLK, 248 .offset_count = sig->mode.hsync_len + 249 sig->mode.hback_porch, 250 .offset_src = DI_SYNC_CLK, 251 .repeat_count = sig->mode.hactive, 252 .cnt_clr_src = DI_SYNC_CNT5, 253 }, { 254 /* 7: Half line HSYNC */ 255 .run_count = h_total / 2 - 1, 256 .run_src = DI_SYNC_CLK, 257 } 258 }; 259 260 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); 261 262 ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF); 263 } 264 265 static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, 266 struct ipu_di_signal_cfg *sig, int div) 267 { 268 u32 h_total = sig->mode.hactive + sig->mode.hsync_len + 269 sig->mode.hback_porch + sig->mode.hfront_porch; 270 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + 271 sig->mode.vback_porch + sig->mode.vfront_porch; 272 struct di_sync_config cfg[] = { 273 { 274 /* 1: INT_HSYNC */ 275 .run_count = h_total - 1, 276 .run_src = DI_SYNC_CLK, 277 } , { 278 /* PIN2: HSYNC */ 279 .run_count = h_total - 1, 280 .run_src = DI_SYNC_CLK, 281 .offset_count = div * sig->v_to_h_sync, 282 .offset_src = DI_SYNC_CLK, 283 .cnt_polarity_gen_en = 1, 284 .cnt_polarity_trigger_src = DI_SYNC_CLK, 285 .cnt_down = sig->mode.hsync_len * 2, 286 } , { 287 /* PIN3: VSYNC */ 288 .run_count = v_total - 1, 289 .run_src = DI_SYNC_INT_HSYNC, 290 .cnt_polarity_gen_en = 1, 291 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, 292 .cnt_down = sig->mode.vsync_len * 2, 293 } , { 294 /* 4: Line Active */ 295 .run_src = DI_SYNC_HSYNC, 296 .offset_count = sig->mode.vsync_len + 297 sig->mode.vback_porch, 298 .offset_src = DI_SYNC_HSYNC, 299 .repeat_count = sig->mode.vactive, 300 .cnt_clr_src = DI_SYNC_VSYNC, 301 } , { 302 /* 5: Pixel Active, referenced by DC */ 303 .run_src = DI_SYNC_CLK, 304 .offset_count = sig->mode.hsync_len + 305 sig->mode.hback_porch, 306 .offset_src = DI_SYNC_CLK, 307 .repeat_count = sig->mode.hactive, 308 .cnt_clr_src = 5, /* Line Active */ 309 } , { 310 /* unused */ 311 } , { 312 /* unused */ 313 } , { 314 /* unused */ 315 } , { 316 /* unused */ 317 }, 318 }; 319 /* can't use #7 and #8 for line active and pixel active counters */ 320 struct di_sync_config cfg_vga[] = { 321 { 322 /* 1: INT_HSYNC */ 323 .run_count = h_total - 1, 324 .run_src = DI_SYNC_CLK, 325 } , { 326 /* 2: VSYNC */ 327 .run_count = v_total - 1, 328 .run_src = DI_SYNC_INT_HSYNC, 329 } , { 330 /* 3: Line Active */ 331 .run_src = DI_SYNC_INT_HSYNC, 332 .offset_count = sig->mode.vsync_len + 333 sig->mode.vback_porch, 334 .offset_src = DI_SYNC_INT_HSYNC, 335 .repeat_count = sig->mode.vactive, 336 .cnt_clr_src = 3 /* VSYNC */, 337 } , { 338 /* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */ 339 .run_count = h_total - 1, 340 .run_src = DI_SYNC_CLK, 341 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ 342 .offset_src = DI_SYNC_CLK, 343 .cnt_polarity_gen_en = 1, 344 .cnt_polarity_trigger_src = DI_SYNC_CLK, 345 .cnt_down = sig->mode.hsync_len * 2, 346 } , { 347 /* 5: Pixel Active signal to DC */ 348 .run_src = DI_SYNC_CLK, 349 .offset_count = sig->mode.hsync_len + 350 sig->mode.hback_porch, 351 .offset_src = DI_SYNC_CLK, 352 .repeat_count = sig->mode.hactive, 353 .cnt_clr_src = 4, /* Line Active */ 354 } , { 355 /* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */ 356 .run_count = v_total - 1, 357 .run_src = DI_SYNC_INT_HSYNC, 358 .offset_count = 1, /* magic value from Freescale TVE driver */ 359 .offset_src = DI_SYNC_INT_HSYNC, 360 .cnt_polarity_gen_en = 1, 361 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, 362 .cnt_down = sig->mode.vsync_len * 2, 363 } , { 364 /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */ 365 .run_count = h_total - 1, 366 .run_src = DI_SYNC_CLK, 367 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ 368 .offset_src = DI_SYNC_CLK, 369 .cnt_polarity_gen_en = 1, 370 .cnt_polarity_trigger_src = DI_SYNC_CLK, 371 .cnt_down = sig->mode.hsync_len * 2, 372 } , { 373 /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */ 374 .run_count = v_total - 1, 375 .run_src = DI_SYNC_INT_HSYNC, 376 .offset_count = 1, /* magic value from Freescale TVE driver */ 377 .offset_src = DI_SYNC_INT_HSYNC, 378 .cnt_polarity_gen_en = 1, 379 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, 380 .cnt_down = sig->mode.vsync_len * 2, 381 } , { 382 /* unused */ 383 }, 384 }; 385 386 ipu_di_write(di, v_total - 1, DI_SCR_CONF); 387 if (sig->hsync_pin == 2 && sig->vsync_pin == 3) 388 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); 389 else 390 ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga)); 391 } 392 393 static void ipu_di_config_clock(struct ipu_di *di, 394 const struct ipu_di_signal_cfg *sig) 395 { 396 struct clk *clk; 397 unsigned clkgen0; 398 uint32_t val; 399 400 if (sig->clkflags & IPU_DI_CLKMODE_EXT) { 401 /* 402 * CLKMODE_EXT means we must use the DI clock: this is 403 * needed for things like LVDS which needs to feed the 404 * DI and LDB with the same pixel clock. 405 */ 406 clk = di->clk_di; 407 408 if (sig->clkflags & IPU_DI_CLKMODE_SYNC) { 409 /* 410 * CLKMODE_SYNC means that we want the DI to be 411 * clocked at the same rate as the parent clock. 412 * This is needed (eg) for LDB which needs to be 413 * fed with the same pixel clock. We assume that 414 * the LDB clock has already been set correctly. 415 */ 416 clkgen0 = 1 << 4; 417 } else { 418 /* 419 * We can use the divider. We should really have 420 * a flag here indicating whether the bridge can 421 * cope with a fractional divider or not. For the 422 * time being, let's go for simplicitly and 423 * reliability. 424 */ 425 unsigned long in_rate; 426 unsigned div; 427 428 clk_set_rate(clk, sig->mode.pixelclock); 429 430 in_rate = clk_get_rate(clk); 431 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); 432 div = clamp(div, 1U, 255U); 433 434 clkgen0 = div << 4; 435 } 436 } else { 437 /* 438 * For other interfaces, we can arbitarily select between 439 * the DI specific clock and the internal IPU clock. See 440 * DI_GENERAL bit 20. We select the IPU clock if it can 441 * give us a clock rate within 1% of the requested frequency, 442 * otherwise we use the DI clock. 443 */ 444 unsigned long rate, clkrate; 445 unsigned div, error; 446 447 clkrate = clk_get_rate(di->clk_ipu); 448 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); 449 div = clamp(div, 1U, 255U); 450 rate = clkrate / div; 451 452 error = rate / (sig->mode.pixelclock / 1000); 453 454 dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n", 455 rate, div, (signed)(error - 1000) / 10, error % 10); 456 457 /* Allow a 1% error */ 458 if (error < 1010 && error >= 990) { 459 clk = di->clk_ipu; 460 461 clkgen0 = div << 4; 462 } else { 463 unsigned long in_rate; 464 unsigned div; 465 466 clk = di->clk_di; 467 468 clk_set_rate(clk, sig->mode.pixelclock); 469 470 in_rate = clk_get_rate(clk); 471 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); 472 div = clamp(div, 1U, 255U); 473 474 clkgen0 = div << 4; 475 } 476 } 477 478 di->clk_di_pixel = clk; 479 480 /* Set the divider */ 481 ipu_di_write(di, clkgen0, DI_BS_CLKGEN0); 482 483 /* 484 * Set the high/low periods. Bits 24:16 give us the falling edge, 485 * and bits 8:0 give the rising edge. LSB is fraction, and is 486 * based on the divider above. We want a 50% duty cycle, so set 487 * the falling edge to be half the divider. 488 */ 489 ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1); 490 491 /* Finally select the input clock */ 492 val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT; 493 if (clk == di->clk_di) 494 val |= DI_GEN_DI_CLK_EXT; 495 ipu_di_write(di, val, DI_GENERAL); 496 497 dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n", 498 sig->mode.pixelclock, 499 clk_get_rate(di->clk_ipu), 500 clk_get_rate(di->clk_di), 501 clk == di->clk_di ? "DI" : "IPU", 502 clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4)); 503 } 504 505 /* 506 * This function is called to adjust a video mode to IPU restrictions. 507 * It is meant to be called from drm crtc mode_fixup() methods. 508 */ 509 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode) 510 { 511 u32 diff; 512 513 if (mode->vfront_porch >= 2) 514 return 0; 515 516 diff = 2 - mode->vfront_porch; 517 518 if (mode->vback_porch >= diff) { 519 mode->vfront_porch = 2; 520 mode->vback_porch -= diff; 521 } else if (mode->vsync_len > diff) { 522 mode->vfront_porch = 2; 523 mode->vsync_len = mode->vsync_len - diff; 524 } else { 525 dev_warn(di->ipu->dev, "failed to adjust videomode\n"); 526 return -EINVAL; 527 } 528 529 dev_dbg(di->ipu->dev, "videomode adapted for IPU restrictions\n"); 530 return 0; 531 } 532 EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode); 533 534 static u32 ipu_di_gen_polarity(int pin) 535 { 536 switch (pin) { 537 case 1: 538 return DI_GEN_POLARITY_1; 539 case 2: 540 return DI_GEN_POLARITY_2; 541 case 3: 542 return DI_GEN_POLARITY_3; 543 case 4: 544 return DI_GEN_POLARITY_4; 545 case 5: 546 return DI_GEN_POLARITY_5; 547 case 6: 548 return DI_GEN_POLARITY_6; 549 case 7: 550 return DI_GEN_POLARITY_7; 551 case 8: 552 return DI_GEN_POLARITY_8; 553 } 554 return 0; 555 } 556 557 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) 558 { 559 u32 reg; 560 u32 di_gen, vsync_cnt; 561 u32 div; 562 563 dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n", 564 di->id, sig->mode.hactive, sig->mode.vactive); 565 566 dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n", 567 clk_get_rate(di->clk_ipu), 568 clk_get_rate(di->clk_di), 569 sig->mode.pixelclock); 570 571 mutex_lock(&di_mutex); 572 573 ipu_di_config_clock(di, sig); 574 575 div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff; 576 div = div / 16; /* Now divider is integer portion */ 577 578 /* Setup pixel clock timing */ 579 /* Down time is half of period */ 580 ipu_di_write(di, (div << 16), DI_BS_CLKGEN1); 581 582 ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1); 583 ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); 584 585 di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT; 586 di_gen |= DI_GEN_DI_VSYNC_EXT; 587 588 if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) { 589 ipu_di_sync_config_interlaced(di, sig); 590 591 /* set y_sel = 1 */ 592 di_gen |= 0x10000000; 593 594 vsync_cnt = 3; 595 } else { 596 ipu_di_sync_config_noninterlaced(di, sig, div); 597 598 vsync_cnt = 3; 599 if (di->id == 1) 600 /* 601 * TODO: change only for TVEv2, parallel display 602 * uses pin 2 / 3 603 */ 604 if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3)) 605 vsync_cnt = 6; 606 } 607 608 if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) 609 di_gen |= ipu_di_gen_polarity(sig->hsync_pin); 610 if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) 611 di_gen |= ipu_di_gen_polarity(sig->vsync_pin); 612 613 if (sig->clk_pol) 614 di_gen |= DI_GEN_POLARITY_DISP_CLK; 615 616 ipu_di_write(di, di_gen, DI_GENERAL); 617 618 ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002, 619 DI_SYNC_AS_GEN); 620 621 reg = ipu_di_read(di, DI_POL); 622 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); 623 624 if (sig->enable_pol) 625 reg |= DI_POL_DRDY_POLARITY_15; 626 if (sig->data_pol) 627 reg |= DI_POL_DRDY_DATA_POLARITY; 628 629 ipu_di_write(di, reg, DI_POL); 630 631 mutex_unlock(&di_mutex); 632 633 return 0; 634 } 635 EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel); 636 637 int ipu_di_enable(struct ipu_di *di) 638 { 639 int ret; 640 641 WARN_ON(IS_ERR(di->clk_di_pixel)); 642 643 ret = clk_prepare_enable(di->clk_di_pixel); 644 if (ret) 645 return ret; 646 647 ipu_module_enable(di->ipu, di->module); 648 649 return 0; 650 } 651 EXPORT_SYMBOL_GPL(ipu_di_enable); 652 653 int ipu_di_disable(struct ipu_di *di) 654 { 655 WARN_ON(IS_ERR(di->clk_di_pixel)); 656 657 ipu_module_disable(di->ipu, di->module); 658 659 clk_disable_unprepare(di->clk_di_pixel); 660 661 return 0; 662 } 663 EXPORT_SYMBOL_GPL(ipu_di_disable); 664 665 int ipu_di_get_num(struct ipu_di *di) 666 { 667 return di->id; 668 } 669 EXPORT_SYMBOL_GPL(ipu_di_get_num); 670 671 static DEFINE_MUTEX(ipu_di_lock); 672 673 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp) 674 { 675 struct ipu_di *di; 676 677 if (disp > 1) 678 return ERR_PTR(-EINVAL); 679 680 di = ipu->di_priv[disp]; 681 682 mutex_lock(&ipu_di_lock); 683 684 if (di->inuse) { 685 di = ERR_PTR(-EBUSY); 686 goto out; 687 } 688 689 di->inuse = true; 690 out: 691 mutex_unlock(&ipu_di_lock); 692 693 return di; 694 } 695 EXPORT_SYMBOL_GPL(ipu_di_get); 696 697 void ipu_di_put(struct ipu_di *di) 698 { 699 mutex_lock(&ipu_di_lock); 700 701 di->inuse = false; 702 703 mutex_unlock(&ipu_di_lock); 704 } 705 EXPORT_SYMBOL_GPL(ipu_di_put); 706 707 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, 708 unsigned long base, 709 u32 module, struct clk *clk_ipu) 710 { 711 struct ipu_di *di; 712 713 if (id > 1) 714 return -ENODEV; 715 716 di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL); 717 if (!di) 718 return -ENOMEM; 719 720 ipu->di_priv[id] = di; 721 722 di->clk_di = devm_clk_get(dev, id ? "di1" : "di0"); 723 if (IS_ERR(di->clk_di)) 724 return PTR_ERR(di->clk_di); 725 726 di->module = module; 727 di->id = id; 728 di->clk_ipu = clk_ipu; 729 di->base = devm_ioremap(dev, base, PAGE_SIZE); 730 if (!di->base) 731 return -ENOMEM; 732 733 ipu_di_write(di, 0x10, DI_BS_CLKGEN0); 734 735 dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n", 736 id, base, di->base); 737 di->inuse = false; 738 di->ipu = ipu; 739 740 return 0; 741 } 742 743 void ipu_di_exit(struct ipu_soc *ipu, int id) 744 { 745 } 746