1 /* 2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 #include <linux/export.h> 16 #include <linux/module.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/io.h> 20 #include <linux/err.h> 21 #include <linux/platform_device.h> 22 23 #include <video/imx-ipu-v3.h> 24 #include "ipu-prv.h" 25 26 struct ipu_di { 27 void __iomem *base; 28 int id; 29 u32 module; 30 struct clk *clk_di; /* display input clock */ 31 struct clk *clk_ipu; /* IPU bus clock */ 32 struct clk *clk_di_pixel; /* resulting pixel clock */ 33 bool inuse; 34 struct ipu_soc *ipu; 35 }; 36 37 static DEFINE_MUTEX(di_mutex); 38 39 struct di_sync_config { 40 int run_count; 41 int run_src; 42 int offset_count; 43 int offset_src; 44 int repeat_count; 45 int cnt_clr_src; 46 int cnt_polarity_gen_en; 47 int cnt_polarity_clr_src; 48 int cnt_polarity_trigger_src; 49 int cnt_up; 50 int cnt_down; 51 }; 52 53 enum di_pins { 54 DI_PIN11 = 0, 55 DI_PIN12 = 1, 56 DI_PIN13 = 2, 57 DI_PIN14 = 3, 58 DI_PIN15 = 4, 59 DI_PIN16 = 5, 60 DI_PIN17 = 6, 61 DI_PIN_CS = 7, 62 63 DI_PIN_SER_CLK = 0, 64 DI_PIN_SER_RS = 1, 65 }; 66 67 enum di_sync_wave { 68 DI_SYNC_NONE = 0, 69 DI_SYNC_CLK = 1, 70 DI_SYNC_INT_HSYNC = 2, 71 DI_SYNC_HSYNC = 3, 72 DI_SYNC_VSYNC = 4, 73 DI_SYNC_DE = 6, 74 }; 75 76 #define SYNC_WAVE 0 77 78 #define DI_GENERAL 0x0000 79 #define DI_BS_CLKGEN0 0x0004 80 #define DI_BS_CLKGEN1 0x0008 81 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1)) 82 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1)) 83 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2)) 84 #define DI_SYNC_AS_GEN 0x0054 85 #define DI_DW_GEN(gen) (0x0058 + 4 * (gen)) 86 #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set))) 87 #define DI_SER_CONF 0x015c 88 #define DI_SSC 0x0160 89 #define DI_POL 0x0164 90 #define DI_AW0 0x0168 91 #define DI_AW1 0x016c 92 #define DI_SCR_CONF 0x0170 93 #define DI_STAT 0x0174 94 95 #define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19) 96 #define DI_SW_GEN0_RUN_SRC(x) ((x) << 16) 97 #define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3) 98 #define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0) 99 100 #define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29) 101 #define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25) 102 #define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12) 103 #define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9) 104 #define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16) 105 #define DI_SW_GEN1_CNT_UP(x) (x) 106 #define DI_SW_GEN1_AUTO_RELOAD (0x10000000) 107 108 #define DI_DW_GEN_ACCESS_SIZE_OFFSET 24 109 #define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16 110 111 #define DI_GEN_POLARITY_1 (1 << 0) 112 #define DI_GEN_POLARITY_2 (1 << 1) 113 #define DI_GEN_POLARITY_3 (1 << 2) 114 #define DI_GEN_POLARITY_4 (1 << 3) 115 #define DI_GEN_POLARITY_5 (1 << 4) 116 #define DI_GEN_POLARITY_6 (1 << 5) 117 #define DI_GEN_POLARITY_7 (1 << 6) 118 #define DI_GEN_POLARITY_8 (1 << 7) 119 #define DI_GEN_POLARITY_DISP_CLK (1 << 17) 120 #define DI_GEN_DI_CLK_EXT (1 << 20) 121 #define DI_GEN_DI_VSYNC_EXT (1 << 21) 122 123 #define DI_POL_DRDY_DATA_POLARITY (1 << 7) 124 #define DI_POL_DRDY_POLARITY_15 (1 << 4) 125 126 #define DI_VSYNC_SEL_OFFSET 13 127 128 static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset) 129 { 130 return readl(di->base + offset); 131 } 132 133 static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset) 134 { 135 writel(value, di->base + offset); 136 } 137 138 static void ipu_di_data_wave_config(struct ipu_di *di, 139 int wave_gen, 140 int access_size, int component_size) 141 { 142 u32 reg; 143 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | 144 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); 145 ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); 146 } 147 148 static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin, 149 int set, int up, int down) 150 { 151 u32 reg; 152 153 reg = ipu_di_read(di, DI_DW_GEN(wave_gen)); 154 reg &= ~(0x3 << (di_pin * 2)); 155 reg |= set << (di_pin * 2); 156 ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); 157 158 ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set)); 159 } 160 161 static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config, 162 int start, int count) 163 { 164 u32 reg; 165 int i; 166 167 for (i = 0; i < count; i++) { 168 struct di_sync_config *c = &config[i]; 169 int wave_gen = start + i + 1; 170 171 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || 172 (c->repeat_count >= 0x1000) || 173 (c->cnt_up >= 0x400) || 174 (c->cnt_down >= 0x400)) { 175 dev_err(di->ipu->dev, "DI%d counters out of range.\n", 176 di->id); 177 return; 178 } 179 180 reg = DI_SW_GEN0_RUN_COUNT(c->run_count) | 181 DI_SW_GEN0_RUN_SRC(c->run_src) | 182 DI_SW_GEN0_OFFSET_COUNT(c->offset_count) | 183 DI_SW_GEN0_OFFSET_SRC(c->offset_src); 184 ipu_di_write(di, reg, DI_SW_GEN0(wave_gen)); 185 186 reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) | 187 DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) | 188 DI_SW_GEN1_CNT_POL_TRIGGER_SRC( 189 c->cnt_polarity_trigger_src) | 190 DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) | 191 DI_SW_GEN1_CNT_DOWN(c->cnt_down) | 192 DI_SW_GEN1_CNT_UP(c->cnt_up); 193 194 /* Enable auto reload */ 195 if (c->repeat_count == 0) 196 reg |= DI_SW_GEN1_AUTO_RELOAD; 197 198 ipu_di_write(di, reg, DI_SW_GEN1(wave_gen)); 199 200 reg = ipu_di_read(di, DI_STP_REP(wave_gen)); 201 reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1))); 202 reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1)); 203 ipu_di_write(di, reg, DI_STP_REP(wave_gen)); 204 } 205 } 206 207 static void ipu_di_sync_config_interlaced(struct ipu_di *di, 208 struct ipu_di_signal_cfg *sig) 209 { 210 u32 h_total = sig->mode.hactive + sig->mode.hsync_len + 211 sig->mode.hback_porch + sig->mode.hfront_porch; 212 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + 213 sig->mode.vback_porch + sig->mode.vfront_porch; 214 u32 reg; 215 struct di_sync_config cfg[] = { 216 { 217 .run_count = h_total / 2 - 1, 218 .run_src = DI_SYNC_CLK, 219 }, { 220 .run_count = h_total - 11, 221 .run_src = DI_SYNC_CLK, 222 .cnt_down = 4, 223 }, { 224 .run_count = v_total * 2 - 1, 225 .run_src = DI_SYNC_INT_HSYNC, 226 .offset_count = 1, 227 .offset_src = DI_SYNC_INT_HSYNC, 228 .cnt_down = 4, 229 }, { 230 .run_count = v_total / 2 - 1, 231 .run_src = DI_SYNC_HSYNC, 232 .offset_count = sig->mode.vback_porch, 233 .offset_src = DI_SYNC_HSYNC, 234 .repeat_count = 2, 235 .cnt_clr_src = DI_SYNC_VSYNC, 236 }, { 237 .run_src = DI_SYNC_HSYNC, 238 .repeat_count = sig->mode.vactive / 2, 239 .cnt_clr_src = 4, 240 }, { 241 .run_count = v_total - 1, 242 .run_src = DI_SYNC_HSYNC, 243 }, { 244 .run_count = v_total / 2 - 1, 245 .run_src = DI_SYNC_HSYNC, 246 .offset_count = 9, 247 .offset_src = DI_SYNC_HSYNC, 248 .repeat_count = 2, 249 .cnt_clr_src = DI_SYNC_VSYNC, 250 }, { 251 .run_src = DI_SYNC_CLK, 252 .offset_count = sig->mode.hback_porch, 253 .offset_src = DI_SYNC_CLK, 254 .repeat_count = sig->mode.hactive, 255 .cnt_clr_src = 5, 256 }, { 257 .run_count = v_total - 1, 258 .run_src = DI_SYNC_INT_HSYNC, 259 .offset_count = v_total / 2, 260 .offset_src = DI_SYNC_INT_HSYNC, 261 .cnt_clr_src = DI_SYNC_HSYNC, 262 .cnt_down = 4, 263 } 264 }; 265 266 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); 267 268 /* set gentime select and tag sel */ 269 reg = ipu_di_read(di, DI_SW_GEN1(9)); 270 reg &= 0x1FFFFFFF; 271 reg |= (3 - 1) << 29 | 0x00008000; 272 ipu_di_write(di, reg, DI_SW_GEN1(9)); 273 274 ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF); 275 } 276 277 static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, 278 struct ipu_di_signal_cfg *sig, int div) 279 { 280 u32 h_total = sig->mode.hactive + sig->mode.hsync_len + 281 sig->mode.hback_porch + sig->mode.hfront_porch; 282 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + 283 sig->mode.vback_porch + sig->mode.vfront_porch; 284 struct di_sync_config cfg[] = { 285 { 286 /* 1: INT_HSYNC */ 287 .run_count = h_total - 1, 288 .run_src = DI_SYNC_CLK, 289 } , { 290 /* PIN2: HSYNC */ 291 .run_count = h_total - 1, 292 .run_src = DI_SYNC_CLK, 293 .offset_count = div * sig->v_to_h_sync, 294 .offset_src = DI_SYNC_CLK, 295 .cnt_polarity_gen_en = 1, 296 .cnt_polarity_trigger_src = DI_SYNC_CLK, 297 .cnt_down = sig->mode.hsync_len * 2, 298 } , { 299 /* PIN3: VSYNC */ 300 .run_count = v_total - 1, 301 .run_src = DI_SYNC_INT_HSYNC, 302 .cnt_polarity_gen_en = 1, 303 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, 304 .cnt_down = sig->mode.vsync_len * 2, 305 } , { 306 /* 4: Line Active */ 307 .run_src = DI_SYNC_HSYNC, 308 .offset_count = sig->mode.vsync_len + 309 sig->mode.vback_porch, 310 .offset_src = DI_SYNC_HSYNC, 311 .repeat_count = sig->mode.vactive, 312 .cnt_clr_src = DI_SYNC_VSYNC, 313 } , { 314 /* 5: Pixel Active, referenced by DC */ 315 .run_src = DI_SYNC_CLK, 316 .offset_count = sig->mode.hsync_len + 317 sig->mode.hback_porch, 318 .offset_src = DI_SYNC_CLK, 319 .repeat_count = sig->mode.hactive, 320 .cnt_clr_src = 5, /* Line Active */ 321 } , { 322 /* unused */ 323 } , { 324 /* unused */ 325 } , { 326 /* unused */ 327 } , { 328 /* unused */ 329 }, 330 }; 331 /* can't use #7 and #8 for line active and pixel active counters */ 332 struct di_sync_config cfg_vga[] = { 333 { 334 /* 1: INT_HSYNC */ 335 .run_count = h_total - 1, 336 .run_src = DI_SYNC_CLK, 337 } , { 338 /* 2: VSYNC */ 339 .run_count = v_total - 1, 340 .run_src = DI_SYNC_INT_HSYNC, 341 } , { 342 /* 3: Line Active */ 343 .run_src = DI_SYNC_INT_HSYNC, 344 .offset_count = sig->mode.vsync_len + 345 sig->mode.vback_porch, 346 .offset_src = DI_SYNC_INT_HSYNC, 347 .repeat_count = sig->mode.vactive, 348 .cnt_clr_src = 3 /* VSYNC */, 349 } , { 350 /* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */ 351 .run_count = h_total - 1, 352 .run_src = DI_SYNC_CLK, 353 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ 354 .offset_src = DI_SYNC_CLK, 355 .cnt_polarity_gen_en = 1, 356 .cnt_polarity_trigger_src = DI_SYNC_CLK, 357 .cnt_down = sig->mode.hsync_len * 2, 358 } , { 359 /* 5: Pixel Active signal to DC */ 360 .run_src = DI_SYNC_CLK, 361 .offset_count = sig->mode.hsync_len + 362 sig->mode.hback_porch, 363 .offset_src = DI_SYNC_CLK, 364 .repeat_count = sig->mode.hactive, 365 .cnt_clr_src = 4, /* Line Active */ 366 } , { 367 /* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */ 368 .run_count = v_total - 1, 369 .run_src = DI_SYNC_INT_HSYNC, 370 .offset_count = 1, /* magic value from Freescale TVE driver */ 371 .offset_src = DI_SYNC_INT_HSYNC, 372 .cnt_polarity_gen_en = 1, 373 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, 374 .cnt_down = sig->mode.vsync_len * 2, 375 } , { 376 /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */ 377 .run_count = h_total - 1, 378 .run_src = DI_SYNC_CLK, 379 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ 380 .offset_src = DI_SYNC_CLK, 381 .cnt_polarity_gen_en = 1, 382 .cnt_polarity_trigger_src = DI_SYNC_CLK, 383 .cnt_down = sig->mode.hsync_len * 2, 384 } , { 385 /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */ 386 .run_count = v_total - 1, 387 .run_src = DI_SYNC_INT_HSYNC, 388 .offset_count = 1, /* magic value from Freescale TVE driver */ 389 .offset_src = DI_SYNC_INT_HSYNC, 390 .cnt_polarity_gen_en = 1, 391 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, 392 .cnt_down = sig->mode.vsync_len * 2, 393 } , { 394 /* unused */ 395 }, 396 }; 397 398 ipu_di_write(di, v_total - 1, DI_SCR_CONF); 399 if (sig->hsync_pin == 2 && sig->vsync_pin == 3) 400 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); 401 else 402 ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga)); 403 } 404 405 static void ipu_di_config_clock(struct ipu_di *di, 406 const struct ipu_di_signal_cfg *sig) 407 { 408 struct clk *clk; 409 unsigned clkgen0; 410 uint32_t val; 411 412 if (sig->clkflags & IPU_DI_CLKMODE_EXT) { 413 /* 414 * CLKMODE_EXT means we must use the DI clock: this is 415 * needed for things like LVDS which needs to feed the 416 * DI and LDB with the same pixel clock. 417 */ 418 clk = di->clk_di; 419 420 if (sig->clkflags & IPU_DI_CLKMODE_SYNC) { 421 /* 422 * CLKMODE_SYNC means that we want the DI to be 423 * clocked at the same rate as the parent clock. 424 * This is needed (eg) for LDB which needs to be 425 * fed with the same pixel clock. We assume that 426 * the LDB clock has already been set correctly. 427 */ 428 clkgen0 = 1 << 4; 429 } else { 430 /* 431 * We can use the divider. We should really have 432 * a flag here indicating whether the bridge can 433 * cope with a fractional divider or not. For the 434 * time being, let's go for simplicitly and 435 * reliability. 436 */ 437 unsigned long in_rate; 438 unsigned div; 439 440 clk_set_rate(clk, sig->mode.pixelclock); 441 442 in_rate = clk_get_rate(clk); 443 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); 444 div = clamp(div, 1U, 255U); 445 446 clkgen0 = div << 4; 447 } 448 } else { 449 /* 450 * For other interfaces, we can arbitarily select between 451 * the DI specific clock and the internal IPU clock. See 452 * DI_GENERAL bit 20. We select the IPU clock if it can 453 * give us a clock rate within 1% of the requested frequency, 454 * otherwise we use the DI clock. 455 */ 456 unsigned long rate, clkrate; 457 unsigned div, error; 458 459 clkrate = clk_get_rate(di->clk_ipu); 460 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); 461 div = clamp(div, 1U, 255U); 462 rate = clkrate / div; 463 464 error = rate / (sig->mode.pixelclock / 1000); 465 466 dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n", 467 rate, div, (signed)(error - 1000) / 10, error % 10); 468 469 /* Allow a 1% error */ 470 if (error < 1010 && error >= 990) { 471 clk = di->clk_ipu; 472 473 clkgen0 = div << 4; 474 } else { 475 unsigned long in_rate; 476 unsigned div; 477 478 clk = di->clk_di; 479 480 clk_set_rate(clk, sig->mode.pixelclock); 481 482 in_rate = clk_get_rate(clk); 483 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); 484 div = clamp(div, 1U, 255U); 485 486 clkgen0 = div << 4; 487 } 488 } 489 490 di->clk_di_pixel = clk; 491 492 /* Set the divider */ 493 ipu_di_write(di, clkgen0, DI_BS_CLKGEN0); 494 495 /* 496 * Set the high/low periods. Bits 24:16 give us the falling edge, 497 * and bits 8:0 give the rising edge. LSB is fraction, and is 498 * based on the divider above. We want a 50% duty cycle, so set 499 * the falling edge to be half the divider. 500 */ 501 ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1); 502 503 /* Finally select the input clock */ 504 val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT; 505 if (clk == di->clk_di) 506 val |= DI_GEN_DI_CLK_EXT; 507 ipu_di_write(di, val, DI_GENERAL); 508 509 dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n", 510 sig->mode.pixelclock, 511 clk_get_rate(di->clk_ipu), 512 clk_get_rate(di->clk_di), 513 clk == di->clk_di ? "DI" : "IPU", 514 clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4)); 515 } 516 517 /* 518 * This function is called to adjust a video mode to IPU restrictions. 519 * It is meant to be called from drm crtc mode_fixup() methods. 520 */ 521 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode) 522 { 523 u32 diff; 524 525 if (mode->vfront_porch >= 2) 526 return 0; 527 528 diff = 2 - mode->vfront_porch; 529 530 if (mode->vback_porch >= diff) { 531 mode->vfront_porch = 2; 532 mode->vback_porch -= diff; 533 } else if (mode->vsync_len > diff) { 534 mode->vfront_porch = 2; 535 mode->vsync_len = mode->vsync_len - diff; 536 } else { 537 dev_warn(di->ipu->dev, "failed to adjust videomode\n"); 538 return -EINVAL; 539 } 540 541 dev_warn(di->ipu->dev, "videomode adapted for IPU restrictions\n"); 542 return 0; 543 } 544 EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode); 545 546 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) 547 { 548 u32 reg; 549 u32 di_gen, vsync_cnt; 550 u32 div; 551 552 dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n", 553 di->id, sig->mode.hactive, sig->mode.vactive); 554 555 if ((sig->mode.vsync_len == 0) || (sig->mode.hsync_len == 0)) 556 return -EINVAL; 557 558 dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n", 559 clk_get_rate(di->clk_ipu), 560 clk_get_rate(di->clk_di), 561 sig->mode.pixelclock); 562 563 mutex_lock(&di_mutex); 564 565 ipu_di_config_clock(di, sig); 566 567 div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff; 568 div = div / 16; /* Now divider is integer portion */ 569 570 /* Setup pixel clock timing */ 571 /* Down time is half of period */ 572 ipu_di_write(di, (div << 16), DI_BS_CLKGEN1); 573 574 ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1); 575 ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); 576 577 di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT; 578 di_gen |= DI_GEN_DI_VSYNC_EXT; 579 580 if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) { 581 ipu_di_sync_config_interlaced(di, sig); 582 583 /* set y_sel = 1 */ 584 di_gen |= 0x10000000; 585 di_gen |= DI_GEN_POLARITY_5; 586 di_gen |= DI_GEN_POLARITY_8; 587 588 vsync_cnt = 7; 589 590 if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) 591 di_gen |= DI_GEN_POLARITY_3; 592 if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) 593 di_gen |= DI_GEN_POLARITY_2; 594 } else { 595 ipu_di_sync_config_noninterlaced(di, sig, div); 596 597 vsync_cnt = 3; 598 if (di->id == 1) 599 /* 600 * TODO: change only for TVEv2, parallel display 601 * uses pin 2 / 3 602 */ 603 if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3)) 604 vsync_cnt = 6; 605 606 if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) { 607 if (sig->hsync_pin == 2) 608 di_gen |= DI_GEN_POLARITY_2; 609 else if (sig->hsync_pin == 4) 610 di_gen |= DI_GEN_POLARITY_4; 611 else if (sig->hsync_pin == 7) 612 di_gen |= DI_GEN_POLARITY_7; 613 } 614 if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) { 615 if (sig->vsync_pin == 3) 616 di_gen |= DI_GEN_POLARITY_3; 617 else if (sig->vsync_pin == 6) 618 di_gen |= DI_GEN_POLARITY_6; 619 else if (sig->vsync_pin == 8) 620 di_gen |= DI_GEN_POLARITY_8; 621 } 622 } 623 624 if (sig->clk_pol) 625 di_gen |= DI_GEN_POLARITY_DISP_CLK; 626 627 ipu_di_write(di, di_gen, DI_GENERAL); 628 629 ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002, 630 DI_SYNC_AS_GEN); 631 632 reg = ipu_di_read(di, DI_POL); 633 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); 634 635 if (sig->enable_pol) 636 reg |= DI_POL_DRDY_POLARITY_15; 637 if (sig->data_pol) 638 reg |= DI_POL_DRDY_DATA_POLARITY; 639 640 ipu_di_write(di, reg, DI_POL); 641 642 mutex_unlock(&di_mutex); 643 644 return 0; 645 } 646 EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel); 647 648 int ipu_di_enable(struct ipu_di *di) 649 { 650 int ret; 651 652 WARN_ON(IS_ERR(di->clk_di_pixel)); 653 654 ret = clk_prepare_enable(di->clk_di_pixel); 655 if (ret) 656 return ret; 657 658 ipu_module_enable(di->ipu, di->module); 659 660 return 0; 661 } 662 EXPORT_SYMBOL_GPL(ipu_di_enable); 663 664 int ipu_di_disable(struct ipu_di *di) 665 { 666 WARN_ON(IS_ERR(di->clk_di_pixel)); 667 668 ipu_module_disable(di->ipu, di->module); 669 670 clk_disable_unprepare(di->clk_di_pixel); 671 672 return 0; 673 } 674 EXPORT_SYMBOL_GPL(ipu_di_disable); 675 676 int ipu_di_get_num(struct ipu_di *di) 677 { 678 return di->id; 679 } 680 EXPORT_SYMBOL_GPL(ipu_di_get_num); 681 682 static DEFINE_MUTEX(ipu_di_lock); 683 684 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp) 685 { 686 struct ipu_di *di; 687 688 if (disp > 1) 689 return ERR_PTR(-EINVAL); 690 691 di = ipu->di_priv[disp]; 692 693 mutex_lock(&ipu_di_lock); 694 695 if (di->inuse) { 696 di = ERR_PTR(-EBUSY); 697 goto out; 698 } 699 700 di->inuse = true; 701 out: 702 mutex_unlock(&ipu_di_lock); 703 704 return di; 705 } 706 EXPORT_SYMBOL_GPL(ipu_di_get); 707 708 void ipu_di_put(struct ipu_di *di) 709 { 710 mutex_lock(&ipu_di_lock); 711 712 di->inuse = false; 713 714 mutex_unlock(&ipu_di_lock); 715 } 716 EXPORT_SYMBOL_GPL(ipu_di_put); 717 718 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, 719 unsigned long base, 720 u32 module, struct clk *clk_ipu) 721 { 722 struct ipu_di *di; 723 724 if (id > 1) 725 return -ENODEV; 726 727 di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL); 728 if (!di) 729 return -ENOMEM; 730 731 ipu->di_priv[id] = di; 732 733 di->clk_di = devm_clk_get(dev, id ? "di1" : "di0"); 734 if (IS_ERR(di->clk_di)) 735 return PTR_ERR(di->clk_di); 736 737 di->module = module; 738 di->id = id; 739 di->clk_ipu = clk_ipu; 740 di->base = devm_ioremap(dev, base, PAGE_SIZE); 741 if (!di->base) 742 return -ENOMEM; 743 744 ipu_di_write(di, 0x10, DI_BS_CLKGEN0); 745 746 dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n", 747 id, base, di->base); 748 di->inuse = false; 749 di->ipu = ipu; 750 751 return 0; 752 } 753 754 void ipu_di_exit(struct ipu_soc *ipu, int id) 755 { 756 } 757