1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 5 */ 6 #include <linux/module.h> 7 #include <linux/export.h> 8 #include <linux/types.h> 9 #include <linux/reset.h> 10 #include <linux/platform_device.h> 11 #include <linux/err.h> 12 #include <linux/spinlock.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/clk.h> 17 #include <linux/list.h> 18 #include <linux/irq.h> 19 #include <linux/irqchip/chained_irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of.h> 22 #include <linux/of_graph.h> 23 24 #include <drm/drm_fourcc.h> 25 26 #include <video/imx-ipu-v3.h> 27 #include "ipu-prv.h" 28 29 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) 30 { 31 return readl(ipu->cm_reg + offset); 32 } 33 34 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) 35 { 36 writel(value, ipu->cm_reg + offset); 37 } 38 39 int ipu_get_num(struct ipu_soc *ipu) 40 { 41 return ipu->id; 42 } 43 EXPORT_SYMBOL_GPL(ipu_get_num); 44 45 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) 46 { 47 u32 val; 48 49 val = ipu_cm_read(ipu, IPU_SRM_PRI2); 50 val &= ~DP_S_SRM_MODE_MASK; 51 val |= sync ? DP_S_SRM_MODE_NEXT_FRAME : 52 DP_S_SRM_MODE_NOW; 53 ipu_cm_write(ipu, val, IPU_SRM_PRI2); 54 } 55 EXPORT_SYMBOL_GPL(ipu_srm_dp_update); 56 57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) 58 { 59 switch (drm_fourcc) { 60 case DRM_FORMAT_ARGB1555: 61 case DRM_FORMAT_ABGR1555: 62 case DRM_FORMAT_RGBA5551: 63 case DRM_FORMAT_BGRA5551: 64 case DRM_FORMAT_RGB565: 65 case DRM_FORMAT_BGR565: 66 case DRM_FORMAT_RGB888: 67 case DRM_FORMAT_BGR888: 68 case DRM_FORMAT_ARGB4444: 69 case DRM_FORMAT_XRGB8888: 70 case DRM_FORMAT_XBGR8888: 71 case DRM_FORMAT_RGBX8888: 72 case DRM_FORMAT_BGRX8888: 73 case DRM_FORMAT_ARGB8888: 74 case DRM_FORMAT_ABGR8888: 75 case DRM_FORMAT_RGBA8888: 76 case DRM_FORMAT_BGRA8888: 77 case DRM_FORMAT_RGB565_A8: 78 case DRM_FORMAT_BGR565_A8: 79 case DRM_FORMAT_RGB888_A8: 80 case DRM_FORMAT_BGR888_A8: 81 case DRM_FORMAT_RGBX8888_A8: 82 case DRM_FORMAT_BGRX8888_A8: 83 return IPUV3_COLORSPACE_RGB; 84 case DRM_FORMAT_YUYV: 85 case DRM_FORMAT_UYVY: 86 case DRM_FORMAT_YUV420: 87 case DRM_FORMAT_YVU420: 88 case DRM_FORMAT_YUV422: 89 case DRM_FORMAT_YVU422: 90 case DRM_FORMAT_YUV444: 91 case DRM_FORMAT_YVU444: 92 case DRM_FORMAT_NV12: 93 case DRM_FORMAT_NV21: 94 case DRM_FORMAT_NV16: 95 case DRM_FORMAT_NV61: 96 return IPUV3_COLORSPACE_YUV; 97 default: 98 return IPUV3_COLORSPACE_UNKNOWN; 99 } 100 } 101 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); 102 103 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) 104 { 105 switch (pixelformat) { 106 case V4L2_PIX_FMT_YUV420: 107 case V4L2_PIX_FMT_YVU420: 108 case V4L2_PIX_FMT_YUV422P: 109 case V4L2_PIX_FMT_UYVY: 110 case V4L2_PIX_FMT_YUYV: 111 case V4L2_PIX_FMT_NV12: 112 case V4L2_PIX_FMT_NV21: 113 case V4L2_PIX_FMT_NV16: 114 case V4L2_PIX_FMT_NV61: 115 return IPUV3_COLORSPACE_YUV; 116 case V4L2_PIX_FMT_RGB565: 117 case V4L2_PIX_FMT_BGR24: 118 case V4L2_PIX_FMT_RGB24: 119 case V4L2_PIX_FMT_ABGR32: 120 case V4L2_PIX_FMT_XBGR32: 121 case V4L2_PIX_FMT_BGRA32: 122 case V4L2_PIX_FMT_BGRX32: 123 case V4L2_PIX_FMT_RGBA32: 124 case V4L2_PIX_FMT_RGBX32: 125 case V4L2_PIX_FMT_ARGB32: 126 case V4L2_PIX_FMT_XRGB32: 127 case V4L2_PIX_FMT_RGB32: 128 case V4L2_PIX_FMT_BGR32: 129 return IPUV3_COLORSPACE_RGB; 130 default: 131 return IPUV3_COLORSPACE_UNKNOWN; 132 } 133 } 134 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); 135 136 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 137 bool hflip, bool vflip) 138 { 139 u32 r90, vf, hf; 140 141 switch (degrees) { 142 case 0: 143 vf = hf = r90 = 0; 144 break; 145 case 90: 146 vf = hf = 0; 147 r90 = 1; 148 break; 149 case 180: 150 vf = hf = 1; 151 r90 = 0; 152 break; 153 case 270: 154 vf = hf = r90 = 1; 155 break; 156 default: 157 return -EINVAL; 158 } 159 160 hf ^= (u32)hflip; 161 vf ^= (u32)vflip; 162 163 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf); 164 return 0; 165 } 166 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode); 167 168 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) 169 { 170 struct ipuv3_channel *channel; 171 172 dev_dbg(ipu->dev, "%s %d\n", __func__, num); 173 174 if (num > 63) 175 return ERR_PTR(-ENODEV); 176 177 mutex_lock(&ipu->channel_lock); 178 179 list_for_each_entry(channel, &ipu->channels, list) { 180 if (channel->num == num) { 181 channel = ERR_PTR(-EBUSY); 182 goto out; 183 } 184 } 185 186 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 187 if (!channel) { 188 channel = ERR_PTR(-ENOMEM); 189 goto out; 190 } 191 192 channel->num = num; 193 channel->ipu = ipu; 194 list_add(&channel->list, &ipu->channels); 195 196 out: 197 mutex_unlock(&ipu->channel_lock); 198 199 return channel; 200 } 201 EXPORT_SYMBOL_GPL(ipu_idmac_get); 202 203 void ipu_idmac_put(struct ipuv3_channel *channel) 204 { 205 struct ipu_soc *ipu = channel->ipu; 206 207 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); 208 209 mutex_lock(&ipu->channel_lock); 210 211 list_del(&channel->list); 212 kfree(channel); 213 214 mutex_unlock(&ipu->channel_lock); 215 } 216 EXPORT_SYMBOL_GPL(ipu_idmac_put); 217 218 #define idma_mask(ch) (1 << ((ch) & 0x1f)) 219 220 /* 221 * This is an undocumented feature, a write one to a channel bit in 222 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's 223 * internal current buffer pointer so that transfers start from buffer 224 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM 225 * only says these are read-only registers). This operation is required 226 * for channel linking to work correctly, for instance video capture 227 * pipelines that carry out image rotations will fail after the first 228 * streaming unless this function is called for each channel before 229 * re-enabling the channels. 230 */ 231 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel) 232 { 233 struct ipu_soc *ipu = channel->ipu; 234 unsigned int chno = channel->num; 235 236 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); 237 } 238 239 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 240 bool doublebuffer) 241 { 242 struct ipu_soc *ipu = channel->ipu; 243 unsigned long flags; 244 u32 reg; 245 246 spin_lock_irqsave(&ipu->lock, flags); 247 248 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 249 if (doublebuffer) 250 reg |= idma_mask(channel->num); 251 else 252 reg &= ~idma_mask(channel->num); 253 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); 254 255 __ipu_idmac_reset_current_buffer(channel); 256 257 spin_unlock_irqrestore(&ipu->lock, flags); 258 } 259 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); 260 261 static const struct { 262 int chnum; 263 u32 reg; 264 int shift; 265 } idmac_lock_en_info[] = { 266 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, }, 267 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, }, 268 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, }, 269 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, }, 270 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, }, 271 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, }, 272 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, }, 273 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, }, 274 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, }, 275 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, }, 276 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, }, 277 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, }, 278 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, }, 279 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, }, 280 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, }, 281 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, }, 282 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, }, 283 }; 284 285 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts) 286 { 287 struct ipu_soc *ipu = channel->ipu; 288 unsigned long flags; 289 u32 bursts, regval; 290 int i; 291 292 switch (num_bursts) { 293 case 0: 294 case 1: 295 bursts = 0x00; /* locking disabled */ 296 break; 297 case 2: 298 bursts = 0x01; 299 break; 300 case 4: 301 bursts = 0x02; 302 break; 303 case 8: 304 bursts = 0x03; 305 break; 306 default: 307 return -EINVAL; 308 } 309 310 /* 311 * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M / 312 * i.MX53 channel arbitration locking doesn't seem to work properly. 313 * Allow enabling the lock feature on IPUv3H / i.MX6 only. 314 */ 315 if (bursts && ipu->ipu_type != IPUV3H) 316 return -EINVAL; 317 318 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) { 319 if (channel->num == idmac_lock_en_info[i].chnum) 320 break; 321 } 322 if (i >= ARRAY_SIZE(idmac_lock_en_info)) 323 return -EINVAL; 324 325 spin_lock_irqsave(&ipu->lock, flags); 326 327 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); 328 regval &= ~(0x03 << idmac_lock_en_info[i].shift); 329 regval |= (bursts << idmac_lock_en_info[i].shift); 330 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); 331 332 spin_unlock_irqrestore(&ipu->lock, flags); 333 334 return 0; 335 } 336 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable); 337 338 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) 339 { 340 unsigned long lock_flags; 341 u32 val; 342 343 spin_lock_irqsave(&ipu->lock, lock_flags); 344 345 val = ipu_cm_read(ipu, IPU_DISP_GEN); 346 347 if (mask & IPU_CONF_DI0_EN) 348 val |= IPU_DI0_COUNTER_RELEASE; 349 if (mask & IPU_CONF_DI1_EN) 350 val |= IPU_DI1_COUNTER_RELEASE; 351 352 ipu_cm_write(ipu, val, IPU_DISP_GEN); 353 354 val = ipu_cm_read(ipu, IPU_CONF); 355 val |= mask; 356 ipu_cm_write(ipu, val, IPU_CONF); 357 358 spin_unlock_irqrestore(&ipu->lock, lock_flags); 359 360 return 0; 361 } 362 EXPORT_SYMBOL_GPL(ipu_module_enable); 363 364 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) 365 { 366 unsigned long lock_flags; 367 u32 val; 368 369 spin_lock_irqsave(&ipu->lock, lock_flags); 370 371 val = ipu_cm_read(ipu, IPU_CONF); 372 val &= ~mask; 373 ipu_cm_write(ipu, val, IPU_CONF); 374 375 val = ipu_cm_read(ipu, IPU_DISP_GEN); 376 377 if (mask & IPU_CONF_DI0_EN) 378 val &= ~IPU_DI0_COUNTER_RELEASE; 379 if (mask & IPU_CONF_DI1_EN) 380 val &= ~IPU_DI1_COUNTER_RELEASE; 381 382 ipu_cm_write(ipu, val, IPU_DISP_GEN); 383 384 spin_unlock_irqrestore(&ipu->lock, lock_flags); 385 386 return 0; 387 } 388 EXPORT_SYMBOL_GPL(ipu_module_disable); 389 390 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel) 391 { 392 struct ipu_soc *ipu = channel->ipu; 393 unsigned int chno = channel->num; 394 395 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; 396 } 397 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer); 398 399 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num) 400 { 401 struct ipu_soc *ipu = channel->ipu; 402 unsigned long flags; 403 u32 reg = 0; 404 405 spin_lock_irqsave(&ipu->lock, flags); 406 switch (buf_num) { 407 case 0: 408 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); 409 break; 410 case 1: 411 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); 412 break; 413 case 2: 414 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); 415 break; 416 } 417 spin_unlock_irqrestore(&ipu->lock, flags); 418 419 return ((reg & idma_mask(channel->num)) != 0); 420 } 421 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready); 422 423 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) 424 { 425 struct ipu_soc *ipu = channel->ipu; 426 unsigned int chno = channel->num; 427 unsigned long flags; 428 429 spin_lock_irqsave(&ipu->lock, flags); 430 431 /* Mark buffer as ready. */ 432 if (buf_num == 0) 433 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 434 else 435 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 436 437 spin_unlock_irqrestore(&ipu->lock, flags); 438 } 439 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); 440 441 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num) 442 { 443 struct ipu_soc *ipu = channel->ipu; 444 unsigned int chno = channel->num; 445 unsigned long flags; 446 447 spin_lock_irqsave(&ipu->lock, flags); 448 449 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ 450 switch (buf_num) { 451 case 0: 452 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 453 break; 454 case 1: 455 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 456 break; 457 case 2: 458 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); 459 break; 460 default: 461 break; 462 } 463 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 464 465 spin_unlock_irqrestore(&ipu->lock, flags); 466 } 467 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer); 468 469 int ipu_idmac_enable_channel(struct ipuv3_channel *channel) 470 { 471 struct ipu_soc *ipu = channel->ipu; 472 u32 val; 473 unsigned long flags; 474 475 spin_lock_irqsave(&ipu->lock, flags); 476 477 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 478 val |= idma_mask(channel->num); 479 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 480 481 spin_unlock_irqrestore(&ipu->lock, flags); 482 483 return 0; 484 } 485 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); 486 487 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms) 488 { 489 struct ipu_soc *ipu = channel->ipu; 490 unsigned long timeout; 491 492 timeout = jiffies + msecs_to_jiffies(ms); 493 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & 494 idma_mask(channel->num)) { 495 if (time_after(jiffies, timeout)) 496 return -ETIMEDOUT; 497 cpu_relax(); 498 } 499 500 return 0; 501 } 502 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy); 503 504 int ipu_idmac_disable_channel(struct ipuv3_channel *channel) 505 { 506 struct ipu_soc *ipu = channel->ipu; 507 u32 val; 508 unsigned long flags; 509 510 spin_lock_irqsave(&ipu->lock, flags); 511 512 /* Disable DMA channel(s) */ 513 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 514 val &= ~idma_mask(channel->num); 515 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 516 517 __ipu_idmac_reset_current_buffer(channel); 518 519 /* Set channel buffers NOT to be ready */ 520 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ 521 522 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & 523 idma_mask(channel->num)) { 524 ipu_cm_write(ipu, idma_mask(channel->num), 525 IPU_CHA_BUF0_RDY(channel->num)); 526 } 527 528 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & 529 idma_mask(channel->num)) { 530 ipu_cm_write(ipu, idma_mask(channel->num), 531 IPU_CHA_BUF1_RDY(channel->num)); 532 } 533 534 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 535 536 /* Reset the double buffer */ 537 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 538 val &= ~idma_mask(channel->num); 539 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); 540 541 spin_unlock_irqrestore(&ipu->lock, flags); 542 543 return 0; 544 } 545 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); 546 547 /* 548 * The imx6 rev. D TRM says that enabling the WM feature will increase 549 * a channel's priority. Refer to Table 36-8 Calculated priority value. 550 * The sub-module that is the sink or source for the channel must enable 551 * watermark signal for this to take effect (SMFC_WM for instance). 552 */ 553 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable) 554 { 555 struct ipu_soc *ipu = channel->ipu; 556 unsigned long flags; 557 u32 val; 558 559 spin_lock_irqsave(&ipu->lock, flags); 560 561 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); 562 if (enable) 563 val |= 1 << (channel->num % 32); 564 else 565 val &= ~(1 << (channel->num % 32)); 566 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); 567 568 spin_unlock_irqrestore(&ipu->lock, flags); 569 } 570 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark); 571 572 static int ipu_memory_reset(struct ipu_soc *ipu) 573 { 574 unsigned long timeout; 575 576 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); 577 578 timeout = jiffies + msecs_to_jiffies(1000); 579 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { 580 if (time_after(jiffies, timeout)) 581 return -ETIME; 582 cpu_relax(); 583 } 584 585 return 0; 586 } 587 588 /* 589 * Set the source mux for the given CSI. Selects either parallel or 590 * MIPI CSI2 sources. 591 */ 592 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) 593 { 594 unsigned long flags; 595 u32 val, mask; 596 597 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : 598 IPU_CONF_CSI0_DATA_SOURCE; 599 600 spin_lock_irqsave(&ipu->lock, flags); 601 602 val = ipu_cm_read(ipu, IPU_CONF); 603 if (mipi_csi2) 604 val |= mask; 605 else 606 val &= ~mask; 607 ipu_cm_write(ipu, val, IPU_CONF); 608 609 spin_unlock_irqrestore(&ipu->lock, flags); 610 } 611 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux); 612 613 /* 614 * Set the source mux for the IC. Selects either CSI[01] or the VDI. 615 */ 616 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) 617 { 618 unsigned long flags; 619 u32 val; 620 621 spin_lock_irqsave(&ipu->lock, flags); 622 623 val = ipu_cm_read(ipu, IPU_CONF); 624 if (vdi) 625 val |= IPU_CONF_IC_INPUT; 626 else 627 val &= ~IPU_CONF_IC_INPUT; 628 629 if (csi_id == 1) 630 val |= IPU_CONF_CSI_SEL; 631 else 632 val &= ~IPU_CONF_CSI_SEL; 633 634 ipu_cm_write(ipu, val, IPU_CONF); 635 636 spin_unlock_irqrestore(&ipu->lock, flags); 637 } 638 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux); 639 640 641 /* Frame Synchronization Unit Channel Linking */ 642 643 struct fsu_link_reg_info { 644 int chno; 645 u32 reg; 646 u32 mask; 647 u32 val; 648 }; 649 650 struct fsu_link_info { 651 struct fsu_link_reg_info src; 652 struct fsu_link_reg_info sink; 653 }; 654 655 static const struct fsu_link_info fsu_link_info[] = { 656 { 657 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2, 658 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC }, 659 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1, 660 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC }, 661 }, { 662 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2, 663 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF }, 664 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1, 665 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF }, 666 }, { 667 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2, 668 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP }, 669 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1, 670 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP }, 671 }, { 672 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 }, 673 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1, 674 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT }, 675 }, 676 }; 677 678 static const struct fsu_link_info *find_fsu_link_info(int src, int sink) 679 { 680 int i; 681 682 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) { 683 if (src == fsu_link_info[i].src.chno && 684 sink == fsu_link_info[i].sink.chno) 685 return &fsu_link_info[i]; 686 } 687 688 return NULL; 689 } 690 691 /* 692 * Links a source channel to a sink channel in the FSU. 693 */ 694 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) 695 { 696 const struct fsu_link_info *link; 697 u32 src_reg, sink_reg; 698 unsigned long flags; 699 700 link = find_fsu_link_info(src_ch, sink_ch); 701 if (!link) 702 return -EINVAL; 703 704 spin_lock_irqsave(&ipu->lock, flags); 705 706 if (link->src.mask) { 707 src_reg = ipu_cm_read(ipu, link->src.reg); 708 src_reg &= ~link->src.mask; 709 src_reg |= link->src.val; 710 ipu_cm_write(ipu, src_reg, link->src.reg); 711 } 712 713 if (link->sink.mask) { 714 sink_reg = ipu_cm_read(ipu, link->sink.reg); 715 sink_reg &= ~link->sink.mask; 716 sink_reg |= link->sink.val; 717 ipu_cm_write(ipu, sink_reg, link->sink.reg); 718 } 719 720 spin_unlock_irqrestore(&ipu->lock, flags); 721 return 0; 722 } 723 EXPORT_SYMBOL_GPL(ipu_fsu_link); 724 725 /* 726 * Unlinks source and sink channels in the FSU. 727 */ 728 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) 729 { 730 const struct fsu_link_info *link; 731 u32 src_reg, sink_reg; 732 unsigned long flags; 733 734 link = find_fsu_link_info(src_ch, sink_ch); 735 if (!link) 736 return -EINVAL; 737 738 spin_lock_irqsave(&ipu->lock, flags); 739 740 if (link->src.mask) { 741 src_reg = ipu_cm_read(ipu, link->src.reg); 742 src_reg &= ~link->src.mask; 743 ipu_cm_write(ipu, src_reg, link->src.reg); 744 } 745 746 if (link->sink.mask) { 747 sink_reg = ipu_cm_read(ipu, link->sink.reg); 748 sink_reg &= ~link->sink.mask; 749 ipu_cm_write(ipu, sink_reg, link->sink.reg); 750 } 751 752 spin_unlock_irqrestore(&ipu->lock, flags); 753 return 0; 754 } 755 EXPORT_SYMBOL_GPL(ipu_fsu_unlink); 756 757 /* Link IDMAC channels in the FSU */ 758 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink) 759 { 760 return ipu_fsu_link(src->ipu, src->num, sink->num); 761 } 762 EXPORT_SYMBOL_GPL(ipu_idmac_link); 763 764 /* Unlink IDMAC channels in the FSU */ 765 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink) 766 { 767 return ipu_fsu_unlink(src->ipu, src->num, sink->num); 768 } 769 EXPORT_SYMBOL_GPL(ipu_idmac_unlink); 770 771 struct ipu_devtype { 772 const char *name; 773 unsigned long cm_ofs; 774 unsigned long cpmem_ofs; 775 unsigned long srm_ofs; 776 unsigned long tpm_ofs; 777 unsigned long csi0_ofs; 778 unsigned long csi1_ofs; 779 unsigned long ic_ofs; 780 unsigned long disp0_ofs; 781 unsigned long disp1_ofs; 782 unsigned long dc_tmpl_ofs; 783 unsigned long vdi_ofs; 784 enum ipuv3_type type; 785 }; 786 787 static struct ipu_devtype ipu_type_imx51 = { 788 .name = "IPUv3EX", 789 .cm_ofs = 0x1e000000, 790 .cpmem_ofs = 0x1f000000, 791 .srm_ofs = 0x1f040000, 792 .tpm_ofs = 0x1f060000, 793 .csi0_ofs = 0x1e030000, 794 .csi1_ofs = 0x1e038000, 795 .ic_ofs = 0x1e020000, 796 .disp0_ofs = 0x1e040000, 797 .disp1_ofs = 0x1e048000, 798 .dc_tmpl_ofs = 0x1f080000, 799 .vdi_ofs = 0x1e068000, 800 .type = IPUV3EX, 801 }; 802 803 static struct ipu_devtype ipu_type_imx53 = { 804 .name = "IPUv3M", 805 .cm_ofs = 0x06000000, 806 .cpmem_ofs = 0x07000000, 807 .srm_ofs = 0x07040000, 808 .tpm_ofs = 0x07060000, 809 .csi0_ofs = 0x06030000, 810 .csi1_ofs = 0x06038000, 811 .ic_ofs = 0x06020000, 812 .disp0_ofs = 0x06040000, 813 .disp1_ofs = 0x06048000, 814 .dc_tmpl_ofs = 0x07080000, 815 .vdi_ofs = 0x06068000, 816 .type = IPUV3M, 817 }; 818 819 static struct ipu_devtype ipu_type_imx6q = { 820 .name = "IPUv3H", 821 .cm_ofs = 0x00200000, 822 .cpmem_ofs = 0x00300000, 823 .srm_ofs = 0x00340000, 824 .tpm_ofs = 0x00360000, 825 .csi0_ofs = 0x00230000, 826 .csi1_ofs = 0x00238000, 827 .ic_ofs = 0x00220000, 828 .disp0_ofs = 0x00240000, 829 .disp1_ofs = 0x00248000, 830 .dc_tmpl_ofs = 0x00380000, 831 .vdi_ofs = 0x00268000, 832 .type = IPUV3H, 833 }; 834 835 static const struct of_device_id imx_ipu_dt_ids[] = { 836 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, 837 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, 838 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, 839 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, }, 840 { /* sentinel */ } 841 }; 842 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); 843 844 static int ipu_submodules_init(struct ipu_soc *ipu, 845 struct platform_device *pdev, unsigned long ipu_base, 846 struct clk *ipu_clk) 847 { 848 char *unit; 849 int ret; 850 struct device *dev = &pdev->dev; 851 const struct ipu_devtype *devtype = ipu->devtype; 852 853 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); 854 if (ret) { 855 unit = "cpmem"; 856 goto err_cpmem; 857 } 858 859 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, 860 IPU_CONF_CSI0_EN, ipu_clk); 861 if (ret) { 862 unit = "csi0"; 863 goto err_csi_0; 864 } 865 866 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, 867 IPU_CONF_CSI1_EN, ipu_clk); 868 if (ret) { 869 unit = "csi1"; 870 goto err_csi_1; 871 } 872 873 ret = ipu_ic_init(ipu, dev, 874 ipu_base + devtype->ic_ofs, 875 ipu_base + devtype->tpm_ofs); 876 if (ret) { 877 unit = "ic"; 878 goto err_ic; 879 } 880 881 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, 882 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN | 883 IPU_CONF_IC_INPUT); 884 if (ret) { 885 unit = "vdi"; 886 goto err_vdi; 887 } 888 889 ret = ipu_image_convert_init(ipu, dev); 890 if (ret) { 891 unit = "image_convert"; 892 goto err_image_convert; 893 } 894 895 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, 896 IPU_CONF_DI0_EN, ipu_clk); 897 if (ret) { 898 unit = "di0"; 899 goto err_di_0; 900 } 901 902 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, 903 IPU_CONF_DI1_EN, ipu_clk); 904 if (ret) { 905 unit = "di1"; 906 goto err_di_1; 907 } 908 909 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + 910 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); 911 if (ret) { 912 unit = "dc_template"; 913 goto err_dc; 914 } 915 916 ret = ipu_dmfc_init(ipu, dev, ipu_base + 917 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); 918 if (ret) { 919 unit = "dmfc"; 920 goto err_dmfc; 921 } 922 923 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); 924 if (ret) { 925 unit = "dp"; 926 goto err_dp; 927 } 928 929 ret = ipu_smfc_init(ipu, dev, ipu_base + 930 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); 931 if (ret) { 932 unit = "smfc"; 933 goto err_smfc; 934 } 935 936 return 0; 937 938 err_smfc: 939 ipu_dp_exit(ipu); 940 err_dp: 941 ipu_dmfc_exit(ipu); 942 err_dmfc: 943 ipu_dc_exit(ipu); 944 err_dc: 945 ipu_di_exit(ipu, 1); 946 err_di_1: 947 ipu_di_exit(ipu, 0); 948 err_di_0: 949 ipu_image_convert_exit(ipu); 950 err_image_convert: 951 ipu_vdi_exit(ipu); 952 err_vdi: 953 ipu_ic_exit(ipu); 954 err_ic: 955 ipu_csi_exit(ipu, 1); 956 err_csi_1: 957 ipu_csi_exit(ipu, 0); 958 err_csi_0: 959 ipu_cpmem_exit(ipu); 960 err_cpmem: 961 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); 962 return ret; 963 } 964 965 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) 966 { 967 unsigned long status; 968 int i, bit; 969 970 for (i = 0; i < num_regs; i++) { 971 972 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); 973 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); 974 975 for_each_set_bit(bit, &status, 32) 976 generic_handle_domain_irq(ipu->domain, 977 regs[i] * 32 + bit); 978 } 979 } 980 981 static void ipu_irq_handler(struct irq_desc *desc) 982 { 983 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 984 struct irq_chip *chip = irq_desc_get_chip(desc); 985 static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; 986 987 chained_irq_enter(chip, desc); 988 989 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 990 991 chained_irq_exit(chip, desc); 992 } 993 994 static void ipu_err_irq_handler(struct irq_desc *desc) 995 { 996 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 997 struct irq_chip *chip = irq_desc_get_chip(desc); 998 static const int int_reg[] = { 4, 5, 8, 9}; 999 1000 chained_irq_enter(chip, desc); 1001 1002 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 1003 1004 chained_irq_exit(chip, desc); 1005 } 1006 1007 int ipu_map_irq(struct ipu_soc *ipu, int irq) 1008 { 1009 int virq; 1010 1011 virq = irq_linear_revmap(ipu->domain, irq); 1012 if (!virq) 1013 virq = irq_create_mapping(ipu->domain, irq); 1014 1015 return virq; 1016 } 1017 EXPORT_SYMBOL_GPL(ipu_map_irq); 1018 1019 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 1020 enum ipu_channel_irq irq_type) 1021 { 1022 return ipu_map_irq(ipu, irq_type + channel->num); 1023 } 1024 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); 1025 1026 static void ipu_submodules_exit(struct ipu_soc *ipu) 1027 { 1028 ipu_smfc_exit(ipu); 1029 ipu_dp_exit(ipu); 1030 ipu_dmfc_exit(ipu); 1031 ipu_dc_exit(ipu); 1032 ipu_di_exit(ipu, 1); 1033 ipu_di_exit(ipu, 0); 1034 ipu_image_convert_exit(ipu); 1035 ipu_vdi_exit(ipu); 1036 ipu_ic_exit(ipu); 1037 ipu_csi_exit(ipu, 1); 1038 ipu_csi_exit(ipu, 0); 1039 ipu_cpmem_exit(ipu); 1040 } 1041 1042 static int platform_remove_devices_fn(struct device *dev, void *unused) 1043 { 1044 struct platform_device *pdev = to_platform_device(dev); 1045 1046 platform_device_unregister(pdev); 1047 1048 return 0; 1049 } 1050 1051 static void platform_device_unregister_children(struct platform_device *pdev) 1052 { 1053 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); 1054 } 1055 1056 struct ipu_platform_reg { 1057 struct ipu_client_platformdata pdata; 1058 const char *name; 1059 }; 1060 1061 /* These must be in the order of the corresponding device tree port nodes */ 1062 static struct ipu_platform_reg client_reg[] = { 1063 { 1064 .pdata = { 1065 .csi = 0, 1066 .dma[0] = IPUV3_CHANNEL_CSI0, 1067 .dma[1] = -EINVAL, 1068 }, 1069 .name = "imx-ipuv3-csi", 1070 }, { 1071 .pdata = { 1072 .csi = 1, 1073 .dma[0] = IPUV3_CHANNEL_CSI1, 1074 .dma[1] = -EINVAL, 1075 }, 1076 .name = "imx-ipuv3-csi", 1077 }, { 1078 .pdata = { 1079 .di = 0, 1080 .dc = 5, 1081 .dp = IPU_DP_FLOW_SYNC_BG, 1082 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, 1083 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC, 1084 }, 1085 .name = "imx-ipuv3-crtc", 1086 }, { 1087 .pdata = { 1088 .di = 1, 1089 .dc = 1, 1090 .dp = -EINVAL, 1091 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, 1092 .dma[1] = -EINVAL, 1093 }, 1094 .name = "imx-ipuv3-crtc", 1095 }, 1096 }; 1097 1098 static DEFINE_MUTEX(ipu_client_id_mutex); 1099 static int ipu_client_id; 1100 1101 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) 1102 { 1103 struct device *dev = ipu->dev; 1104 unsigned i; 1105 int id, ret; 1106 1107 mutex_lock(&ipu_client_id_mutex); 1108 id = ipu_client_id; 1109 ipu_client_id += ARRAY_SIZE(client_reg); 1110 mutex_unlock(&ipu_client_id_mutex); 1111 1112 for (i = 0; i < ARRAY_SIZE(client_reg); i++) { 1113 struct ipu_platform_reg *reg = &client_reg[i]; 1114 struct platform_device *pdev; 1115 struct device_node *of_node; 1116 1117 /* Associate subdevice with the corresponding port node */ 1118 of_node = of_graph_get_port_by_id(dev->of_node, i); 1119 if (!of_node) { 1120 dev_info(dev, 1121 "no port@%d node in %pOF, not using %s%d\n", 1122 i, dev->of_node, 1123 (i / 2) ? "DI" : "CSI", i % 2); 1124 continue; 1125 } 1126 1127 pdev = platform_device_alloc(reg->name, id++); 1128 if (!pdev) { 1129 ret = -ENOMEM; 1130 of_node_put(of_node); 1131 goto err_register; 1132 } 1133 1134 pdev->dev.parent = dev; 1135 1136 reg->pdata.of_node = of_node; 1137 ret = platform_device_add_data(pdev, ®->pdata, 1138 sizeof(reg->pdata)); 1139 if (!ret) 1140 ret = platform_device_add(pdev); 1141 if (ret) { 1142 platform_device_put(pdev); 1143 goto err_register; 1144 } 1145 } 1146 1147 return 0; 1148 1149 err_register: 1150 platform_device_unregister_children(to_platform_device(dev)); 1151 1152 return ret; 1153 } 1154 1155 1156 static int ipu_irq_init(struct ipu_soc *ipu) 1157 { 1158 struct irq_chip_generic *gc; 1159 struct irq_chip_type *ct; 1160 unsigned long unused[IPU_NUM_IRQS / 32] = { 1161 0x400100d0, 0xffe000fd, 1162 0x400100d0, 0xffe000fd, 1163 0x400100d0, 0xffe000fd, 1164 0x4077ffff, 0xffe7e1fd, 1165 0x23fffffe, 0x8880fff0, 1166 0xf98fe7d0, 0xfff81fff, 1167 0x400100d0, 0xffe000fd, 1168 0x00000000, 1169 }; 1170 int ret, i; 1171 1172 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, 1173 &irq_generic_chip_ops, ipu); 1174 if (!ipu->domain) { 1175 dev_err(ipu->dev, "failed to add irq domain\n"); 1176 return -ENODEV; 1177 } 1178 1179 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", 1180 handle_level_irq, 0, 0, 0); 1181 if (ret < 0) { 1182 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); 1183 irq_domain_remove(ipu->domain); 1184 return ret; 1185 } 1186 1187 /* Mask and clear all interrupts */ 1188 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1189 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); 1190 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); 1191 } 1192 1193 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1194 gc = irq_get_domain_generic_chip(ipu->domain, i); 1195 gc->reg_base = ipu->cm_reg; 1196 gc->unused = unused[i / 32]; 1197 ct = gc->chip_types; 1198 ct->chip.irq_ack = irq_gc_ack_set_bit; 1199 ct->chip.irq_mask = irq_gc_mask_clr_bit; 1200 ct->chip.irq_unmask = irq_gc_mask_set_bit; 1201 ct->regs.ack = IPU_INT_STAT(i / 32); 1202 ct->regs.mask = IPU_INT_CTRL(i / 32); 1203 } 1204 1205 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); 1206 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, 1207 ipu); 1208 1209 return 0; 1210 } 1211 1212 static void ipu_irq_exit(struct ipu_soc *ipu) 1213 { 1214 int i, irq; 1215 1216 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); 1217 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); 1218 1219 /* TODO: remove irq_domain_generic_chips */ 1220 1221 for (i = 0; i < IPU_NUM_IRQS; i++) { 1222 irq = irq_linear_revmap(ipu->domain, i); 1223 if (irq) 1224 irq_dispose_mapping(irq); 1225 } 1226 1227 irq_domain_remove(ipu->domain); 1228 } 1229 1230 void ipu_dump(struct ipu_soc *ipu) 1231 { 1232 int i; 1233 1234 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", 1235 ipu_cm_read(ipu, IPU_CONF)); 1236 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", 1237 ipu_idmac_read(ipu, IDMAC_CONF)); 1238 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", 1239 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); 1240 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", 1241 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); 1242 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", 1243 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); 1244 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", 1245 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); 1246 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", 1247 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); 1248 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", 1249 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); 1250 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", 1251 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); 1252 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", 1253 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); 1254 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", 1255 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); 1256 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", 1257 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); 1258 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", 1259 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); 1260 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", 1261 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); 1262 for (i = 0; i < 15; i++) 1263 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, 1264 ipu_cm_read(ipu, IPU_INT_CTRL(i))); 1265 } 1266 EXPORT_SYMBOL_GPL(ipu_dump); 1267 1268 static int ipu_probe(struct platform_device *pdev) 1269 { 1270 struct device_node *np = pdev->dev.of_node; 1271 struct ipu_soc *ipu; 1272 struct resource *res; 1273 unsigned long ipu_base; 1274 int ret, irq_sync, irq_err; 1275 const struct ipu_devtype *devtype; 1276 1277 devtype = of_device_get_match_data(&pdev->dev); 1278 if (!devtype) 1279 return -EINVAL; 1280 1281 irq_sync = platform_get_irq(pdev, 0); 1282 irq_err = platform_get_irq(pdev, 1); 1283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1284 1285 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", 1286 irq_sync, irq_err); 1287 1288 if (!res || irq_sync < 0 || irq_err < 0) 1289 return -ENODEV; 1290 1291 ipu_base = res->start; 1292 1293 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); 1294 if (!ipu) 1295 return -ENODEV; 1296 1297 ipu->id = of_alias_get_id(np, "ipu"); 1298 if (ipu->id < 0) 1299 ipu->id = 0; 1300 1301 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && 1302 IS_ENABLED(CONFIG_DRM)) { 1303 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, 1304 "fsl,prg", ipu->id); 1305 if (!ipu->prg_priv) 1306 return -EPROBE_DEFER; 1307 } 1308 1309 ipu->devtype = devtype; 1310 ipu->ipu_type = devtype->type; 1311 1312 spin_lock_init(&ipu->lock); 1313 mutex_init(&ipu->channel_lock); 1314 INIT_LIST_HEAD(&ipu->channels); 1315 1316 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", 1317 ipu_base + devtype->cm_ofs); 1318 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", 1319 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); 1320 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", 1321 ipu_base + devtype->cpmem_ofs); 1322 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", 1323 ipu_base + devtype->csi0_ofs); 1324 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", 1325 ipu_base + devtype->csi1_ofs); 1326 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1327 ipu_base + devtype->ic_ofs); 1328 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", 1329 ipu_base + devtype->disp0_ofs); 1330 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", 1331 ipu_base + devtype->disp1_ofs); 1332 dev_dbg(&pdev->dev, "srm: 0x%08lx\n", 1333 ipu_base + devtype->srm_ofs); 1334 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", 1335 ipu_base + devtype->tpm_ofs); 1336 dev_dbg(&pdev->dev, "dc: 0x%08lx\n", 1337 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); 1338 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1339 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); 1340 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", 1341 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); 1342 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", 1343 ipu_base + devtype->vdi_ofs); 1344 1345 ipu->cm_reg = devm_ioremap(&pdev->dev, 1346 ipu_base + devtype->cm_ofs, PAGE_SIZE); 1347 ipu->idmac_reg = devm_ioremap(&pdev->dev, 1348 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, 1349 PAGE_SIZE); 1350 1351 if (!ipu->cm_reg || !ipu->idmac_reg) 1352 return -ENOMEM; 1353 1354 ipu->clk = devm_clk_get(&pdev->dev, "bus"); 1355 if (IS_ERR(ipu->clk)) { 1356 ret = PTR_ERR(ipu->clk); 1357 dev_err(&pdev->dev, "clk_get failed with %d", ret); 1358 return ret; 1359 } 1360 1361 platform_set_drvdata(pdev, ipu); 1362 1363 ret = clk_prepare_enable(ipu->clk); 1364 if (ret) { 1365 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1366 return ret; 1367 } 1368 1369 ipu->dev = &pdev->dev; 1370 ipu->irq_sync = irq_sync; 1371 ipu->irq_err = irq_err; 1372 1373 ret = device_reset(&pdev->dev); 1374 if (ret) { 1375 dev_err(&pdev->dev, "failed to reset: %d\n", ret); 1376 goto out_failed_reset; 1377 } 1378 ret = ipu_memory_reset(ipu); 1379 if (ret) 1380 goto out_failed_reset; 1381 1382 ret = ipu_irq_init(ipu); 1383 if (ret) 1384 goto out_failed_irq; 1385 1386 /* Set MCU_T to divide MCU access window into 2 */ 1387 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), 1388 IPU_DISP_GEN); 1389 1390 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); 1391 if (ret) 1392 goto failed_submodules_init; 1393 1394 ret = ipu_add_client_devices(ipu, ipu_base); 1395 if (ret) { 1396 dev_err(&pdev->dev, "adding client devices failed with %d\n", 1397 ret); 1398 goto failed_add_clients; 1399 } 1400 1401 dev_info(&pdev->dev, "%s probed\n", devtype->name); 1402 1403 return 0; 1404 1405 failed_add_clients: 1406 ipu_submodules_exit(ipu); 1407 failed_submodules_init: 1408 ipu_irq_exit(ipu); 1409 out_failed_irq: 1410 out_failed_reset: 1411 clk_disable_unprepare(ipu->clk); 1412 return ret; 1413 } 1414 1415 static void ipu_remove(struct platform_device *pdev) 1416 { 1417 struct ipu_soc *ipu = platform_get_drvdata(pdev); 1418 1419 platform_device_unregister_children(pdev); 1420 ipu_submodules_exit(ipu); 1421 ipu_irq_exit(ipu); 1422 1423 clk_disable_unprepare(ipu->clk); 1424 } 1425 1426 static struct platform_driver imx_ipu_driver = { 1427 .driver = { 1428 .name = "imx-ipuv3", 1429 .of_match_table = imx_ipu_dt_ids, 1430 }, 1431 .probe = ipu_probe, 1432 .remove = ipu_remove, 1433 }; 1434 1435 static struct platform_driver * const drivers[] = { 1436 #if IS_ENABLED(CONFIG_DRM) 1437 &ipu_pre_drv, 1438 &ipu_prg_drv, 1439 #endif 1440 &imx_ipu_driver, 1441 }; 1442 1443 static int __init imx_ipu_init(void) 1444 { 1445 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 1446 } 1447 module_init(imx_ipu_init); 1448 1449 static void __exit imx_ipu_exit(void) 1450 { 1451 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 1452 } 1453 module_exit(imx_ipu_exit); 1454 1455 MODULE_ALIAS("platform:imx-ipuv3"); 1456 MODULE_DESCRIPTION("i.MX IPU v3 driver"); 1457 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 1458 MODULE_LICENSE("GPL"); 1459