1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 NVIDIA Corporation. 4 */ 5 6 #define HOST1X_CHANNEL_DMASTART 0x0000 7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004 8 #define HOST1X_CHANNEL_DMAPUT 0x0008 9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c 10 #define HOST1X_CHANNEL_DMAGET 0x0010 11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014 12 #define HOST1X_CHANNEL_DMAEND 0x0018 13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c 14 #define HOST1X_CHANNEL_DMACTRL 0x0020 15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0) 16 #define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1) 17 #define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2) 18 #define HOST1X_CHANNEL_CMDFIFO_STAT 0x0024 19 #define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13) 20 #define HOST1X_CHANNEL_CMDFIFO_RDATA 0x0028 21 #define HOST1X_CHANNEL_CMDP_OFFSET 0x0030 22 #define HOST1X_CHANNEL_CMDP_CLASS 0x0034 23 #define HOST1X_CHANNEL_CHANNELSTAT 0x0038 24 #define HOST1X_CHANNEL_CMDPROC_STOP 0x0048 25 #define HOST1X_CHANNEL_TEARDOWN 0x004c 26 27 #define HOST1X_SYNC_SYNCPT_CPU_INCR(x) (0x6400 + 4*(x)) 28 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x) (0x6464 + 4*(x)) 29 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x) (0x652c + 4*(x)) 30 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x) (0x6590 + 4*(x)) 31 #define HOST1X_SYNC_SYNCPT_BASE(x) (0x8000 + 4*(x)) 32 #define HOST1X_SYNC_SYNCPT(x) (0x8080 + 4*(x)) 33 #define HOST1X_SYNC_SYNCPT_INT_THRESH(x) (0x8a00 + 4*(x)) 34 #define HOST1X_SYNC_SYNCPT_CH_APP(x) (0x9384 + 4*(x)) 35 #define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8) 36