1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015 NVIDIA Corporation. 4 */ 5 6 /* 7 * Function naming determines intended use: 8 * 9 * <x>_r(void) : Returns the offset for register <x>. 10 * 11 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. 12 * 13 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. 14 * 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted 16 * and masked to place it at field <y> of register <x>. This value 17 * can be |'d with others to produce a full register value for 18 * register <x>. 19 * 20 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This 21 * value can be ~'d and then &'d to clear the value of field <y> for 22 * register <x>. 23 * 24 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted 25 * to place it at field <y> of register <x>. This value can be |'d 26 * with others to produce a full register value for <x>. 27 * 28 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register 29 * <x> value 'r' after being shifted to place its LSB at bit 0. 30 * This value is suitable for direct comparison with other unshifted 31 * values appropriate for use in field <y> of register <x>. 32 * 33 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for 34 * field <y> of register <x>. This value is suitable for direct 35 * comparison with unshifted values appropriate for use in field <y> 36 * of register <x>. 37 */ 38 39 #ifndef HOST1X_HW_HOST1X05_SYNC_H 40 #define HOST1X_HW_HOST1X05_SYNC_H 41 42 #define REGISTER_STRIDE 4 43 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) 45 { 46 return 0xf80 + id * REGISTER_STRIDE; 47 } 48 #define HOST1X_SYNC_SYNCPT(id) \ 49 host1x_sync_syncpt_r(id) 50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) 51 { 52 return 0xe80 + id * REGISTER_STRIDE; 53 } 54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ 55 host1x_sync_syncpt_thresh_cpu0_int_status_r(id) 56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) 57 { 58 return 0xf00 + id * REGISTER_STRIDE; 59 } 60 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ 61 host1x_sync_syncpt_thresh_int_disable_r(id) 62 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) 63 { 64 return 0xf20 + id * REGISTER_STRIDE; 65 } 66 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ 67 host1x_sync_syncpt_thresh_int_enable_cpu0_r(id) 68 static inline u32 host1x_sync_cf_setup_r(unsigned int channel) 69 { 70 return 0xc00 + channel * REGISTER_STRIDE; 71 } 72 #define HOST1X_SYNC_CF_SETUP(channel) \ 73 host1x_sync_cf_setup_r(channel) 74 static inline u32 host1x_sync_cf_setup_base_v(u32 r) 75 { 76 return (r >> 0) & 0x3ff; 77 } 78 #define HOST1X_SYNC_CF_SETUP_BASE_V(r) \ 79 host1x_sync_cf_setup_base_v(r) 80 static inline u32 host1x_sync_cf_setup_limit_v(u32 r) 81 { 82 return (r >> 16) & 0x3ff; 83 } 84 #define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \ 85 host1x_sync_cf_setup_limit_v(r) 86 static inline u32 host1x_sync_cmdproc_stop_r(void) 87 { 88 return 0xac; 89 } 90 #define HOST1X_SYNC_CMDPROC_STOP \ 91 host1x_sync_cmdproc_stop_r() 92 static inline u32 host1x_sync_ch_teardown_r(void) 93 { 94 return 0xb0; 95 } 96 #define HOST1X_SYNC_CH_TEARDOWN \ 97 host1x_sync_ch_teardown_r() 98 static inline u32 host1x_sync_usec_clk_r(void) 99 { 100 return 0x1a4; 101 } 102 #define HOST1X_SYNC_USEC_CLK \ 103 host1x_sync_usec_clk_r() 104 static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void) 105 { 106 return 0x1a8; 107 } 108 #define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \ 109 host1x_sync_ctxsw_timeout_cfg_r() 110 static inline u32 host1x_sync_ip_busy_timeout_r(void) 111 { 112 return 0x1bc; 113 } 114 #define HOST1X_SYNC_IP_BUSY_TIMEOUT \ 115 host1x_sync_ip_busy_timeout_r() 116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id) 117 { 118 return 0x340 + id * REGISTER_STRIDE; 119 } 120 #define HOST1X_SYNC_MLOCK_OWNER(id) \ 121 host1x_sync_mlock_owner_r(id) 122 static inline u32 host1x_sync_mlock_owner_chid_v(u32 r) 123 { 124 return (r >> 8) & 0xf; 125 } 126 #define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \ 127 host1x_sync_mlock_owner_chid_v(v) 128 static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r) 129 { 130 return (r >> 1) & 0x1; 131 } 132 #define HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(r) \ 133 host1x_sync_mlock_owner_cpu_owns_v(r) 134 static inline u32 host1x_sync_mlock_owner_ch_owns_v(u32 r) 135 { 136 return (r >> 0) & 0x1; 137 } 138 #define HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(r) \ 139 host1x_sync_mlock_owner_ch_owns_v(r) 140 static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id) 141 { 142 return 0x1380 + id * REGISTER_STRIDE; 143 } 144 #define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \ 145 host1x_sync_syncpt_int_thresh_r(id) 146 static inline u32 host1x_sync_syncpt_base_r(unsigned int id) 147 { 148 return 0x600 + id * REGISTER_STRIDE; 149 } 150 #define HOST1X_SYNC_SYNCPT_BASE(id) \ 151 host1x_sync_syncpt_base_r(id) 152 static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id) 153 { 154 return 0xf60 + id * REGISTER_STRIDE; 155 } 156 #define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \ 157 host1x_sync_syncpt_cpu_incr_r(id) 158 static inline u32 host1x_sync_cbread_r(unsigned int channel) 159 { 160 return 0xc80 + channel * REGISTER_STRIDE; 161 } 162 #define HOST1X_SYNC_CBREAD(channel) \ 163 host1x_sync_cbread_r(channel) 164 static inline u32 host1x_sync_cfpeek_ctrl_r(void) 165 { 166 return 0x74c; 167 } 168 #define HOST1X_SYNC_CFPEEK_CTRL \ 169 host1x_sync_cfpeek_ctrl_r() 170 static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v) 171 { 172 return (v & 0x3ff) << 0; 173 } 174 #define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \ 175 host1x_sync_cfpeek_ctrl_addr_f(v) 176 static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v) 177 { 178 return (v & 0xf) << 16; 179 } 180 #define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \ 181 host1x_sync_cfpeek_ctrl_channr_f(v) 182 static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v) 183 { 184 return (v & 0x1) << 31; 185 } 186 #define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \ 187 host1x_sync_cfpeek_ctrl_ena_f(v) 188 static inline u32 host1x_sync_cfpeek_read_r(void) 189 { 190 return 0x750; 191 } 192 #define HOST1X_SYNC_CFPEEK_READ \ 193 host1x_sync_cfpeek_read_r() 194 static inline u32 host1x_sync_cfpeek_ptrs_r(void) 195 { 196 return 0x754; 197 } 198 #define HOST1X_SYNC_CFPEEK_PTRS \ 199 host1x_sync_cfpeek_ptrs_r() 200 static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r) 201 { 202 return (r >> 0) & 0x3ff; 203 } 204 #define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \ 205 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r) 206 static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r) 207 { 208 return (r >> 16) & 0x3ff; 209 } 210 #define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \ 211 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r) 212 static inline u32 host1x_sync_cbstat_r(unsigned int channel) 213 { 214 return 0xcc0 + channel * REGISTER_STRIDE; 215 } 216 #define HOST1X_SYNC_CBSTAT(channel) \ 217 host1x_sync_cbstat_r(channel) 218 static inline u32 host1x_sync_cbstat_cboffset_v(u32 r) 219 { 220 return (r >> 0) & 0xffff; 221 } 222 #define HOST1X_SYNC_CBSTAT_CBOFFSET_V(r) \ 223 host1x_sync_cbstat_cboffset_v(r) 224 static inline u32 host1x_sync_cbstat_cbclass_v(u32 r) 225 { 226 return (r >> 16) & 0x3ff; 227 } 228 #define HOST1X_SYNC_CBSTAT_CBCLASS_V(r) \ 229 host1x_sync_cbstat_cbclass_v(r) 230 231 #endif 232