1 /* 2 * Copyright (c) 2013 NVIDIA Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 * 16 */ 17 18 /* 19 * Function naming determines intended use: 20 * 21 * <x>_r(void) : Returns the offset for register <x>. 22 * 23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. 24 * 25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. 26 * 27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted 28 * and masked to place it at field <y> of register <x>. This value 29 * can be |'d with others to produce a full register value for 30 * register <x>. 31 * 32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This 33 * value can be ~'d and then &'d to clear the value of field <y> for 34 * register <x>. 35 * 36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted 37 * to place it at field <y> of register <x>. This value can be |'d 38 * with others to produce a full register value for <x>. 39 * 40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register 41 * <x> value 'r' after being shifted to place its LSB at bit 0. 42 * This value is suitable for direct comparison with other unshifted 43 * values appropriate for use in field <y> of register <x>. 44 * 45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for 46 * field <y> of register <x>. This value is suitable for direct 47 * comparison with unshifted values appropriate for use in field <y> 48 * of register <x>. 49 */ 50 51 #ifndef HOST1X_HW_HOST1X04_CHANNEL_H 52 #define HOST1X_HW_HOST1X04_CHANNEL_H 53 54 static inline u32 host1x_channel_fifostat_r(void) 55 { 56 return 0x0; 57 } 58 #define HOST1X_CHANNEL_FIFOSTAT \ 59 host1x_channel_fifostat_r() 60 static inline u32 host1x_channel_fifostat_cfempty_v(u32 r) 61 { 62 return (r >> 11) & 0x1; 63 } 64 #define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \ 65 host1x_channel_fifostat_cfempty_v(r) 66 static inline u32 host1x_channel_dmastart_r(void) 67 { 68 return 0x14; 69 } 70 #define HOST1X_CHANNEL_DMASTART \ 71 host1x_channel_dmastart_r() 72 static inline u32 host1x_channel_dmaput_r(void) 73 { 74 return 0x18; 75 } 76 #define HOST1X_CHANNEL_DMAPUT \ 77 host1x_channel_dmaput_r() 78 static inline u32 host1x_channel_dmaget_r(void) 79 { 80 return 0x1c; 81 } 82 #define HOST1X_CHANNEL_DMAGET \ 83 host1x_channel_dmaget_r() 84 static inline u32 host1x_channel_dmaend_r(void) 85 { 86 return 0x20; 87 } 88 #define HOST1X_CHANNEL_DMAEND \ 89 host1x_channel_dmaend_r() 90 static inline u32 host1x_channel_dmactrl_r(void) 91 { 92 return 0x24; 93 } 94 #define HOST1X_CHANNEL_DMACTRL \ 95 host1x_channel_dmactrl_r() 96 static inline u32 host1x_channel_dmactrl_dmastop(void) 97 { 98 return 1 << 0; 99 } 100 #define HOST1X_CHANNEL_DMACTRL_DMASTOP \ 101 host1x_channel_dmactrl_dmastop() 102 static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r) 103 { 104 return (r >> 0) & 0x1; 105 } 106 #define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \ 107 host1x_channel_dmactrl_dmastop_v(r) 108 static inline u32 host1x_channel_dmactrl_dmagetrst(void) 109 { 110 return 1 << 1; 111 } 112 #define HOST1X_CHANNEL_DMACTRL_DMAGETRST \ 113 host1x_channel_dmactrl_dmagetrst() 114 static inline u32 host1x_channel_dmactrl_dmainitget(void) 115 { 116 return 1 << 2; 117 } 118 #define HOST1X_CHANNEL_DMACTRL_DMAINITGET \ 119 host1x_channel_dmactrl_dmainitget() 120 121 #endif 122