1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x Channel 4 * 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 6 */ 7 8 #include <linux/host1x.h> 9 #include <linux/iommu.h> 10 #include <linux/slab.h> 11 12 #include <trace/events/host1x.h> 13 14 #include "../channel.h" 15 #include "../dev.h" 16 #include "../intr.h" 17 #include "../job.h" 18 19 #define TRACE_MAX_LENGTH 128U 20 21 static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo, 22 u32 offset, u32 words) 23 { 24 struct device *dev = cdma_to_channel(cdma)->dev; 25 void *mem = NULL; 26 27 if (host1x_debug_trace_cmdbuf) 28 mem = host1x_bo_mmap(bo); 29 30 if (mem) { 31 u32 i; 32 /* 33 * Write in batches of 128 as there seems to be a limit 34 * of how much you can output to ftrace at once. 35 */ 36 for (i = 0; i < words; i += TRACE_MAX_LENGTH) { 37 u32 num_words = min(words - i, TRACE_MAX_LENGTH); 38 39 trace_host1x_cdma_push_gather(dev_name(dev), bo, 40 num_words, 41 offset + i * sizeof(u32), 42 mem); 43 } 44 45 host1x_bo_munmap(bo, mem); 46 } 47 } 48 49 static void submit_wait(struct host1x_job *job, u32 id, u32 threshold) 50 { 51 struct host1x_cdma *cdma = &job->channel->cdma; 52 53 #if HOST1X_HW >= 2 54 host1x_cdma_push_wide(cdma, 55 host1x_opcode_setclass( 56 HOST1X_CLASS_HOST1X, 57 HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32, 58 /* WAIT_SYNCPT_32 is at SYNCPT_PAYLOAD_32+2 */ 59 BIT(0) | BIT(2) 60 ), 61 threshold, 62 id, 63 HOST1X_OPCODE_NOP 64 ); 65 #else 66 /* TODO add waitchk or use waitbases or other mitigation */ 67 host1x_cdma_push(cdma, 68 host1x_opcode_setclass( 69 HOST1X_CLASS_HOST1X, 70 host1x_uclass_wait_syncpt_r(), 71 BIT(0) 72 ), 73 host1x_class_host_wait_syncpt(id, threshold) 74 ); 75 #endif 76 } 77 78 static void submit_setclass(struct host1x_job *job, u32 next_class) 79 { 80 struct host1x_cdma *cdma = &job->channel->cdma; 81 82 #if HOST1X_HW >= 6 83 u32 stream_id; 84 85 /* 86 * If a memory context has been set, use it. Otherwise 87 * (if context isolation is disabled) use the engine's 88 * firmware stream ID. 89 */ 90 if (job->memory_context) 91 stream_id = job->memory_context->stream_id; 92 else 93 stream_id = job->engine_fallback_streamid; 94 95 host1x_cdma_push_wide(cdma, 96 host1x_opcode_setclass(next_class, 0, 0), 97 host1x_opcode_setpayload(stream_id), 98 host1x_opcode_setstreamid(job->engine_streamid_offset / 4), 99 HOST1X_OPCODE_NOP); 100 #else 101 host1x_cdma_push(cdma, 102 host1x_opcode_setclass(next_class, 0, 0), 103 HOST1X_OPCODE_NOP 104 ); 105 #endif 106 } 107 108 static void submit_gathers(struct host1x_job *job, struct host1x_job_cmd *cmds, u32 num_cmds, 109 u32 job_syncpt_base) 110 { 111 struct host1x_cdma *cdma = &job->channel->cdma; 112 #if HOST1X_HW < 6 113 struct device *dev = job->channel->dev; 114 #endif 115 unsigned int i; 116 u32 threshold; 117 118 for (i = 0; i < num_cmds; i++) { 119 struct host1x_job_cmd *cmd = &cmds[i]; 120 121 if (cmd->is_wait) { 122 if (cmd->wait.relative) 123 threshold = job_syncpt_base + cmd->wait.threshold; 124 else 125 threshold = cmd->wait.threshold; 126 127 submit_wait(job, cmd->wait.id, threshold); 128 submit_setclass(job, cmd->wait.next_class); 129 } else { 130 struct host1x_job_gather *g = &cmd->gather; 131 132 dma_addr_t addr = g->base + g->offset; 133 u32 op2, op3; 134 135 op2 = lower_32_bits(addr); 136 op3 = upper_32_bits(addr); 137 138 trace_write_gather(cdma, g->bo, g->offset, g->words); 139 140 if (op3 != 0) { 141 #if HOST1X_HW >= 6 142 u32 op1 = host1x_opcode_gather_wide(g->words); 143 u32 op4 = HOST1X_OPCODE_NOP; 144 145 host1x_cdma_push_wide(cdma, op1, op2, op3, op4); 146 #else 147 dev_err(dev, "invalid gather for push buffer %pad\n", 148 &addr); 149 continue; 150 #endif 151 } else { 152 u32 op1 = host1x_opcode_gather(g->words); 153 154 host1x_cdma_push(cdma, op1, op2); 155 } 156 } 157 } 158 } 159 160 static inline void synchronize_syncpt_base(struct host1x_job *job) 161 { 162 struct host1x_syncpt *sp = job->syncpt; 163 unsigned int id; 164 u32 value; 165 166 value = host1x_syncpt_read_max(sp); 167 id = sp->base->id; 168 169 host1x_cdma_push(&job->channel->cdma, 170 host1x_opcode_setclass(HOST1X_CLASS_HOST1X, 171 HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1), 172 HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(id) | 173 HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value)); 174 } 175 176 static void host1x_channel_set_streamid(struct host1x_channel *channel) 177 { 178 #if HOST1X_HW >= 6 179 u32 stream_id; 180 181 if (!tegra_dev_iommu_get_stream_id(channel->dev->parent, &stream_id)) 182 stream_id = TEGRA_STREAM_ID_BYPASS; 183 184 host1x_ch_writel(channel, stream_id, HOST1X_CHANNEL_SMMU_STREAMID); 185 #endif 186 } 187 188 static void host1x_enable_gather_filter(struct host1x_channel *ch) 189 { 190 #if HOST1X_HW >= 6 191 struct host1x *host = dev_get_drvdata(ch->dev->parent); 192 u32 val; 193 194 if (!host->hv_regs) 195 return; 196 197 val = host1x_hypervisor_readl( 198 host, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); 199 val |= BIT(ch->id % 32); 200 host1x_hypervisor_writel( 201 host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); 202 #elif HOST1X_HW >= 4 203 host1x_ch_writel(ch, 204 HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(1), 205 HOST1X_CHANNEL_CHANNELCTRL); 206 #endif 207 } 208 209 static void channel_program_cdma(struct host1x_job *job) 210 { 211 struct host1x_cdma *cdma = &job->channel->cdma; 212 struct host1x_syncpt *sp = job->syncpt; 213 214 #if HOST1X_HW >= 6 215 u32 fence; 216 int i = 0; 217 218 if (job->num_cmds == 0) 219 goto prefences_done; 220 if (!job->cmds[0].is_wait || job->cmds[0].wait.relative) 221 goto prefences_done; 222 223 /* Enter host1x class with invalid stream ID for prefence waits. */ 224 host1x_cdma_push_wide(cdma, 225 host1x_opcode_acquire_mlock(1), 226 host1x_opcode_setclass(1, 0, 0), 227 host1x_opcode_setpayload(0), 228 host1x_opcode_setstreamid(0x1fffff)); 229 230 for (i = 0; i < job->num_cmds; i++) { 231 struct host1x_job_cmd *cmd = &job->cmds[i]; 232 233 if (!cmd->is_wait || cmd->wait.relative) 234 break; 235 236 submit_wait(job, cmd->wait.id, cmd->wait.threshold); 237 } 238 239 host1x_cdma_push(cdma, 240 HOST1X_OPCODE_NOP, 241 host1x_opcode_release_mlock(1)); 242 243 prefences_done: 244 /* Enter engine class with invalid stream ID. */ 245 host1x_cdma_push_wide(cdma, 246 host1x_opcode_acquire_mlock(job->class), 247 host1x_opcode_setclass(job->class, 0, 0), 248 host1x_opcode_setpayload(0), 249 host1x_opcode_setstreamid(job->engine_streamid_offset / 4)); 250 251 /* Before switching stream ID to real stream ID, ensure engine is idle. */ 252 fence = host1x_syncpt_incr_max(sp, 1); 253 host1x_cdma_push(&job->channel->cdma, 254 host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1), 255 HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) | 256 HOST1X_UCLASS_INCR_SYNCPT_COND_F(4)); 257 submit_wait(job, job->syncpt->id, fence); 258 submit_setclass(job, job->class); 259 260 /* Submit work. */ 261 job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs); 262 submit_gathers(job, job->cmds + i, job->num_cmds - i, job->syncpt_end - job->syncpt_incrs); 263 264 /* Before releasing MLOCK, ensure engine is idle again. */ 265 fence = host1x_syncpt_incr_max(sp, 1); 266 host1x_cdma_push(&job->channel->cdma, 267 host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1), 268 HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) | 269 HOST1X_UCLASS_INCR_SYNCPT_COND_F(4)); 270 submit_wait(job, job->syncpt->id, fence); 271 272 /* Release MLOCK. */ 273 host1x_cdma_push(cdma, 274 HOST1X_OPCODE_NOP, host1x_opcode_release_mlock(job->class)); 275 #else 276 if (job->serialize) { 277 /* 278 * Force serialization by inserting a host wait for the 279 * previous job to finish before this one can commence. 280 */ 281 host1x_cdma_push(cdma, 282 host1x_opcode_setclass(HOST1X_CLASS_HOST1X, 283 host1x_uclass_wait_syncpt_r(), 1), 284 host1x_class_host_wait_syncpt(job->syncpt->id, 285 host1x_syncpt_read_max(sp))); 286 } 287 288 /* Synchronize base register to allow using it for relative waiting */ 289 if (sp->base) 290 synchronize_syncpt_base(job); 291 292 /* add a setclass for modules that require it */ 293 if (job->class) 294 host1x_cdma_push(cdma, 295 host1x_opcode_setclass(job->class, 0, 0), 296 HOST1X_OPCODE_NOP); 297 298 job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs); 299 300 submit_gathers(job, job->cmds, job->num_cmds, job->syncpt_end - job->syncpt_incrs); 301 #endif 302 } 303 304 static void job_complete_callback(struct dma_fence *fence, struct dma_fence_cb *cb) 305 { 306 struct host1x_job *job = container_of(cb, struct host1x_job, fence_cb); 307 308 /* Schedules CDMA update. */ 309 host1x_cdma_update(&job->channel->cdma); 310 } 311 312 static int channel_submit(struct host1x_job *job) 313 { 314 struct host1x_channel *ch = job->channel; 315 struct host1x_syncpt *sp = job->syncpt; 316 u32 prev_max = 0; 317 u32 syncval; 318 int err; 319 struct host1x *host = dev_get_drvdata(ch->dev->parent); 320 321 trace_host1x_channel_submit(dev_name(ch->dev), 322 job->num_cmds, job->num_relocs, 323 job->syncpt->id, job->syncpt_incrs); 324 325 /* before error checks, return current max */ 326 prev_max = job->syncpt_end = host1x_syncpt_read_max(sp); 327 328 /* get submit lock */ 329 err = mutex_lock_interruptible(&ch->submitlock); 330 if (err) 331 return err; 332 333 host1x_channel_set_streamid(ch); 334 host1x_enable_gather_filter(ch); 335 host1x_hw_syncpt_assign_to_channel(host, sp, ch); 336 337 /* begin a CDMA submit */ 338 err = host1x_cdma_begin(&ch->cdma, job); 339 if (err) { 340 mutex_unlock(&ch->submitlock); 341 return err; 342 } 343 344 channel_program_cdma(job); 345 syncval = host1x_syncpt_read_max(sp); 346 347 /* 348 * Create fence before submitting job to HW to avoid job completing 349 * before the fence is set up. 350 */ 351 job->fence = host1x_fence_create(sp, syncval, true); 352 if (WARN(IS_ERR(job->fence), "Failed to create submit complete fence")) { 353 job->fence = NULL; 354 } else { 355 err = dma_fence_add_callback(job->fence, &job->fence_cb, 356 job_complete_callback); 357 } 358 359 /* end CDMA submit & stash pinned hMems into sync queue */ 360 host1x_cdma_end(&ch->cdma, job); 361 362 trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, syncval); 363 364 mutex_unlock(&ch->submitlock); 365 366 if (err == -ENOENT) 367 host1x_cdma_update(&ch->cdma); 368 else 369 WARN(err, "Failed to set submit complete interrupt"); 370 371 return 0; 372 } 373 374 static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev, 375 unsigned int index) 376 { 377 #if HOST1X_HW < 6 378 ch->regs = dev->regs + index * 0x4000; 379 #else 380 ch->regs = dev->regs + index * 0x100; 381 #endif 382 return 0; 383 } 384 385 static const struct host1x_channel_ops host1x_channel_ops = { 386 .init = host1x_channel_init, 387 .submit = channel_submit, 388 }; 389