1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x Channel 4 * 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 6 */ 7 8 #include <linux/host1x.h> 9 #include <linux/iommu.h> 10 #include <linux/overflow.h> 11 #include <linux/slab.h> 12 13 #include <trace/events/host1x.h> 14 15 #include "../channel.h" 16 #include "../dev.h" 17 #include "../intr.h" 18 #include "../job.h" 19 20 #define TRACE_MAX_LENGTH 128U 21 22 static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo, 23 u32 offset, u32 words) 24 { 25 struct device *dev = cdma_to_channel(cdma)->dev; 26 void *mem = NULL; 27 28 if (host1x_debug_trace_cmdbuf) 29 mem = host1x_bo_mmap(bo); 30 31 if (mem) { 32 u32 i; 33 /* 34 * Write in batches of 128 as there seems to be a limit 35 * of how much you can output to ftrace at once. 36 */ 37 for (i = 0; i < words; i += TRACE_MAX_LENGTH) { 38 u32 num_words = min(words - i, TRACE_MAX_LENGTH); 39 40 trace_host1x_cdma_push_gather(dev_name(dev), bo, 41 num_words, 42 offset + i * sizeof(u32), 43 mem); 44 } 45 46 host1x_bo_munmap(bo, mem); 47 } 48 } 49 50 static void submit_wait(struct host1x_job *job, u32 id, u32 threshold) 51 { 52 struct host1x_cdma *cdma = &job->channel->cdma; 53 54 #if HOST1X_HW >= 2 55 host1x_cdma_push_wide(cdma, 56 host1x_opcode_setclass( 57 HOST1X_CLASS_HOST1X, 58 HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32, 59 /* WAIT_SYNCPT_32 is at SYNCPT_PAYLOAD_32+2 */ 60 BIT(0) | BIT(2) 61 ), 62 threshold, 63 id, 64 HOST1X_OPCODE_NOP 65 ); 66 #else 67 /* TODO add waitchk or use waitbases or other mitigation */ 68 host1x_cdma_push(cdma, 69 host1x_opcode_setclass( 70 HOST1X_CLASS_HOST1X, 71 host1x_uclass_wait_syncpt_r(), 72 BIT(0) 73 ), 74 host1x_class_host_wait_syncpt(id, threshold) 75 ); 76 #endif 77 } 78 79 static void submit_setclass(struct host1x_job *job, u32 next_class) 80 { 81 struct host1x_cdma *cdma = &job->channel->cdma; 82 83 #if HOST1X_HW >= 6 84 u32 stream_id; 85 86 /* 87 * If a memory context has been set, use it. Otherwise 88 * (if context isolation is disabled) use the engine's 89 * firmware stream ID. 90 */ 91 if (job->memory_context) 92 stream_id = job->memory_context->stream_id; 93 else 94 stream_id = job->engine_fallback_streamid; 95 96 host1x_cdma_push_wide(cdma, 97 host1x_opcode_setclass(next_class, 0, 0), 98 host1x_opcode_setpayload(stream_id), 99 host1x_opcode_setstreamid(job->engine_streamid_offset / 4), 100 HOST1X_OPCODE_NOP); 101 #else 102 host1x_cdma_push(cdma, 103 host1x_opcode_setclass(next_class, 0, 0), 104 HOST1X_OPCODE_NOP 105 ); 106 #endif 107 } 108 109 static void submit_gathers(struct host1x_job *job, struct host1x_job_cmd *cmds, u32 num_cmds, 110 u32 job_syncpt_base) 111 { 112 struct host1x_cdma *cdma = &job->channel->cdma; 113 #if HOST1X_HW < 6 114 struct device *dev = job->channel->dev; 115 #endif 116 unsigned int i; 117 u32 threshold; 118 119 for (i = 0; i < num_cmds; i++) { 120 struct host1x_job_cmd *cmd = &cmds[i]; 121 122 if (cmd->is_wait) { 123 if (cmd->wait.relative) 124 threshold = wrapping_add(u32, job_syncpt_base, 125 cmd->wait.threshold); 126 else 127 threshold = cmd->wait.threshold; 128 129 submit_wait(job, cmd->wait.id, threshold); 130 submit_setclass(job, cmd->wait.next_class); 131 } else { 132 struct host1x_job_gather *g = &cmd->gather; 133 134 dma_addr_t addr = g->base + g->offset; 135 u32 op2, op3; 136 137 op2 = lower_32_bits(addr); 138 op3 = upper_32_bits(addr); 139 140 trace_write_gather(cdma, g->bo, g->offset, g->words); 141 142 if (op3 != 0) { 143 #if HOST1X_HW >= 6 144 u32 op1 = host1x_opcode_gather_wide(g->words); 145 u32 op4 = HOST1X_OPCODE_NOP; 146 147 host1x_cdma_push_wide(cdma, op1, op2, op3, op4); 148 #else 149 dev_err(dev, "invalid gather for push buffer %pad\n", 150 &addr); 151 continue; 152 #endif 153 } else { 154 u32 op1 = host1x_opcode_gather(g->words); 155 156 host1x_cdma_push(cdma, op1, op2); 157 } 158 } 159 } 160 } 161 162 static inline void synchronize_syncpt_base(struct host1x_job *job) 163 { 164 struct host1x_syncpt *sp = job->syncpt; 165 unsigned int id; 166 u32 value; 167 168 value = host1x_syncpt_read_max(sp); 169 id = sp->base->id; 170 171 host1x_cdma_push(&job->channel->cdma, 172 host1x_opcode_setclass(HOST1X_CLASS_HOST1X, 173 HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1), 174 HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(id) | 175 HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value)); 176 } 177 178 static void host1x_channel_set_streamid(struct host1x_channel *channel) 179 { 180 #if HOST1X_HW >= 6 181 u32 stream_id; 182 183 if (!tegra_dev_iommu_get_stream_id(channel->dev->parent, &stream_id)) 184 stream_id = TEGRA_STREAM_ID_BYPASS; 185 186 host1x_ch_writel(channel, stream_id, HOST1X_CHANNEL_SMMU_STREAMID); 187 #endif 188 } 189 190 static void host1x_enable_gather_filter(struct host1x_channel *ch) 191 { 192 #if HOST1X_HW >= 6 193 struct host1x *host = dev_get_drvdata(ch->dev->parent); 194 u32 val; 195 196 if (!host->hv_regs) 197 return; 198 199 val = host1x_hypervisor_readl( 200 host, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); 201 val |= BIT(ch->id % 32); 202 host1x_hypervisor_writel( 203 host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); 204 #elif HOST1X_HW >= 4 205 host1x_ch_writel(ch, 206 HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(1), 207 HOST1X_CHANNEL_CHANNELCTRL); 208 #endif 209 } 210 211 static void channel_program_cdma(struct host1x_job *job) 212 { 213 struct host1x_cdma *cdma = &job->channel->cdma; 214 struct host1x_syncpt *sp = job->syncpt; 215 216 #if HOST1X_HW >= 6 217 u32 fence; 218 int i = 0; 219 220 if (job->num_cmds == 0) 221 goto prefences_done; 222 if (!job->cmds[0].is_wait || job->cmds[0].wait.relative) 223 goto prefences_done; 224 225 /* Enter host1x class with invalid stream ID for prefence waits. */ 226 host1x_cdma_push_wide(cdma, 227 host1x_opcode_acquire_mlock(1), 228 host1x_opcode_setclass(1, 0, 0), 229 host1x_opcode_setpayload(0), 230 host1x_opcode_setstreamid(0x1fffff)); 231 232 for (i = 0; i < job->num_cmds; i++) { 233 struct host1x_job_cmd *cmd = &job->cmds[i]; 234 235 if (!cmd->is_wait || cmd->wait.relative) 236 break; 237 238 submit_wait(job, cmd->wait.id, cmd->wait.threshold); 239 } 240 241 host1x_cdma_push(cdma, 242 HOST1X_OPCODE_NOP, 243 host1x_opcode_release_mlock(1)); 244 245 prefences_done: 246 /* Enter engine class with invalid stream ID. */ 247 host1x_cdma_push_wide(cdma, 248 host1x_opcode_acquire_mlock(job->class), 249 host1x_opcode_setclass(job->class, 0, 0), 250 host1x_opcode_setpayload(0), 251 host1x_opcode_setstreamid(job->engine_streamid_offset / 4)); 252 253 /* Before switching stream ID to real stream ID, ensure engine is idle. */ 254 fence = host1x_syncpt_incr_max(sp, 1); 255 host1x_cdma_push(&job->channel->cdma, 256 host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1), 257 HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) | 258 HOST1X_UCLASS_INCR_SYNCPT_COND_F(4)); 259 submit_wait(job, job->syncpt->id, fence); 260 submit_setclass(job, job->class); 261 262 /* Submit work. */ 263 job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs); 264 submit_gathers(job, job->cmds + i, job->num_cmds - i, 265 wrapping_sub(u32, job->syncpt_end, job->syncpt_incrs)); 266 267 /* Before releasing MLOCK, ensure engine is idle again. */ 268 fence = host1x_syncpt_incr_max(sp, 1); 269 host1x_cdma_push(&job->channel->cdma, 270 host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1), 271 HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) | 272 HOST1X_UCLASS_INCR_SYNCPT_COND_F(4)); 273 submit_wait(job, job->syncpt->id, fence); 274 275 /* Release MLOCK. */ 276 host1x_cdma_push(cdma, 277 HOST1X_OPCODE_NOP, host1x_opcode_release_mlock(job->class)); 278 #else 279 if (job->serialize) { 280 /* 281 * Force serialization by inserting a host wait for the 282 * previous job to finish before this one can commence. 283 */ 284 host1x_cdma_push(cdma, 285 host1x_opcode_setclass(HOST1X_CLASS_HOST1X, 286 host1x_uclass_wait_syncpt_r(), 1), 287 host1x_class_host_wait_syncpt(job->syncpt->id, 288 host1x_syncpt_read_max(sp))); 289 } 290 291 /* Synchronize base register to allow using it for relative waiting */ 292 if (sp->base) 293 synchronize_syncpt_base(job); 294 295 /* add a setclass for modules that require it */ 296 if (job->class) 297 host1x_cdma_push(cdma, 298 host1x_opcode_setclass(job->class, 0, 0), 299 HOST1X_OPCODE_NOP); 300 301 job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs); 302 303 submit_gathers(job, job->cmds, job->num_cmds, 304 wrapping_sub(u32, job->syncpt_end, job->syncpt_incrs)); 305 #endif 306 } 307 308 static void job_complete_callback(struct dma_fence *fence, struct dma_fence_cb *cb) 309 { 310 struct host1x_job *job = container_of(cb, struct host1x_job, fence_cb); 311 312 /* Schedules CDMA update. */ 313 host1x_cdma_update(&job->channel->cdma); 314 } 315 316 static int channel_submit(struct host1x_job *job) 317 { 318 struct host1x_channel *ch = job->channel; 319 struct host1x_syncpt *sp = job->syncpt; 320 u32 prev_max = 0; 321 u32 syncval; 322 int err; 323 struct host1x *host = dev_get_drvdata(ch->dev->parent); 324 325 trace_host1x_channel_submit(dev_name(ch->dev), 326 job->num_cmds, job->num_relocs, 327 job->syncpt->id, job->syncpt_incrs); 328 329 /* before error checks, return current max */ 330 prev_max = job->syncpt_end = host1x_syncpt_read_max(sp); 331 332 /* get submit lock */ 333 err = mutex_lock_interruptible(&ch->submitlock); 334 if (err) 335 return err; 336 337 host1x_channel_set_streamid(ch); 338 host1x_enable_gather_filter(ch); 339 host1x_hw_syncpt_assign_to_channel(host, sp, ch); 340 341 /* begin a CDMA submit */ 342 err = host1x_cdma_begin(&ch->cdma, job); 343 if (err) { 344 mutex_unlock(&ch->submitlock); 345 return err; 346 } 347 348 channel_program_cdma(job); 349 syncval = host1x_syncpt_read_max(sp); 350 351 /* 352 * Create fence before submitting job to HW to avoid job completing 353 * before the fence is set up. 354 */ 355 job->fence = host1x_fence_create(sp, syncval, true); 356 if (WARN(IS_ERR(job->fence), "Failed to create submit complete fence")) { 357 job->fence = NULL; 358 } else { 359 err = dma_fence_add_callback(job->fence, &job->fence_cb, 360 job_complete_callback); 361 } 362 363 /* end CDMA submit & stash pinned hMems into sync queue */ 364 host1x_cdma_end(&ch->cdma, job); 365 366 trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, syncval); 367 368 mutex_unlock(&ch->submitlock); 369 370 if (err == -ENOENT) 371 host1x_cdma_update(&ch->cdma); 372 else 373 WARN(err, "Failed to set submit complete interrupt"); 374 375 return 0; 376 } 377 378 static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev, 379 unsigned int index) 380 { 381 #if HOST1X_HW < 6 382 ch->regs = dev->regs + index * 0x4000; 383 #else 384 ch->regs = dev->regs + index * 0x100; 385 #endif 386 return 0; 387 } 388 389 static const struct host1x_channel_ops host1x_channel_ops = { 390 .init = host1x_channel_init, 391 .submit = channel_submit, 392 }; 393