1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012-2015, NVIDIA Corporation. 4 */ 5 6 #ifndef HOST1X_DEV_H 7 #define HOST1X_DEV_H 8 9 #include <linux/device.h> 10 #include <linux/iommu.h> 11 #include <linux/iova.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 15 #include "cdma.h" 16 #include "channel.h" 17 #include "context.h" 18 #include "intr.h" 19 #include "job.h" 20 #include "syncpt.h" 21 22 struct host1x_syncpt; 23 struct host1x_syncpt_base; 24 struct host1x_channel; 25 struct host1x_cdma; 26 struct host1x_job; 27 struct push_buffer; 28 struct output; 29 struct dentry; 30 31 struct host1x_channel_ops { 32 int (*init)(struct host1x_channel *channel, struct host1x *host, 33 unsigned int id); 34 int (*submit)(struct host1x_job *job); 35 }; 36 37 struct host1x_cdma_ops { 38 void (*start)(struct host1x_cdma *cdma); 39 void (*stop)(struct host1x_cdma *cdma); 40 void (*flush)(struct host1x_cdma *cdma); 41 int (*timeout_init)(struct host1x_cdma *cdma); 42 void (*timeout_destroy)(struct host1x_cdma *cdma); 43 void (*freeze)(struct host1x_cdma *cdma); 44 void (*resume)(struct host1x_cdma *cdma, u32 getptr); 45 void (*timeout_cpu_incr)(struct host1x_cdma *cdma, u32 getptr, 46 u32 syncpt_incrs, u32 syncval, u32 nr_slots); 47 }; 48 49 struct host1x_pushbuffer_ops { 50 void (*init)(struct push_buffer *pb); 51 }; 52 53 struct host1x_debug_ops { 54 void (*debug_init)(struct dentry *de); 55 void (*show_channel_cdma)(struct host1x *host, 56 struct host1x_channel *ch, 57 struct output *o); 58 void (*show_channel_fifo)(struct host1x *host, 59 struct host1x_channel *ch, 60 struct output *o); 61 void (*show_mlocks)(struct host1x *host, struct output *output); 62 63 }; 64 65 struct host1x_syncpt_ops { 66 void (*restore)(struct host1x_syncpt *syncpt); 67 void (*restore_wait_base)(struct host1x_syncpt *syncpt); 68 void (*load_wait_base)(struct host1x_syncpt *syncpt); 69 u32 (*load)(struct host1x_syncpt *syncpt); 70 int (*cpu_incr)(struct host1x_syncpt *syncpt); 71 void (*assign_to_channel)(struct host1x_syncpt *syncpt, 72 struct host1x_channel *channel); 73 void (*enable_protection)(struct host1x *host); 74 }; 75 76 struct host1x_intr_ops { 77 int (*init_host_sync)(struct host1x *host, u32 cpm); 78 void (*set_syncpt_threshold)( 79 struct host1x *host, unsigned int id, u32 thresh); 80 void (*enable_syncpt_intr)(struct host1x *host, unsigned int id); 81 void (*disable_syncpt_intr)(struct host1x *host, unsigned int id); 82 void (*disable_all_syncpt_intrs)(struct host1x *host); 83 int (*free_syncpt_irq)(struct host1x *host); 84 }; 85 86 struct host1x_sid_entry { 87 unsigned int base; 88 unsigned int offset; 89 unsigned int limit; 90 }; 91 92 struct host1x_table_desc { 93 unsigned int base; 94 unsigned int count; 95 }; 96 97 struct host1x_info { 98 unsigned int nb_channels; /* host1x: number of channels supported */ 99 unsigned int nb_pts; /* host1x: number of syncpoints supported */ 100 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */ 101 unsigned int nb_mlocks; /* host1x: number of mlocks supported */ 102 int (*init)(struct host1x *host1x); /* initialize per SoC ops */ 103 unsigned int sync_offset; /* offset of syncpoint registers */ 104 u64 dma_mask; /* mask of addressable memory */ 105 bool has_wide_gather; /* supports GATHER_W opcode */ 106 bool has_hypervisor; /* has hypervisor registers */ 107 bool has_common; /* has common registers separate from hypervisor */ 108 unsigned int num_sid_entries; 109 const struct host1x_sid_entry *sid_table; 110 struct host1x_table_desc streamid_vm_table; 111 struct host1x_table_desc classid_vm_table; 112 struct host1x_table_desc mmio_vm_table; 113 /* 114 * On T20-T148, the boot chain may setup DC to increment syncpoints 115 * 26/27 on VBLANK. As such we cannot use these syncpoints until 116 * the display driver disables VBLANK increments. 117 */ 118 bool reserve_vblank_syncpts; 119 }; 120 121 struct host1x { 122 const struct host1x_info *info; 123 124 void __iomem *regs; 125 void __iomem *hv_regs; /* hypervisor region */ 126 void __iomem *common_regs; 127 int syncpt_irq; 128 struct host1x_syncpt *syncpt; 129 struct host1x_syncpt_base *bases; 130 struct device *dev; 131 struct clk *clk; 132 struct reset_control_bulk_data resets[2]; 133 unsigned int nresets; 134 135 struct iommu_group *group; 136 struct iommu_domain *domain; 137 struct iova_domain iova; 138 dma_addr_t iova_end; 139 140 struct mutex intr_mutex; 141 142 const struct host1x_syncpt_ops *syncpt_op; 143 const struct host1x_intr_ops *intr_op; 144 const struct host1x_channel_ops *channel_op; 145 const struct host1x_cdma_ops *cdma_op; 146 const struct host1x_pushbuffer_ops *cdma_pb_op; 147 const struct host1x_debug_ops *debug_op; 148 149 struct host1x_syncpt *nop_sp; 150 151 struct mutex syncpt_mutex; 152 153 struct host1x_channel_list channel_list; 154 struct host1x_memory_context_list context_list; 155 156 struct dentry *debugfs; 157 158 struct mutex devices_lock; 159 struct list_head devices; 160 161 struct list_head list; 162 163 struct device_dma_parameters dma_parms; 164 165 struct host1x_bo_cache cache; 166 }; 167 168 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r); 169 void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v); 170 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r); 171 void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v); 172 u32 host1x_sync_readl(struct host1x *host1x, u32 r); 173 void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v); 174 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r); 175 176 static inline void host1x_hw_syncpt_restore(struct host1x *host, 177 struct host1x_syncpt *sp) 178 { 179 host->syncpt_op->restore(sp); 180 } 181 182 static inline void host1x_hw_syncpt_restore_wait_base(struct host1x *host, 183 struct host1x_syncpt *sp) 184 { 185 host->syncpt_op->restore_wait_base(sp); 186 } 187 188 static inline void host1x_hw_syncpt_load_wait_base(struct host1x *host, 189 struct host1x_syncpt *sp) 190 { 191 host->syncpt_op->load_wait_base(sp); 192 } 193 194 static inline u32 host1x_hw_syncpt_load(struct host1x *host, 195 struct host1x_syncpt *sp) 196 { 197 return host->syncpt_op->load(sp); 198 } 199 200 static inline int host1x_hw_syncpt_cpu_incr(struct host1x *host, 201 struct host1x_syncpt *sp) 202 { 203 return host->syncpt_op->cpu_incr(sp); 204 } 205 206 static inline void host1x_hw_syncpt_assign_to_channel( 207 struct host1x *host, struct host1x_syncpt *sp, 208 struct host1x_channel *ch) 209 { 210 return host->syncpt_op->assign_to_channel(sp, ch); 211 } 212 213 static inline void host1x_hw_syncpt_enable_protection(struct host1x *host) 214 { 215 return host->syncpt_op->enable_protection(host); 216 } 217 218 static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm) 219 { 220 return host->intr_op->init_host_sync(host, cpm); 221 } 222 223 static inline void host1x_hw_intr_set_syncpt_threshold(struct host1x *host, 224 unsigned int id, 225 u32 thresh) 226 { 227 host->intr_op->set_syncpt_threshold(host, id, thresh); 228 } 229 230 static inline void host1x_hw_intr_enable_syncpt_intr(struct host1x *host, 231 unsigned int id) 232 { 233 host->intr_op->enable_syncpt_intr(host, id); 234 } 235 236 static inline void host1x_hw_intr_disable_syncpt_intr(struct host1x *host, 237 unsigned int id) 238 { 239 host->intr_op->disable_syncpt_intr(host, id); 240 } 241 242 static inline void host1x_hw_intr_disable_all_syncpt_intrs(struct host1x *host) 243 { 244 host->intr_op->disable_all_syncpt_intrs(host); 245 } 246 247 static inline int host1x_hw_intr_free_syncpt_irq(struct host1x *host) 248 { 249 return host->intr_op->free_syncpt_irq(host); 250 } 251 252 static inline int host1x_hw_channel_init(struct host1x *host, 253 struct host1x_channel *channel, 254 unsigned int id) 255 { 256 return host->channel_op->init(channel, host, id); 257 } 258 259 static inline int host1x_hw_channel_submit(struct host1x *host, 260 struct host1x_job *job) 261 { 262 return host->channel_op->submit(job); 263 } 264 265 static inline void host1x_hw_cdma_start(struct host1x *host, 266 struct host1x_cdma *cdma) 267 { 268 host->cdma_op->start(cdma); 269 } 270 271 static inline void host1x_hw_cdma_stop(struct host1x *host, 272 struct host1x_cdma *cdma) 273 { 274 host->cdma_op->stop(cdma); 275 } 276 277 static inline void host1x_hw_cdma_flush(struct host1x *host, 278 struct host1x_cdma *cdma) 279 { 280 host->cdma_op->flush(cdma); 281 } 282 283 static inline int host1x_hw_cdma_timeout_init(struct host1x *host, 284 struct host1x_cdma *cdma) 285 { 286 return host->cdma_op->timeout_init(cdma); 287 } 288 289 static inline void host1x_hw_cdma_timeout_destroy(struct host1x *host, 290 struct host1x_cdma *cdma) 291 { 292 host->cdma_op->timeout_destroy(cdma); 293 } 294 295 static inline void host1x_hw_cdma_freeze(struct host1x *host, 296 struct host1x_cdma *cdma) 297 { 298 host->cdma_op->freeze(cdma); 299 } 300 301 static inline void host1x_hw_cdma_resume(struct host1x *host, 302 struct host1x_cdma *cdma, u32 getptr) 303 { 304 host->cdma_op->resume(cdma, getptr); 305 } 306 307 static inline void host1x_hw_cdma_timeout_cpu_incr(struct host1x *host, 308 struct host1x_cdma *cdma, 309 u32 getptr, 310 u32 syncpt_incrs, 311 u32 syncval, u32 nr_slots) 312 { 313 host->cdma_op->timeout_cpu_incr(cdma, getptr, syncpt_incrs, syncval, 314 nr_slots); 315 } 316 317 static inline void host1x_hw_pushbuffer_init(struct host1x *host, 318 struct push_buffer *pb) 319 { 320 host->cdma_pb_op->init(pb); 321 } 322 323 static inline void host1x_hw_debug_init(struct host1x *host, struct dentry *de) 324 { 325 if (host->debug_op && host->debug_op->debug_init) 326 host->debug_op->debug_init(de); 327 } 328 329 static inline void host1x_hw_show_channel_cdma(struct host1x *host, 330 struct host1x_channel *channel, 331 struct output *o) 332 { 333 host->debug_op->show_channel_cdma(host, channel, o); 334 } 335 336 static inline void host1x_hw_show_channel_fifo(struct host1x *host, 337 struct host1x_channel *channel, 338 struct output *o) 339 { 340 host->debug_op->show_channel_fifo(host, channel, o); 341 } 342 343 static inline void host1x_hw_show_mlocks(struct host1x *host, struct output *o) 344 { 345 host->debug_op->show_mlocks(host, o); 346 } 347 348 extern struct platform_driver tegra_mipi_driver; 349 350 #endif 351