1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x driver 4 * 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/io.h> 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 20 #include <soc/tegra/common.h> 21 22 #define CREATE_TRACE_POINTS 23 #include <trace/events/host1x.h> 24 #undef CREATE_TRACE_POINTS 25 26 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 27 #include <asm/dma-iommu.h> 28 #endif 29 30 #include "bus.h" 31 #include "channel.h" 32 #include "context.h" 33 #include "debug.h" 34 #include "dev.h" 35 #include "intr.h" 36 37 #include "hw/host1x01.h" 38 #include "hw/host1x02.h" 39 #include "hw/host1x04.h" 40 #include "hw/host1x05.h" 41 #include "hw/host1x06.h" 42 #include "hw/host1x07.h" 43 #include "hw/host1x08.h" 44 #include "hw/host1x10.h" 45 46 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r) 47 { 48 writel(v, host1x->common_regs + r); 49 } 50 51 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 52 { 53 writel(v, host1x->hv_regs + r); 54 } 55 56 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 57 { 58 return readl(host1x->hv_regs + r); 59 } 60 61 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 62 { 63 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 64 65 writel(v, sync_regs + r); 66 } 67 68 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 69 { 70 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 71 72 return readl(sync_regs + r); 73 } 74 75 #ifdef CONFIG_64BIT 76 u64 host1x_sync_readq(struct host1x *host1x, u32 r) 77 { 78 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 79 80 return readq(sync_regs + r); 81 } 82 #endif 83 84 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 85 { 86 writel(v, ch->regs + r); 87 } 88 89 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 90 { 91 return readl(ch->regs + r); 92 } 93 94 static const struct host1x_info host1x01_info = { 95 .nb_channels = 8, 96 .nb_pts = 32, 97 .nb_mlocks = 16, 98 .nb_bases = 8, 99 .init = host1x01_init, 100 .sync_offset = 0x3000, 101 .dma_mask = DMA_BIT_MASK(32), 102 .has_wide_gather = false, 103 .has_hypervisor = false, 104 .num_sid_entries = 0, 105 .sid_table = NULL, 106 .reserve_vblank_syncpts = true, 107 }; 108 109 static const struct host1x_info host1x02_info = { 110 .nb_channels = 9, 111 .nb_pts = 32, 112 .nb_mlocks = 16, 113 .nb_bases = 12, 114 .init = host1x02_init, 115 .sync_offset = 0x3000, 116 .dma_mask = DMA_BIT_MASK(32), 117 .has_wide_gather = false, 118 .has_hypervisor = false, 119 .num_sid_entries = 0, 120 .sid_table = NULL, 121 .reserve_vblank_syncpts = true, 122 }; 123 124 static const struct host1x_info host1x04_info = { 125 .nb_channels = 12, 126 .nb_pts = 192, 127 .nb_mlocks = 16, 128 .nb_bases = 64, 129 .init = host1x04_init, 130 .sync_offset = 0x2100, 131 .dma_mask = DMA_BIT_MASK(34), 132 .has_wide_gather = false, 133 .has_hypervisor = false, 134 .num_sid_entries = 0, 135 .sid_table = NULL, 136 .reserve_vblank_syncpts = false, 137 }; 138 139 static const struct host1x_info host1x05_info = { 140 .nb_channels = 14, 141 .nb_pts = 192, 142 .nb_mlocks = 16, 143 .nb_bases = 64, 144 .init = host1x05_init, 145 .sync_offset = 0x2100, 146 .dma_mask = DMA_BIT_MASK(34), 147 .has_wide_gather = false, 148 .has_hypervisor = false, 149 .num_sid_entries = 0, 150 .sid_table = NULL, 151 .reserve_vblank_syncpts = false, 152 }; 153 154 static const struct host1x_sid_entry tegra186_sid_table[] = { 155 { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 }, 156 { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 }, 157 { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 }, 158 { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 }, 159 { /* ISP */ .base = 0x1ae8, .offset = 0x50, .limit = 0x50 }, 160 { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 }, 161 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 }, 162 { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, 163 { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 }, 164 { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 }, 165 { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 }, 166 { /* VI 0 */ .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 }, 167 { /* VI 1 */ .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 }, 168 { /* VI 2 */ .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 }, 169 { /* VI 3 */ .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 }, 170 { /* VI 4 */ .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 }, 171 { /* VI 5 */ .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 }, 172 { /* VI 6 */ .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 }, 173 { /* VI 7 */ .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 }, 174 { /* VI 8 */ .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 }, 175 { /* VI 9 */ .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 }, 176 { /* VI 10 */ .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 }, 177 { /* VI 11 */ .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 }, 178 }; 179 180 static const struct host1x_info host1x06_info = { 181 .nb_channels = 63, 182 .nb_pts = 576, 183 .nb_mlocks = 24, 184 .nb_bases = 16, 185 .init = host1x06_init, 186 .sync_offset = 0x0, 187 .dma_mask = DMA_BIT_MASK(40), 188 .has_wide_gather = true, 189 .has_hypervisor = true, 190 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), 191 .sid_table = tegra186_sid_table, 192 .reserve_vblank_syncpts = false, 193 .skip_reset_assert = true, 194 }; 195 196 static const struct host1x_sid_entry tegra194_sid_table[] = { 197 { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 }, 198 { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 }, 199 { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 }, 200 { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 }, 201 { /* ISP */ .base = 0x1ae8, .offset = 0x800, .limit = 0x800 }, 202 { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 }, 203 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 }, 204 { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, 205 { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 }, 206 { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 }, 207 { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 }, 208 { /* VI */ .base = 0x1b80, .offset = 0x800, .limit = 0x800 }, 209 { /* VI_THI */ .base = 0x1b88, .offset = 0x30, .limit = 0x34 }, 210 { /* ISP_THI */ .base = 0x1b90, .offset = 0x30, .limit = 0x34 }, 211 { /* PVA0_CLUSTER */ .base = 0x1b98, .offset = 0x0, .limit = 0x0 }, 212 { /* PVA0_CLUSTER */ .base = 0x1ba0, .offset = 0x0, .limit = 0x0 }, 213 { /* NVDLA0 */ .base = 0x1ba8, .offset = 0x30, .limit = 0x34 }, 214 { /* NVDLA1 */ .base = 0x1bb0, .offset = 0x30, .limit = 0x34 }, 215 { /* NVENC1 */ .base = 0x1bb8, .offset = 0x30, .limit = 0x34 }, 216 { /* NVDEC1 */ .base = 0x1bc0, .offset = 0x30, .limit = 0x34 }, 217 }; 218 219 static const struct host1x_info host1x07_info = { 220 .nb_channels = 63, 221 .nb_pts = 704, 222 .nb_mlocks = 32, 223 .nb_bases = 0, 224 .init = host1x07_init, 225 .sync_offset = 0x0, 226 .dma_mask = DMA_BIT_MASK(40), 227 .has_wide_gather = true, 228 .has_hypervisor = true, 229 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), 230 .sid_table = tegra194_sid_table, 231 .reserve_vblank_syncpts = false, 232 }; 233 234 /* 235 * Tegra234 has two stream ID protection tables, one for setting stream IDs 236 * through the channel path via SETSTREAMID, and one for setting them via 237 * MMIO. We program each engine's data stream ID in the channel path table 238 * and firmware stream ID in the MMIO path table. 239 */ 240 static const struct host1x_sid_entry tegra234_sid_table[] = { 241 { /* SE1 MMIO */ .base = 0x1650, .offset = 0x90, .limit = 0x90 }, 242 { /* SE1 ch */ .base = 0x1730, .offset = 0x90, .limit = 0x90 }, 243 { /* SE2 MMIO */ .base = 0x1658, .offset = 0x90, .limit = 0x90 }, 244 { /* SE2 ch */ .base = 0x1738, .offset = 0x90, .limit = 0x90 }, 245 { /* SE4 MMIO */ .base = 0x1660, .offset = 0x90, .limit = 0x90 }, 246 { /* SE4 ch */ .base = 0x1740, .offset = 0x90, .limit = 0x90 }, 247 { /* ISP MMIO */ .base = 0x1680, .offset = 0x800, .limit = 0x800 }, 248 { /* VIC MMIO */ .base = 0x1688, .offset = 0x34, .limit = 0x34 }, 249 { /* VIC ch */ .base = 0x17b8, .offset = 0x30, .limit = 0x30 }, 250 { /* NVENC MMIO */ .base = 0x1690, .offset = 0x34, .limit = 0x34 }, 251 { /* NVENC ch */ .base = 0x17c0, .offset = 0x30, .limit = 0x30 }, 252 { /* NVDEC MMIO */ .base = 0x1698, .offset = 0x34, .limit = 0x34 }, 253 { /* NVDEC ch */ .base = 0x17c8, .offset = 0x30, .limit = 0x30 }, 254 { /* NVJPG MMIO */ .base = 0x16a0, .offset = 0x34, .limit = 0x34 }, 255 { /* NVJPG ch */ .base = 0x17d0, .offset = 0x30, .limit = 0x30 }, 256 { /* TSEC MMIO */ .base = 0x16a8, .offset = 0x30, .limit = 0x34 }, 257 { /* NVJPG1 MMIO */ .base = 0x16b0, .offset = 0x34, .limit = 0x34 }, 258 { /* NVJPG1 ch */ .base = 0x17a8, .offset = 0x30, .limit = 0x30 }, 259 { /* VI MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 }, 260 { /* VI_THI MMIO */ .base = 0x16c0, .offset = 0x30, .limit = 0x34 }, 261 { /* ISP_THI MMIO */ .base = 0x16c8, .offset = 0x30, .limit = 0x34 }, 262 { /* NVDLA MMIO */ .base = 0x16d8, .offset = 0x30, .limit = 0x34 }, 263 { /* NVDLA ch */ .base = 0x17e0, .offset = 0x30, .limit = 0x34 }, 264 { /* NVDLA1 MMIO */ .base = 0x16e0, .offset = 0x30, .limit = 0x34 }, 265 { /* NVDLA1 ch */ .base = 0x17e8, .offset = 0x30, .limit = 0x34 }, 266 { /* OFA MMIO */ .base = 0x16e8, .offset = 0x34, .limit = 0x34 }, 267 { /* OFA ch */ .base = 0x1768, .offset = 0x30, .limit = 0x30 }, 268 { /* VI2 MMIO */ .base = 0x16f0, .offset = 0x800, .limit = 0x800 }, 269 { /* VI2_THI MMIO */ .base = 0x16f8, .offset = 0x30, .limit = 0x34 }, 270 }; 271 272 static const struct host1x_info host1x08_info = { 273 .nb_channels = 63, 274 .nb_pts = 1024, 275 .nb_mlocks = 24, 276 .nb_bases = 0, 277 .init = host1x08_init, 278 .sync_offset = 0x0, 279 .dma_mask = DMA_BIT_MASK(40), 280 .has_wide_gather = true, 281 .has_hypervisor = true, 282 .has_common = true, 283 .num_sid_entries = ARRAY_SIZE(tegra234_sid_table), 284 .sid_table = tegra234_sid_table, 285 .streamid_vm_table = { 0x1004, 128 }, 286 .classid_vm_table = { 0x1404, 25 }, 287 .mmio_vm_table = { 0x1504, 25 }, 288 .reserve_vblank_syncpts = false, 289 }; 290 291 static const struct host1x_sid_entry tegra264_sid_table[] = { 292 { /* SE1 MMIO */ .base = 0x1650, .offset = 0x90, .limit = 0x90 }, 293 { /* SE2 MMIO */ .base = 0x1658, .offset = 0x90, .limit = 0x90 }, 294 { /* SE4 MMIO */ .base = 0x1660, .offset = 0x90, .limit = 0x90 }, 295 { /* SE1 ch */ .base = 0x1738, .offset = 0x90, .limit = 0x90 }, 296 { /* SE2 ch */ .base = 0x1740, .offset = 0x90, .limit = 0x90 }, 297 { /* SE4 ch */ .base = 0x1748, .offset = 0x90, .limit = 0x90 }, 298 { /* VIC ch */ .base = 0x1790, .offset = 0x30, .limit = 0x30 }, 299 { /* VIC MMIO */ .base = 0x1688, .offset = 0x34, .limit = 0x34 }, 300 { /* TSEC MMIO */ .base = 0x1690, .offset = 0x30, .limit = 0x34 }, 301 { /* VI MMIO */ .base = 0x1698, .offset = 0x800, .limit = 0x800 }, 302 { /* VI_THI MMIO */ .base = 0x16a0, .offset = 0x30, .limit = 0x34 }, 303 { /* ISP MMIO */ .base = 0x1680, .offset = 0x800, .limit = 0x800 }, 304 { /* ISP_THI MMIO */ .base = 0x16a8, .offset = 0x30, .limit = 0x34 }, 305 { /* VI2 MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 }, 306 { /* VI2_THI MMIO */ .base = 0x16c0, .offset = 0x30, .limit = 0x34 }, 307 { /* ISP1 MMIO */ .base = 0x16c8, .offset = 0x800, .limit = 0x800 }, 308 { /* ISP1_THI MMIO */ .base = 0x16d0, .offset = 0x30, .limit = 0x34 }, 309 }; 310 311 static const struct host1x_info host1x10_info = { 312 .nb_channels = 63, 313 .nb_pts = 1024, 314 .nb_mlocks = 24, 315 .nb_bases = 0, 316 .init = host1x10_init, 317 .sync_offset = 0x0, 318 .dma_mask = DMA_BIT_MASK(40), 319 .has_wide_gather = true, 320 .has_hypervisor = true, 321 .has_common = true, 322 .num_sid_entries = ARRAY_SIZE(tegra264_sid_table), 323 .sid_table = tegra264_sid_table, 324 .streamid_vm_table = { 0x1004, 128 }, 325 .classid_vm_table = { 0x1404, 25 }, 326 .mmio_vm_table = { 0x1504, 25 }, 327 .reserve_vblank_syncpts = false, 328 }; 329 330 static const struct of_device_id host1x_of_match[] = { 331 { .compatible = "nvidia,tegra264-host1x", .data = &host1x10_info, }, 332 { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, }, 333 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, 334 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 335 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 336 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 337 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 338 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 339 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 340 { }, 341 }; 342 MODULE_DEVICE_TABLE(of, host1x_of_match); 343 344 static void host1x_setup_virtualization_tables(struct host1x *host) 345 { 346 const struct host1x_info *info = host->info; 347 unsigned int i; 348 349 if (!host->hv_regs) 350 return; 351 352 for (i = 0; i < info->num_sid_entries; i++) { 353 const struct host1x_sid_entry *entry = &info->sid_table[i]; 354 355 host1x_hypervisor_writel(host, entry->offset, entry->base); 356 host1x_hypervisor_writel(host, entry->limit, entry->base + 4); 357 } 358 359 for (i = 0; i < info->streamid_vm_table.count; i++) { 360 /* Allow access to all stream IDs to all VMs. */ 361 host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i); 362 } 363 364 for (i = 0; i < info->classid_vm_table.count; i++) { 365 /* Allow access to all classes to all VMs. */ 366 host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i); 367 } 368 369 for (i = 0; i < info->mmio_vm_table.count; i++) { 370 /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */ 371 host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i); 372 } 373 } 374 375 static int host1x_get_assigned_resources(struct host1x *host) 376 { 377 struct device_node *np = host->dev->of_node; 378 u32 vals[2]; 379 int err; 380 381 err = of_property_read_u32_array(np, "nvidia,channels", vals, 2); 382 if (err == 0) { 383 host->channel_base = vals[0]; 384 host->channel_end = vals[0] + vals[1]; 385 } else if (err == -EINVAL) { 386 host->channel_base = 0; 387 host->channel_end = host->info->nb_channels; 388 } else { 389 dev_err(host->dev, "invalid nvidia,channels property: %d\n", err); 390 return err; 391 } 392 393 err = of_property_read_u32_array(np, "nvidia,syncpoints", vals, 2); 394 if (err == 0) { 395 host->syncpt_base = vals[0]; 396 host->syncpt_end = vals[0] + vals[1]; 397 } else if (err == -EINVAL) { 398 host->syncpt_base = 0; 399 host->syncpt_end = host->info->nb_pts; 400 } else { 401 dev_err(host->dev, "invalid nvidia,syncpoints property: %d\n", err); 402 return err; 403 } 404 405 return 0; 406 } 407 408 static bool host1x_wants_iommu(struct host1x *host1x) 409 { 410 /* Our IOMMU usage policy doesn't currently play well with GART */ 411 if (of_machine_is_compatible("nvidia,tegra20")) 412 return false; 413 414 /* 415 * If we support addressing a maximum of 32 bits of physical memory 416 * and if the host1x firewall is enabled, there's no need to enable 417 * IOMMU support. This can happen for example on Tegra20, Tegra30 418 * and Tegra114. 419 * 420 * Tegra124 and later can address up to 34 bits of physical memory and 421 * many platforms come equipped with more than 2 GiB of system memory, 422 * which requires crossing the 4 GiB boundary. But there's a catch: on 423 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can 424 * only address up to 32 bits of memory in GATHER opcodes, which means 425 * that command buffers need to either be in the first 2 GiB of system 426 * memory (which could quickly lead to memory exhaustion), or command 427 * buffers need to be treated differently from other buffers (which is 428 * not possible with the current ABI). 429 * 430 * A third option is to use the IOMMU in these cases to make sure all 431 * buffers will be mapped into a 32-bit IOVA space that host1x can 432 * address. This allows all of the system memory to be used and works 433 * within the limitations of the host1x on these SoCs. 434 * 435 * In summary, default to enable IOMMU on Tegra124 and later. For any 436 * of the earlier SoCs, only use the IOMMU for additional safety when 437 * the host1x firewall is disabled. 438 */ 439 if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) { 440 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 441 return false; 442 } 443 444 return true; 445 } 446 447 /* 448 * Returns ERR_PTR on failure, NULL if the translation is IDENTITY, otherwise a 449 * valid paging domain. 450 */ 451 static struct iommu_domain *host1x_iommu_attach(struct host1x *host) 452 { 453 struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev); 454 int err; 455 456 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 457 if (host->dev->archdata.mapping) { 458 struct dma_iommu_mapping *mapping = 459 to_dma_iommu_mapping(host->dev); 460 arm_iommu_detach_device(host->dev); 461 arm_iommu_release_mapping(mapping); 462 463 domain = iommu_get_domain_for_dev(host->dev); 464 } 465 #endif 466 467 /* 468 * We may not always want to enable IOMMU support (for example if the 469 * host1x firewall is already enabled and we don't support addressing 470 * more than 32 bits of physical memory), so check for that first. 471 * 472 * Similarly, if host1x is already attached to an IOMMU (via the DMA 473 * API), don't try to attach again. 474 */ 475 if (domain && domain->type == IOMMU_DOMAIN_IDENTITY) 476 domain = NULL; 477 if (!host1x_wants_iommu(host) || domain) 478 return domain; 479 480 host->group = iommu_group_get(host->dev); 481 if (host->group) { 482 struct iommu_domain_geometry *geometry; 483 dma_addr_t start, end; 484 unsigned long order; 485 486 err = iova_cache_get(); 487 if (err < 0) 488 goto put_group; 489 490 host->domain = iommu_paging_domain_alloc(host->dev); 491 if (IS_ERR(host->domain)) { 492 err = PTR_ERR(host->domain); 493 host->domain = NULL; 494 goto put_cache; 495 } 496 497 err = iommu_attach_group(host->domain, host->group); 498 if (err) { 499 if (err == -ENODEV) 500 err = 0; 501 502 goto free_domain; 503 } 504 505 geometry = &host->domain->geometry; 506 start = geometry->aperture_start & host->info->dma_mask; 507 end = geometry->aperture_end & host->info->dma_mask; 508 509 order = __ffs(host->domain->pgsize_bitmap); 510 init_iova_domain(&host->iova, 1UL << order, start >> order); 511 host->iova_end = end; 512 513 domain = host->domain; 514 } 515 516 return domain; 517 518 free_domain: 519 iommu_domain_free(host->domain); 520 host->domain = NULL; 521 put_cache: 522 iova_cache_put(); 523 put_group: 524 iommu_group_put(host->group); 525 host->group = NULL; 526 527 return ERR_PTR(err); 528 } 529 530 static int host1x_iommu_init(struct host1x *host) 531 { 532 u64 mask = host->info->dma_mask; 533 struct iommu_domain *domain; 534 int err; 535 536 domain = host1x_iommu_attach(host); 537 if (IS_ERR(domain)) { 538 err = PTR_ERR(domain); 539 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err); 540 return err; 541 } 542 543 /* 544 * If we're not behind an IOMMU make sure we don't get push buffers 545 * that are allocated outside of the range addressable by the GATHER 546 * opcode. 547 * 548 * Newer generations of Tegra (Tegra186 and later) support a wide 549 * variant of the GATHER opcode that allows addressing more bits. 550 */ 551 if (!domain && !host->info->has_wide_gather) 552 mask = DMA_BIT_MASK(32); 553 554 err = dma_coerce_mask_and_coherent(host->dev, mask); 555 if (err < 0) { 556 dev_err(host->dev, "failed to set DMA mask: %d\n", err); 557 return err; 558 } 559 560 return 0; 561 } 562 563 static void host1x_iommu_exit(struct host1x *host) 564 { 565 if (host->domain) { 566 put_iova_domain(&host->iova); 567 iommu_detach_group(host->domain, host->group); 568 569 iommu_domain_free(host->domain); 570 host->domain = NULL; 571 572 iova_cache_put(); 573 574 iommu_group_put(host->group); 575 host->group = NULL; 576 } 577 } 578 579 static int host1x_get_resets(struct host1x *host) 580 { 581 int err; 582 583 host->resets[0].id = "mc"; 584 host->resets[1].id = "host1x"; 585 host->nresets = ARRAY_SIZE(host->resets); 586 587 err = devm_reset_control_bulk_get_optional_exclusive_released( 588 host->dev, host->nresets, host->resets); 589 if (err) { 590 dev_err(host->dev, "failed to get reset: %d\n", err); 591 return err; 592 } 593 594 return 0; 595 } 596 597 static int host1x_probe(struct platform_device *pdev) 598 { 599 struct host1x *host; 600 int err, i; 601 602 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 603 if (!host) 604 return -ENOMEM; 605 606 host->info = of_device_get_match_data(&pdev->dev); 607 608 if (host->info->has_hypervisor) { 609 struct resource *res; 610 611 host->regs = devm_platform_ioremap_resource_byname(pdev, "vm"); 612 if (IS_ERR(host->regs)) 613 return PTR_ERR(host->regs); 614 615 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hypervisor"); 616 if (res) { 617 host->hv_regs = devm_ioremap_resource(&pdev->dev, res); 618 if (IS_ERR(host->hv_regs)) 619 return PTR_ERR(host->hv_regs); 620 } 621 622 if (res && host->info->has_common) { 623 host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common"); 624 if (IS_ERR(host->common_regs)) 625 return PTR_ERR(host->common_regs); 626 } 627 } else { 628 host->regs = devm_platform_ioremap_resource(pdev, 0); 629 if (IS_ERR(host->regs)) 630 return PTR_ERR(host->regs); 631 } 632 633 for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) { 634 char irq_name[] = "syncptX"; 635 636 sprintf(irq_name, "syncpt%d", i); 637 638 err = platform_get_irq_byname_optional(pdev, irq_name); 639 if (err == -ENXIO) 640 break; 641 if (err < 0) 642 return err; 643 644 host->syncpt_irqs[i] = err; 645 } 646 647 host->num_syncpt_irqs = i; 648 649 /* Device tree without irq names */ 650 if (i == 0) { 651 host->syncpt_irqs[0] = platform_get_irq(pdev, 0); 652 if (host->syncpt_irqs[0] < 0) 653 return host->syncpt_irqs[0]; 654 655 host->num_syncpt_irqs = 1; 656 } 657 658 mutex_init(&host->devices_lock); 659 INIT_LIST_HEAD(&host->devices); 660 INIT_LIST_HEAD(&host->list); 661 host->dev = &pdev->dev; 662 663 /* set common host1x device data */ 664 platform_set_drvdata(pdev, host); 665 666 host->dev->dma_parms = &host->dma_parms; 667 dma_set_max_seg_size(host->dev, UINT_MAX); 668 669 if (host->info->init) { 670 err = host->info->init(host); 671 if (err) 672 return err; 673 } 674 675 host->clk = devm_clk_get(&pdev->dev, NULL); 676 if (IS_ERR(host->clk)) 677 return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "failed to get clock\n"); 678 679 err = host1x_get_assigned_resources(host); 680 if (err) 681 return err; 682 683 err = host1x_get_resets(host); 684 if (err) 685 return err; 686 687 host1x_bo_cache_init(&host->cache); 688 689 err = host1x_iommu_init(host); 690 if (err < 0) { 691 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err); 692 goto destroy_cache; 693 } 694 695 err = host1x_channel_list_init(&host->channel_list, 696 host->info->nb_channels); 697 if (err) { 698 dev_err(&pdev->dev, "failed to initialize channel list\n"); 699 goto iommu_exit; 700 } 701 702 err = host1x_memory_context_list_init(host); 703 if (err) { 704 dev_err(&pdev->dev, "failed to initialize context list\n"); 705 goto free_channels; 706 } 707 708 err = host1x_syncpt_init(host); 709 if (err) { 710 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 711 goto free_contexts; 712 } 713 714 mutex_init(&host->intr_mutex); 715 716 pm_runtime_enable(&pdev->dev); 717 718 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 719 if (err) 720 goto pm_disable; 721 722 /* the driver's code isn't ready yet for the dynamic RPM */ 723 err = pm_runtime_resume_and_get(&pdev->dev); 724 if (err) 725 goto pm_disable; 726 727 err = host1x_intr_init(host); 728 if (err) { 729 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 730 goto pm_put; 731 } 732 733 host1x_debug_init(host); 734 735 err = host1x_register(host); 736 if (err < 0) 737 goto deinit_debugfs; 738 739 err = devm_of_platform_populate(&pdev->dev); 740 if (err < 0) 741 goto unregister; 742 743 return 0; 744 745 unregister: 746 host1x_unregister(host); 747 deinit_debugfs: 748 host1x_debug_deinit(host); 749 host1x_intr_deinit(host); 750 pm_put: 751 pm_runtime_put_sync_suspend(&pdev->dev); 752 pm_disable: 753 pm_runtime_disable(&pdev->dev); 754 host1x_syncpt_deinit(host); 755 free_contexts: 756 host1x_memory_context_list_free(&host->context_list); 757 free_channels: 758 host1x_channel_list_free(&host->channel_list); 759 iommu_exit: 760 host1x_iommu_exit(host); 761 destroy_cache: 762 host1x_bo_cache_destroy(&host->cache); 763 764 return err; 765 } 766 767 static void host1x_remove(struct platform_device *pdev) 768 { 769 struct host1x *host = platform_get_drvdata(pdev); 770 771 host1x_unregister(host); 772 host1x_debug_deinit(host); 773 774 pm_runtime_force_suspend(&pdev->dev); 775 776 host1x_intr_deinit(host); 777 host1x_syncpt_deinit(host); 778 host1x_memory_context_list_free(&host->context_list); 779 host1x_channel_list_free(&host->channel_list); 780 host1x_iommu_exit(host); 781 host1x_bo_cache_destroy(&host->cache); 782 } 783 784 static int __maybe_unused host1x_runtime_suspend(struct device *dev) 785 { 786 struct host1x *host = dev_get_drvdata(dev); 787 int err; 788 789 host1x_channel_stop_all(host); 790 host1x_intr_stop(host); 791 host1x_syncpt_save(host); 792 793 if (!host->info->skip_reset_assert) { 794 err = reset_control_bulk_assert(host->nresets, host->resets); 795 if (err) { 796 dev_err(dev, "failed to assert reset: %d\n", err); 797 goto resume_host1x; 798 } 799 800 usleep_range(1000, 2000); 801 } 802 803 clk_disable_unprepare(host->clk); 804 reset_control_bulk_release(host->nresets, host->resets); 805 806 return 0; 807 808 resume_host1x: 809 host1x_setup_virtualization_tables(host); 810 host1x_syncpt_restore(host); 811 host1x_intr_start(host); 812 813 return err; 814 } 815 816 static int __maybe_unused host1x_runtime_resume(struct device *dev) 817 { 818 struct host1x *host = dev_get_drvdata(dev); 819 int err; 820 821 err = reset_control_bulk_acquire(host->nresets, host->resets); 822 if (err) { 823 dev_err(dev, "failed to acquire reset: %d\n", err); 824 return err; 825 } 826 827 err = clk_prepare_enable(host->clk); 828 if (err) { 829 dev_err(dev, "failed to enable clock: %d\n", err); 830 goto release_reset; 831 } 832 833 err = reset_control_bulk_deassert(host->nresets, host->resets); 834 if (err < 0) { 835 dev_err(dev, "failed to deassert reset: %d\n", err); 836 goto disable_clk; 837 } 838 839 host1x_setup_virtualization_tables(host); 840 host1x_syncpt_restore(host); 841 host1x_intr_start(host); 842 843 return 0; 844 845 disable_clk: 846 clk_disable_unprepare(host->clk); 847 release_reset: 848 reset_control_bulk_release(host->nresets, host->resets); 849 850 return err; 851 } 852 853 static const struct dev_pm_ops host1x_pm_ops = { 854 SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume, 855 NULL) 856 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 857 }; 858 859 static struct platform_driver tegra_host1x_driver = { 860 .driver = { 861 .name = "tegra-host1x", 862 .of_match_table = host1x_of_match, 863 .pm = &host1x_pm_ops, 864 }, 865 .probe = host1x_probe, 866 .remove = host1x_remove, 867 }; 868 869 static struct platform_driver * const drivers[] = { 870 &tegra_host1x_driver, 871 &tegra_mipi_driver, 872 }; 873 874 static int __init tegra_host1x_init(void) 875 { 876 int err; 877 878 err = bus_register(&host1x_bus_type); 879 if (err < 0) 880 return err; 881 882 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 883 if (err < 0) 884 bus_unregister(&host1x_bus_type); 885 886 return err; 887 } 888 module_init(tegra_host1x_init); 889 890 static void __exit tegra_host1x_exit(void) 891 { 892 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 893 bus_unregister(&host1x_bus_type); 894 } 895 module_exit(tegra_host1x_exit); 896 897 /** 898 * host1x_get_dma_mask() - query the supported DMA mask for host1x 899 * @host1x: host1x instance 900 * 901 * Note that this returns the supported DMA mask for host1x, which can be 902 * different from the applicable DMA mask under certain circumstances. 903 */ 904 u64 host1x_get_dma_mask(struct host1x *host1x) 905 { 906 return host1x->info->dma_mask; 907 } 908 EXPORT_SYMBOL(host1x_get_dma_mask); 909 910 MODULE_SOFTDEP("post: tegra-drm"); 911 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 912 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 913 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 914 MODULE_LICENSE("GPL"); 915