1 /* 2 * Tegra host1x driver 3 * 4 * Copyright (c) 2010-2013, NVIDIA Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/slab.h> 27 28 #define CREATE_TRACE_POINTS 29 #include <trace/events/host1x.h> 30 #undef CREATE_TRACE_POINTS 31 32 #include "bus.h" 33 #include "channel.h" 34 #include "debug.h" 35 #include "dev.h" 36 #include "intr.h" 37 38 #include "hw/host1x01.h" 39 #include "hw/host1x02.h" 40 #include "hw/host1x04.h" 41 #include "hw/host1x05.h" 42 43 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 44 { 45 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 46 47 writel(v, sync_regs + r); 48 } 49 50 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 51 { 52 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 53 54 return readl(sync_regs + r); 55 } 56 57 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 58 { 59 writel(v, ch->regs + r); 60 } 61 62 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 63 { 64 return readl(ch->regs + r); 65 } 66 67 static const struct host1x_info host1x01_info = { 68 .nb_channels = 8, 69 .nb_pts = 32, 70 .nb_mlocks = 16, 71 .nb_bases = 8, 72 .init = host1x01_init, 73 .sync_offset = 0x3000, 74 .dma_mask = DMA_BIT_MASK(32), 75 }; 76 77 static const struct host1x_info host1x02_info = { 78 .nb_channels = 9, 79 .nb_pts = 32, 80 .nb_mlocks = 16, 81 .nb_bases = 12, 82 .init = host1x02_init, 83 .sync_offset = 0x3000, 84 .dma_mask = DMA_BIT_MASK(32), 85 }; 86 87 static const struct host1x_info host1x04_info = { 88 .nb_channels = 12, 89 .nb_pts = 192, 90 .nb_mlocks = 16, 91 .nb_bases = 64, 92 .init = host1x04_init, 93 .sync_offset = 0x2100, 94 .dma_mask = DMA_BIT_MASK(34), 95 }; 96 97 static const struct host1x_info host1x05_info = { 98 .nb_channels = 14, 99 .nb_pts = 192, 100 .nb_mlocks = 16, 101 .nb_bases = 64, 102 .init = host1x05_init, 103 .sync_offset = 0x2100, 104 .dma_mask = DMA_BIT_MASK(34), 105 }; 106 107 static const struct of_device_id host1x_of_match[] = { 108 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 109 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 110 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 111 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 112 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 113 { }, 114 }; 115 MODULE_DEVICE_TABLE(of, host1x_of_match); 116 117 static int host1x_probe(struct platform_device *pdev) 118 { 119 const struct of_device_id *id; 120 struct host1x *host; 121 struct resource *regs; 122 int syncpt_irq; 123 int err; 124 125 id = of_match_device(host1x_of_match, &pdev->dev); 126 if (!id) 127 return -EINVAL; 128 129 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 130 if (!regs) { 131 dev_err(&pdev->dev, "failed to get registers\n"); 132 return -ENXIO; 133 } 134 135 syncpt_irq = platform_get_irq(pdev, 0); 136 if (syncpt_irq < 0) { 137 dev_err(&pdev->dev, "failed to get IRQ\n"); 138 return -ENXIO; 139 } 140 141 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 142 if (!host) 143 return -ENOMEM; 144 145 mutex_init(&host->devices_lock); 146 INIT_LIST_HEAD(&host->devices); 147 INIT_LIST_HEAD(&host->list); 148 host->dev = &pdev->dev; 149 host->info = id->data; 150 151 /* set common host1x device data */ 152 platform_set_drvdata(pdev, host); 153 154 host->regs = devm_ioremap_resource(&pdev->dev, regs); 155 if (IS_ERR(host->regs)) 156 return PTR_ERR(host->regs); 157 158 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 159 160 if (host->info->init) { 161 err = host->info->init(host); 162 if (err) 163 return err; 164 } 165 166 host->clk = devm_clk_get(&pdev->dev, NULL); 167 if (IS_ERR(host->clk)) { 168 dev_err(&pdev->dev, "failed to get clock\n"); 169 err = PTR_ERR(host->clk); 170 return err; 171 } 172 173 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 174 if (IS_ERR(host->rst)) { 175 err = PTR_ERR(host->rst); 176 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 177 return err; 178 } 179 180 if (iommu_present(&platform_bus_type)) { 181 struct iommu_domain_geometry *geometry; 182 unsigned long order; 183 184 host->domain = iommu_domain_alloc(&platform_bus_type); 185 if (!host->domain) 186 return -ENOMEM; 187 188 err = iommu_attach_device(host->domain, &pdev->dev); 189 if (err) 190 goto fail_free_domain; 191 192 geometry = &host->domain->geometry; 193 194 order = __ffs(host->domain->pgsize_bitmap); 195 init_iova_domain(&host->iova, 1UL << order, 196 geometry->aperture_start >> order, 197 geometry->aperture_end >> order); 198 host->iova_end = geometry->aperture_end; 199 } 200 201 err = host1x_channel_list_init(&host->channel_list, 202 host->info->nb_channels); 203 if (err) { 204 dev_err(&pdev->dev, "failed to initialize channel list\n"); 205 goto fail_detach_device; 206 } 207 208 err = clk_prepare_enable(host->clk); 209 if (err < 0) { 210 dev_err(&pdev->dev, "failed to enable clock\n"); 211 goto fail_free_channels; 212 } 213 214 err = reset_control_deassert(host->rst); 215 if (err < 0) { 216 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 217 goto fail_unprepare_disable; 218 } 219 220 err = host1x_syncpt_init(host); 221 if (err) { 222 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 223 goto fail_reset_assert; 224 } 225 226 err = host1x_intr_init(host, syncpt_irq); 227 if (err) { 228 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 229 goto fail_deinit_syncpt; 230 } 231 232 host1x_debug_init(host); 233 234 err = host1x_register(host); 235 if (err < 0) 236 goto fail_deinit_intr; 237 238 return 0; 239 240 fail_deinit_intr: 241 host1x_intr_deinit(host); 242 fail_deinit_syncpt: 243 host1x_syncpt_deinit(host); 244 fail_reset_assert: 245 reset_control_assert(host->rst); 246 fail_unprepare_disable: 247 clk_disable_unprepare(host->clk); 248 fail_free_channels: 249 host1x_channel_list_free(&host->channel_list); 250 fail_detach_device: 251 if (host->domain) { 252 put_iova_domain(&host->iova); 253 iommu_detach_device(host->domain, &pdev->dev); 254 } 255 fail_free_domain: 256 if (host->domain) 257 iommu_domain_free(host->domain); 258 259 return err; 260 } 261 262 static int host1x_remove(struct platform_device *pdev) 263 { 264 struct host1x *host = platform_get_drvdata(pdev); 265 266 host1x_unregister(host); 267 host1x_intr_deinit(host); 268 host1x_syncpt_deinit(host); 269 reset_control_assert(host->rst); 270 clk_disable_unprepare(host->clk); 271 272 if (host->domain) { 273 put_iova_domain(&host->iova); 274 iommu_detach_device(host->domain, &pdev->dev); 275 iommu_domain_free(host->domain); 276 } 277 278 return 0; 279 } 280 281 static struct platform_driver tegra_host1x_driver = { 282 .driver = { 283 .name = "tegra-host1x", 284 .of_match_table = host1x_of_match, 285 }, 286 .probe = host1x_probe, 287 .remove = host1x_remove, 288 }; 289 290 static struct platform_driver * const drivers[] = { 291 &tegra_host1x_driver, 292 &tegra_mipi_driver, 293 }; 294 295 static int __init tegra_host1x_init(void) 296 { 297 int err; 298 299 err = bus_register(&host1x_bus_type); 300 if (err < 0) 301 return err; 302 303 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 304 if (err < 0) 305 bus_unregister(&host1x_bus_type); 306 307 return err; 308 } 309 module_init(tegra_host1x_init); 310 311 static void __exit tegra_host1x_exit(void) 312 { 313 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 314 bus_unregister(&host1x_bus_type); 315 } 316 module_exit(tegra_host1x_exit); 317 318 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 319 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 320 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 321 MODULE_LICENSE("GPL"); 322