1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP DisplayPort Subsystem Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/module.h> 15 #include <linux/of_graph.h> 16 #include <linux/of_reserved_mem.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_modeset_helper.h> 24 #include <drm/drm_module.h> 25 26 #include "zynqmp_disp.h" 27 #include "zynqmp_dp.h" 28 #include "zynqmp_dpsub.h" 29 #include "zynqmp_kms.h" 30 31 /* ----------------------------------------------------------------------------- 32 * Power Management 33 */ 34 35 static int __maybe_unused zynqmp_dpsub_suspend(struct device *dev) 36 { 37 struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev); 38 39 if (!dpsub->drm) 40 return 0; 41 42 return drm_mode_config_helper_suspend(&dpsub->drm->dev); 43 } 44 45 static int __maybe_unused zynqmp_dpsub_resume(struct device *dev) 46 { 47 struct zynqmp_dpsub *dpsub = dev_get_drvdata(dev); 48 49 if (!dpsub->drm) 50 return 0; 51 52 return drm_mode_config_helper_resume(&dpsub->drm->dev); 53 } 54 55 static const struct dev_pm_ops zynqmp_dpsub_pm_ops = { 56 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dpsub_suspend, zynqmp_dpsub_resume) 57 }; 58 59 /* ----------------------------------------------------------------------------- 60 * Probe & Remove 61 */ 62 63 static int zynqmp_dpsub_init_clocks(struct zynqmp_dpsub *dpsub) 64 { 65 int ret; 66 67 dpsub->apb_clk = devm_clk_get(dpsub->dev, "dp_apb_clk"); 68 if (IS_ERR(dpsub->apb_clk)) 69 return PTR_ERR(dpsub->apb_clk); 70 71 ret = clk_prepare_enable(dpsub->apb_clk); 72 if (ret) { 73 dev_err(dpsub->dev, "failed to enable the APB clock\n"); 74 return ret; 75 } 76 77 /* 78 * Try the live PL video clock, and fall back to the PS clock if the 79 * live PL video clock isn't valid. 80 */ 81 dpsub->vid_clk = devm_clk_get(dpsub->dev, "dp_live_video_in_clk"); 82 if (!IS_ERR(dpsub->vid_clk)) 83 dpsub->vid_clk_from_ps = false; 84 else if (PTR_ERR(dpsub->vid_clk) == -EPROBE_DEFER) 85 return PTR_ERR(dpsub->vid_clk); 86 87 if (IS_ERR_OR_NULL(dpsub->vid_clk)) { 88 dpsub->vid_clk = devm_clk_get(dpsub->dev, "dp_vtc_pixel_clk_in"); 89 if (IS_ERR(dpsub->vid_clk)) { 90 dev_err(dpsub->dev, "failed to init any video clock\n"); 91 return PTR_ERR(dpsub->vid_clk); 92 } 93 dpsub->vid_clk_from_ps = true; 94 } 95 96 /* 97 * Try the live PL audio clock, and fall back to the PS clock if the 98 * live PL audio clock isn't valid. Missing audio clock disables audio 99 * but isn't an error. 100 */ 101 dpsub->aud_clk = devm_clk_get(dpsub->dev, "dp_live_audio_aclk"); 102 if (!IS_ERR(dpsub->aud_clk)) { 103 dpsub->aud_clk_from_ps = false; 104 return 0; 105 } 106 107 dpsub->aud_clk = devm_clk_get(dpsub->dev, "dp_aud_clk"); 108 if (!IS_ERR(dpsub->aud_clk)) { 109 dpsub->aud_clk_from_ps = true; 110 return 0; 111 } 112 113 dev_info(dpsub->dev, "audio disabled due to missing clock\n"); 114 return 0; 115 } 116 117 static int zynqmp_dpsub_parse_dt(struct zynqmp_dpsub *dpsub) 118 { 119 struct device_node *np; 120 unsigned int i; 121 122 /* 123 * For backward compatibility with old device trees that don't contain 124 * ports, consider that only the DP output port is connected if no 125 * ports child no exists. 126 */ 127 np = of_get_child_by_name(dpsub->dev->of_node, "ports"); 128 of_node_put(np); 129 if (!np) { 130 dev_warn(dpsub->dev, "missing ports, update DT bindings\n"); 131 dpsub->connected_ports = BIT(ZYNQMP_DPSUB_PORT_OUT_DP); 132 dpsub->dma_enabled = true; 133 return 0; 134 } 135 136 /* Check which ports are connected. */ 137 for (i = 0; i < ZYNQMP_DPSUB_NUM_PORTS; ++i) { 138 struct device_node *np; 139 140 np = of_graph_get_remote_node(dpsub->dev->of_node, i, -1); 141 if (np) { 142 dpsub->connected_ports |= BIT(i); 143 of_node_put(np); 144 } 145 } 146 147 /* Sanity checks. */ 148 if ((dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) && 149 (dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))) { 150 dev_err(dpsub->dev, "only one live video input is supported\n"); 151 return -EINVAL; 152 } 153 154 if ((dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) || 155 (dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))) { 156 if (dpsub->vid_clk_from_ps) { 157 dev_err(dpsub->dev, 158 "live video input requires PL clock\n"); 159 return -EINVAL; 160 } 161 } else { 162 dpsub->dma_enabled = true; 163 } 164 165 if (dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_AUDIO)) 166 dev_warn(dpsub->dev, "live audio unsupported, ignoring\n"); 167 168 if ((dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_OUT_VIDEO)) || 169 (dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_OUT_AUDIO))) 170 dev_warn(dpsub->dev, "output to PL unsupported, ignoring\n"); 171 172 if (!(dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_OUT_DP))) { 173 dev_err(dpsub->dev, "DP output port not connected\n"); 174 return -EINVAL; 175 } 176 177 return 0; 178 } 179 180 void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub) 181 { 182 kfree(dpsub->disp); 183 kfree(dpsub->dp); 184 kfree(dpsub); 185 } 186 187 static int zynqmp_dpsub_probe(struct platform_device *pdev) 188 { 189 struct zynqmp_dpsub *dpsub; 190 int ret; 191 192 /* Allocate private data. */ 193 dpsub = kzalloc(sizeof(*dpsub), GFP_KERNEL); 194 if (!dpsub) 195 return -ENOMEM; 196 197 dpsub->dev = &pdev->dev; 198 platform_set_drvdata(pdev, dpsub); 199 200 ret = dma_set_mask(dpsub->dev, DMA_BIT_MASK(ZYNQMP_DISP_MAX_DMA_BIT)); 201 if (ret) 202 return ret; 203 204 /* Try the reserved memory. Proceed if there's none. */ 205 of_reserved_mem_device_init(&pdev->dev); 206 207 ret = zynqmp_dpsub_init_clocks(dpsub); 208 if (ret < 0) 209 goto err_mem; 210 211 ret = zynqmp_dpsub_parse_dt(dpsub); 212 if (ret < 0) 213 goto err_mem; 214 215 pm_runtime_enable(&pdev->dev); 216 217 /* 218 * DP should be probed first so that the zynqmp_disp can set the output 219 * format accordingly. 220 */ 221 ret = zynqmp_dp_probe(dpsub); 222 if (ret) 223 goto err_pm; 224 225 ret = zynqmp_disp_probe(dpsub); 226 if (ret) 227 goto err_dp; 228 229 drm_bridge_add(dpsub->bridge); 230 231 if (dpsub->dma_enabled) { 232 ret = zynqmp_dpsub_drm_init(dpsub); 233 if (ret) 234 goto err_disp; 235 } 236 237 ret = zynqmp_audio_init(dpsub); 238 if (ret) 239 goto err_drm_cleanup; 240 241 dev_info(&pdev->dev, "ZynqMP DisplayPort Subsystem driver probed"); 242 243 return 0; 244 245 err_drm_cleanup: 246 if (dpsub->drm) 247 zynqmp_dpsub_drm_cleanup(dpsub); 248 err_disp: 249 drm_bridge_remove(dpsub->bridge); 250 zynqmp_disp_remove(dpsub); 251 err_dp: 252 zynqmp_dp_remove(dpsub); 253 err_pm: 254 pm_runtime_disable(&pdev->dev); 255 clk_disable_unprepare(dpsub->apb_clk); 256 err_mem: 257 of_reserved_mem_device_release(&pdev->dev); 258 if (!dpsub->drm) 259 zynqmp_dpsub_release(dpsub); 260 return ret; 261 } 262 263 static void zynqmp_dpsub_remove(struct platform_device *pdev) 264 { 265 struct zynqmp_dpsub *dpsub = platform_get_drvdata(pdev); 266 267 zynqmp_audio_uninit(dpsub); 268 269 if (dpsub->drm) 270 zynqmp_dpsub_drm_cleanup(dpsub); 271 272 drm_bridge_remove(dpsub->bridge); 273 zynqmp_disp_remove(dpsub); 274 zynqmp_dp_remove(dpsub); 275 276 pm_runtime_disable(&pdev->dev); 277 clk_disable_unprepare(dpsub->apb_clk); 278 of_reserved_mem_device_release(&pdev->dev); 279 280 if (!dpsub->drm) 281 zynqmp_dpsub_release(dpsub); 282 } 283 284 static void zynqmp_dpsub_shutdown(struct platform_device *pdev) 285 { 286 struct zynqmp_dpsub *dpsub = platform_get_drvdata(pdev); 287 288 if (!dpsub->drm) 289 return; 290 291 drm_atomic_helper_shutdown(&dpsub->drm->dev); 292 } 293 294 static const struct of_device_id zynqmp_dpsub_of_match[] = { 295 { .compatible = "xlnx,zynqmp-dpsub-1.7", }, 296 { /* end of table */ }, 297 }; 298 MODULE_DEVICE_TABLE(of, zynqmp_dpsub_of_match); 299 300 static struct platform_driver zynqmp_dpsub_driver = { 301 .probe = zynqmp_dpsub_probe, 302 .remove = zynqmp_dpsub_remove, 303 .shutdown = zynqmp_dpsub_shutdown, 304 .driver = { 305 .name = "zynqmp-dpsub", 306 .pm = &zynqmp_dpsub_pm_ops, 307 .of_match_table = zynqmp_dpsub_of_match, 308 }, 309 }; 310 311 drm_module_platform_driver(zynqmp_dpsub_driver); 312 313 MODULE_AUTHOR("Xilinx, Inc."); 314 MODULE_DESCRIPTION("ZynqMP DP Subsystem Driver"); 315 MODULE_LICENSE("GPL v2"); 316