1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP DisplayPort Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/display/drm_dp_helper.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_device.h> 16 #include <drm/drm_edid.h> 17 #include <drm/drm_fourcc.h> 18 #include <drm/drm_modes.h> 19 #include <drm/drm_of.h> 20 21 #include <linux/bitfield.h> 22 #include <linux/clk.h> 23 #include <linux/debugfs.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/io.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/phy/phy.h> 32 #include <linux/reset.h> 33 #include <linux/slab.h> 34 35 #include "zynqmp_disp.h" 36 #include "zynqmp_dp.h" 37 #include "zynqmp_dpsub.h" 38 #include "zynqmp_kms.h" 39 40 static uint zynqmp_dp_aux_timeout_ms = 50; 41 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); 42 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); 43 44 /* 45 * Some sink requires a delay after power on request 46 */ 47 static uint zynqmp_dp_power_on_delay_ms = 4; 48 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); 49 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)"); 50 51 /* Link configuration registers */ 52 #define ZYNQMP_DP_LINK_BW_SET 0x0 53 #define ZYNQMP_DP_LANE_COUNT_SET 0x4 54 #define ZYNQMP_DP_ENHANCED_FRAME_EN 0x8 55 #define ZYNQMP_DP_TRAINING_PATTERN_SET 0xc 56 #define ZYNQMP_DP_LINK_QUAL_PATTERN_SET 0x10 57 #define ZYNQMP_DP_SCRAMBLING_DISABLE 0x14 58 #define ZYNQMP_DP_DOWNSPREAD_CTL 0x18 59 #define ZYNQMP_DP_SOFTWARE_RESET 0x1c 60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1 BIT(0) 61 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2 BIT(1) 62 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3 BIT(2) 63 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4 BIT(3) 64 #define ZYNQMP_DP_SOFTWARE_RESET_AUX BIT(7) 65 #define ZYNQMP_DP_SOFTWARE_RESET_ALL (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \ 66 ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \ 67 ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \ 68 ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \ 69 ZYNQMP_DP_SOFTWARE_RESET_AUX) 70 #define ZYNQMP_DP_COMP_PATTERN_80BIT_1 0x20 71 #define ZYNQMP_DP_COMP_PATTERN_80BIT_2 0x24 72 #define ZYNQMP_DP_COMP_PATTERN_80BIT_3 0x28 73 74 /* Core enable registers */ 75 #define ZYNQMP_DP_TRANSMITTER_ENABLE 0x80 76 #define ZYNQMP_DP_MAIN_STREAM_ENABLE 0x84 77 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET 0xc0 78 #define ZYNQMP_DP_VERSION 0xf8 79 #define ZYNQMP_DP_VERSION_MAJOR_MASK GENMASK(31, 24) 80 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT 24 81 #define ZYNQMP_DP_VERSION_MINOR_MASK GENMASK(23, 16) 82 #define ZYNQMP_DP_VERSION_MINOR_SHIFT 16 83 #define ZYNQMP_DP_VERSION_REVISION_MASK GENMASK(15, 12) 84 #define ZYNQMP_DP_VERSION_REVISION_SHIFT 12 85 #define ZYNQMP_DP_VERSION_PATCH_MASK GENMASK(11, 8) 86 #define ZYNQMP_DP_VERSION_PATCH_SHIFT 8 87 #define ZYNQMP_DP_VERSION_INTERNAL_MASK GENMASK(7, 0) 88 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT 0 89 90 /* Core ID registers */ 91 #define ZYNQMP_DP_CORE_ID 0xfc 92 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK GENMASK(31, 24) 93 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT 24 94 #define ZYNQMP_DP_CORE_ID_MINOR_MASK GENMASK(23, 16) 95 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT 16 96 #define ZYNQMP_DP_CORE_ID_REVISION_MASK GENMASK(15, 8) 97 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT 8 98 #define ZYNQMP_DP_CORE_ID_DIRECTION GENMASK(1) 99 100 /* AUX channel interface registers */ 101 #define ZYNQMP_DP_AUX_COMMAND 0x100 102 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT 8 103 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY BIT(12) 104 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT 0 105 #define ZYNQMP_DP_AUX_WRITE_FIFO 0x104 106 #define ZYNQMP_DP_AUX_ADDRESS 0x108 107 #define ZYNQMP_DP_AUX_CLK_DIVIDER 0x10c 108 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT 8 109 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE 0x130 110 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD BIT(0) 111 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST BIT(1) 112 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY BIT(2) 113 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT BIT(3) 114 #define ZYNQMP_DP_AUX_REPLY_DATA 0x134 115 #define ZYNQMP_DP_AUX_REPLY_CODE 0x138 116 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK (0) 117 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK BIT(0) 118 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER BIT(1) 119 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK (0) 120 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK BIT(2) 121 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER BIT(3) 122 #define ZYNQMP_DP_AUX_REPLY_COUNT 0x13c 123 #define ZYNQMP_DP_REPLY_DATA_COUNT 0x148 124 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK 0xff 125 #define ZYNQMP_DP_INT_STATUS 0x3a0 126 #define ZYNQMP_DP_INT_MASK 0x3a4 127 #define ZYNQMP_DP_INT_EN 0x3a8 128 #define ZYNQMP_DP_INT_DS 0x3ac 129 #define ZYNQMP_DP_INT_HPD_IRQ BIT(0) 130 #define ZYNQMP_DP_INT_HPD_EVENT BIT(1) 131 #define ZYNQMP_DP_INT_REPLY_RECEIVED BIT(2) 132 #define ZYNQMP_DP_INT_REPLY_TIMEOUT BIT(3) 133 #define ZYNQMP_DP_INT_HPD_PULSE_DET BIT(4) 134 #define ZYNQMP_DP_INT_EXT_PKT_TXD BIT(5) 135 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW BIT(12) 136 #define ZYNQMP_DP_INT_VBLANK_START BIT(13) 137 #define ZYNQMP_DP_INT_PIXEL1_MATCH BIT(14) 138 #define ZYNQMP_DP_INT_PIXEL0_MATCH BIT(15) 139 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK 0x3f0000 140 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK 0xfc00000 141 #define ZYNQMP_DP_INT_CUST_TS_2 BIT(28) 142 #define ZYNQMP_DP_INT_CUST_TS BIT(29) 143 #define ZYNQMP_DP_INT_EXT_VSYNC_TS BIT(30) 144 #define ZYNQMP_DP_INT_VSYNC_TS BIT(31) 145 #define ZYNQMP_DP_INT_ALL (ZYNQMP_DP_INT_HPD_IRQ | \ 146 ZYNQMP_DP_INT_HPD_EVENT | \ 147 ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \ 148 ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) 149 150 /* Main stream attribute registers */ 151 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL 0x180 152 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL 0x184 153 #define ZYNQMP_DP_MAIN_STREAM_POLARITY 0x188 154 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0 155 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1 156 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH 0x18c 157 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH 0x190 158 #define ZYNQMP_DP_MAIN_STREAM_HRES 0x194 159 #define ZYNQMP_DP_MAIN_STREAM_VRES 0x198 160 #define ZYNQMP_DP_MAIN_STREAM_HSTART 0x19c 161 #define ZYNQMP_DP_MAIN_STREAM_VSTART 0x1a0 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0 0x1a4 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK BIT(0) 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB (0 << 1) 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422 (5 << 1) 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444 (6 << 1) 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK (7 << 1) 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE BIT(3) 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR BIT(4) 170 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6 (0 << 5) 171 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8 (1 << 5) 172 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10 (2 << 5) 173 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12 (3 << 5) 174 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16 (4 << 5) 175 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK (7 << 5) 176 #define ZYNQMP_DP_MAIN_STREAM_MISC1 0x1a8 177 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN BIT(7) 178 #define ZYNQMP_DP_MAIN_STREAM_M_VID 0x1ac 179 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE 0x1b0 180 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF 64 181 #define ZYNQMP_DP_MAIN_STREAM_N_VID 0x1b4 182 #define ZYNQMP_DP_USER_PIX_WIDTH 0x1b8 183 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE 0x1bc 184 #define ZYNQMP_DP_MIN_BYTES_PER_TU 0x1c4 185 #define ZYNQMP_DP_FRAC_BYTES_PER_TU 0x1c8 186 #define ZYNQMP_DP_INIT_WAIT 0x1cc 187 188 /* PHY configuration and status registers */ 189 #define ZYNQMP_DP_PHY_RESET 0x200 190 #define ZYNQMP_DP_PHY_RESET_PHY_RESET BIT(0) 191 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET BIT(1) 192 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET BIT(8) 193 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET BIT(9) 194 #define ZYNQMP_DP_PHY_RESET_ALL_RESET (ZYNQMP_DP_PHY_RESET_PHY_RESET | \ 195 ZYNQMP_DP_PHY_RESET_GTTX_RESET | \ 196 ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \ 197 ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET) 198 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0 0x210 199 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1 0x214 200 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2 0x218 201 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3 0x21c 202 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0 0x220 203 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1 0x224 204 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2 0x228 205 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3 0x22c 206 #define ZYNQMP_DP_PHY_CLOCK_SELECT 0x234 207 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G 0x1 208 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G 0x3 209 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G 0x5 210 #define ZYNQMP_DP_TX_PHY_POWER_DOWN 0x238 211 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0 BIT(0) 212 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1 BIT(1) 213 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2 BIT(2) 214 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3 BIT(3) 215 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL 0xf 216 #define ZYNQMP_DP_TRANSMIT_PRBS7 0x230 217 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0 0x23c 218 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1 0x240 219 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2 0x244 220 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3 0x248 221 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0 0x24c 222 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1 0x250 223 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2 0x254 224 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3 0x258 225 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c 226 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250 227 #define ZYNQMP_DP_PHY_STATUS 0x280 228 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT 4 229 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED BIT(6) 230 231 /* Audio registers */ 232 #define ZYNQMP_DP_TX_AUDIO_CONTROL 0x300 233 #define ZYNQMP_DP_TX_AUDIO_CHANNELS 0x304 234 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA 0x308 235 #define ZYNQMP_DP_TX_M_AUD 0x328 236 #define ZYNQMP_DP_TX_N_AUD 0x32c 237 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA 0x330 238 239 #define ZYNQMP_DP_MAX_LANES 2 240 #define ZYNQMP_MAX_FREQ 3000000 241 242 #define DP_REDUCED_BIT_RATE 162000 243 #define DP_HIGH_BIT_RATE 270000 244 #define DP_HIGH_BIT_RATE2 540000 245 #define DP_MAX_TRAINING_TRIES 5 246 #define DP_V1_2 0x12 247 248 /** 249 * struct zynqmp_dp_link_config - Common link config between source and sink 250 * @max_rate: maximum link rate 251 * @max_lanes: maximum number of lanes 252 */ 253 struct zynqmp_dp_link_config { 254 int max_rate; 255 u8 max_lanes; 256 }; 257 258 /** 259 * struct zynqmp_dp_mode - Configured mode of DisplayPort 260 * @bw_code: code for bandwidth(link rate) 261 * @lane_cnt: number of lanes 262 * @pclock: pixel clock frequency of current mode 263 * @fmt: format identifier string 264 */ 265 struct zynqmp_dp_mode { 266 const char *fmt; 267 int pclock; 268 u8 bw_code; 269 u8 lane_cnt; 270 }; 271 272 /** 273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS 274 * @misc0: misc0 configuration (per DP v1.2 spec) 275 * @misc1: misc1 configuration (per DP v1.2 spec) 276 * @bpp: bits per pixel 277 */ 278 struct zynqmp_dp_config { 279 u8 misc0; 280 u8 misc1; 281 u8 bpp; 282 }; 283 284 /** 285 * enum test_pattern - Test patterns for test testing 286 * @TEST_VIDEO: Use regular video input 287 * @TEST_SYMBOL_ERROR: Symbol error measurement pattern 288 * @TEST_PRBS7: Output of the PRBS7 (x^7 + x^6 + 1) polynomial 289 * @TEST_80BIT_CUSTOM: A custom 80-bit pattern 290 * @TEST_CP2520: HBR2 compliance eye pattern 291 * @TEST_TPS1: Link training symbol pattern TPS1 (/D10.2/) 292 * @TEST_TPS2: Link training symbol pattern TPS2 293 * @TEST_TPS3: Link training symbol pattern TPS3 (for HBR2) 294 */ 295 enum test_pattern { 296 TEST_VIDEO, 297 TEST_TPS1, 298 TEST_TPS2, 299 TEST_TPS3, 300 TEST_SYMBOL_ERROR, 301 TEST_PRBS7, 302 TEST_80BIT_CUSTOM, 303 TEST_CP2520, 304 }; 305 306 static const char *const test_pattern_str[] = { 307 [TEST_VIDEO] = "video", 308 [TEST_TPS1] = "tps1", 309 [TEST_TPS2] = "tps2", 310 [TEST_TPS3] = "tps3", 311 [TEST_SYMBOL_ERROR] = "symbol-error", 312 [TEST_PRBS7] = "prbs7", 313 [TEST_80BIT_CUSTOM] = "80bit-custom", 314 [TEST_CP2520] = "cp2520", 315 }; 316 317 /** 318 * struct zynqmp_dp_test - Configuration for test mode 319 * @pattern: The test pattern 320 * @enhanced: Use enhanced framing 321 * @downspread: Use SSC 322 * @active: Whether test mode is active 323 * @custom: Custom pattern for %TEST_80BIT_CUSTOM 324 * @train_set: Voltage/preemphasis settings 325 * @bw_code: Bandwidth code for the link 326 * @link_cnt: Number of lanes 327 */ 328 struct zynqmp_dp_test { 329 enum test_pattern pattern; 330 bool enhanced, downspread, active; 331 u8 custom[10]; 332 u8 train_set[ZYNQMP_DP_MAX_LANES]; 333 u8 bw_code; 334 u8 link_cnt; 335 }; 336 337 /** 338 * struct zynqmp_dp_train_set_priv - Private data for train_set debugfs files 339 * @dp: DisplayPort IP core structure 340 * @lane: The lane for this file 341 */ 342 struct zynqmp_dp_train_set_priv { 343 struct zynqmp_dp *dp; 344 int lane; 345 }; 346 347 /** 348 * struct zynqmp_dp - Xilinx DisplayPort core 349 * @dev: device structure 350 * @dpsub: Display subsystem 351 * @iomem: device I/O memory for register access 352 * @reset: reset controller 353 * @lock: Mutex protecting this struct and register access (but not AUX) 354 * @irq: irq 355 * @bridge: DRM bridge for the DP encoder 356 * @test: Configuration for test mode 357 * @config: IP core configuration from DTS 358 * @aux: aux channel 359 * @aux_done: Completed when we get an AUX reply or timeout 360 * @ignore_aux_errors: If set, AUX errors are suppressed 361 * @phy: PHY handles for DP lanes 362 * @num_lanes: number of enabled phy lanes 363 * @hpd_work: hot plug detection worker 364 * @hpd_irq_work: hot plug detection IRQ worker 365 * @ignore_hpd: If set, HPD events and IRQs are ignored 366 * @status: connection status 367 * @enabled: flag to indicate if the device is enabled 368 * @dpcd: DP configuration data from currently connected sink device 369 * @link_config: common link configuration between IP core and sink device 370 * @mode: current mode between IP core and sink device 371 * @train_set: set of training data 372 * @debugfs_train_set: Debugfs private data for @train_set 373 * 374 * @lock covers the link configuration in this struct and the device's 375 * registers. It does not cover @aux or @ignore_aux_errors. It is not strictly 376 * required for any of the members which are only modified at probe/remove time 377 * (e.g. @dev). 378 */ 379 struct zynqmp_dp { 380 struct drm_dp_aux aux; 381 struct drm_bridge bridge; 382 struct work_struct hpd_work; 383 struct work_struct hpd_irq_work; 384 struct completion aux_done; 385 struct mutex lock; 386 387 struct device *dev; 388 struct zynqmp_dpsub *dpsub; 389 void __iomem *iomem; 390 struct reset_control *reset; 391 struct phy *phy[ZYNQMP_DP_MAX_LANES]; 392 393 enum drm_connector_status status; 394 int irq; 395 bool enabled; 396 bool ignore_aux_errors; 397 bool ignore_hpd; 398 399 struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; 400 struct zynqmp_dp_mode mode; 401 struct zynqmp_dp_link_config link_config; 402 struct zynqmp_dp_test test; 403 struct zynqmp_dp_config config; 404 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 405 u8 train_set[ZYNQMP_DP_MAX_LANES]; 406 u8 num_lanes; 407 }; 408 409 static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge) 410 { 411 return container_of(bridge, struct zynqmp_dp, bridge); 412 } 413 414 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val) 415 { 416 writel(val, dp->iomem + offset); 417 } 418 419 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset) 420 { 421 return readl(dp->iomem + offset); 422 } 423 424 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr) 425 { 426 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr); 427 } 428 429 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set) 430 { 431 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set); 432 } 433 434 /* ----------------------------------------------------------------------------- 435 * PHY Handling 436 */ 437 438 #define RST_TIMEOUT_MS 1000 439 440 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert) 441 { 442 unsigned long timeout; 443 444 if (assert) 445 reset_control_assert(dp->reset); 446 else 447 reset_control_deassert(dp->reset); 448 449 /* Wait for the (de)assert to complete. */ 450 timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS); 451 while (!time_after_eq(jiffies, timeout)) { 452 bool status = !!reset_control_status(dp->reset); 453 454 if (assert == status) 455 return 0; 456 457 cpu_relax(); 458 } 459 460 dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert"); 461 return -ETIMEDOUT; 462 } 463 464 /** 465 * zynqmp_dp_phy_init - Initialize the phy 466 * @dp: DisplayPort IP core structure 467 * 468 * Initialize the phy. 469 * 470 * Return: 0 if the phy instances are initialized correctly, or the error code 471 * returned from the callee functions. 472 */ 473 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp) 474 { 475 int ret; 476 int i; 477 478 for (i = 0; i < dp->num_lanes; i++) { 479 ret = phy_init(dp->phy[i]); 480 if (ret) { 481 dev_err(dp->dev, "failed to init phy lane %d\n", i); 482 return ret; 483 } 484 } 485 486 zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); 487 488 /* 489 * Power on lanes in reverse order as only lane 0 waits for the PLL to 490 * lock. 491 */ 492 for (i = dp->num_lanes - 1; i >= 0; i--) { 493 ret = phy_power_on(dp->phy[i]); 494 if (ret) { 495 dev_err(dp->dev, "failed to power on phy lane %d\n", i); 496 return ret; 497 } 498 } 499 500 return 0; 501 } 502 503 /** 504 * zynqmp_dp_phy_exit - Exit the phy 505 * @dp: DisplayPort IP core structure 506 * 507 * Exit the phy. 508 */ 509 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp) 510 { 511 unsigned int i; 512 int ret; 513 514 for (i = 0; i < dp->num_lanes; i++) { 515 ret = phy_power_off(dp->phy[i]); 516 if (ret) 517 dev_err(dp->dev, "failed to power off phy(%d) %d\n", i, 518 ret); 519 } 520 521 for (i = 0; i < dp->num_lanes; i++) { 522 ret = phy_exit(dp->phy[i]); 523 if (ret) 524 dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret); 525 } 526 } 527 528 /** 529 * zynqmp_dp_phy_probe - Probe the PHYs 530 * @dp: DisplayPort IP core structure 531 * 532 * Probe PHYs for all lanes. Less PHYs may be available than the number of 533 * lanes, which is not considered an error as long as at least one PHY is 534 * found. The caller can check dp->num_lanes to check how many PHYs were found. 535 * 536 * Return: 537 * * 0 - Success 538 * * -ENXIO - No PHY found 539 * * -EPROBE_DEFER - Probe deferral requested 540 * * Other negative value - PHY retrieval failure 541 */ 542 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp) 543 { 544 unsigned int i; 545 546 for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) { 547 char phy_name[16]; 548 struct phy *phy; 549 550 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i); 551 phy = devm_phy_get(dp->dev, phy_name); 552 553 if (IS_ERR(phy)) { 554 switch (PTR_ERR(phy)) { 555 case -ENODEV: 556 if (dp->num_lanes) 557 return 0; 558 559 dev_err(dp->dev, "no PHY found\n"); 560 return -ENXIO; 561 562 case -EPROBE_DEFER: 563 return -EPROBE_DEFER; 564 565 default: 566 dev_err(dp->dev, "failed to get PHY lane %u\n", 567 i); 568 return PTR_ERR(phy); 569 } 570 } 571 572 dp->phy[i] = phy; 573 dp->num_lanes++; 574 } 575 576 return 0; 577 } 578 579 /** 580 * zynqmp_dp_phy_ready - Check if PHY is ready 581 * @dp: DisplayPort IP core structure 582 * 583 * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. 584 * This amount of delay was suggested by IP designer. 585 * 586 * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready. 587 */ 588 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp) 589 { 590 u32 i, reg, ready; 591 592 ready = (1 << dp->num_lanes) - 1; 593 594 /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */ 595 for (i = 0; ; i++) { 596 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS); 597 if ((reg & ready) == ready) 598 return 0; 599 600 if (i == 100) { 601 dev_err(dp->dev, "PHY isn't ready\n"); 602 return -ENODEV; 603 } 604 605 usleep_range(1000, 1100); 606 } 607 608 return 0; 609 } 610 611 /* ----------------------------------------------------------------------------- 612 * DisplayPort Link Training 613 */ 614 615 /** 616 * zynqmp_dp_max_rate - Calculate and return available max pixel clock 617 * @link_rate: link rate (Kilo-bytes / sec) 618 * @lane_num: number of lanes 619 * @bpp: bits per pixel 620 * 621 * Return: max pixel clock (KHz) supported by current link config. 622 */ 623 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp) 624 { 625 return link_rate * lane_num * 8 / bpp; 626 } 627 628 /** 629 * zynqmp_dp_mode_configure - Configure the link values 630 * @dp: DisplayPort IP core structure 631 * @pclock: pixel clock for requested display mode 632 * @current_bw: current link rate 633 * 634 * Find the link configuration values, rate and lane count for requested pixel 635 * clock @pclock. The @pclock is stored in the mode to be used in other 636 * functions later. The returned rate is downshifted from the current rate 637 * @current_bw. 638 * 639 * Return: Current link rate code, or -EINVAL. 640 */ 641 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, 642 u8 current_bw) 643 { 644 int max_rate = dp->link_config.max_rate; 645 u8 bw_code; 646 u8 max_lanes = dp->link_config.max_lanes; 647 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate); 648 u8 bpp = dp->config.bpp; 649 u8 lane_cnt; 650 651 /* Downshift from current bandwidth */ 652 switch (current_bw) { 653 case DP_LINK_BW_5_4: 654 bw_code = DP_LINK_BW_2_7; 655 break; 656 case DP_LINK_BW_2_7: 657 bw_code = DP_LINK_BW_1_62; 658 break; 659 case DP_LINK_BW_1_62: 660 dev_err(dp->dev, "can't downshift. already lowest link rate\n"); 661 return -EINVAL; 662 default: 663 /* If not given, start with max supported */ 664 bw_code = max_link_rate_code; 665 break; 666 } 667 668 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { 669 int bw; 670 u32 rate; 671 672 bw = drm_dp_bw_code_to_link_rate(bw_code); 673 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp); 674 if (pclock <= rate) { 675 dp->mode.bw_code = bw_code; 676 dp->mode.lane_cnt = lane_cnt; 677 dp->mode.pclock = pclock; 678 return dp->mode.bw_code; 679 } 680 } 681 682 dev_err(dp->dev, "failed to configure link values\n"); 683 684 return -EINVAL; 685 } 686 687 /** 688 * zynqmp_dp_adjust_train - Adjust train values 689 * @dp: DisplayPort IP core structure 690 * @link_status: link status from sink which contains requested training values 691 */ 692 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp, 693 u8 link_status[DP_LINK_STATUS_SIZE]) 694 { 695 u8 *train_set = dp->train_set; 696 u8 i; 697 698 for (i = 0; i < dp->mode.lane_cnt; i++) { 699 u8 voltage = drm_dp_get_adjust_request_voltage(link_status, i); 700 u8 preemphasis = 701 drm_dp_get_adjust_request_pre_emphasis(link_status, i); 702 703 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3) 704 voltage |= DP_TRAIN_MAX_SWING_REACHED; 705 706 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2) 707 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 708 709 train_set[i] = voltage | preemphasis; 710 } 711 } 712 713 /** 714 * zynqmp_dp_update_vs_emph - Update the training values 715 * @dp: DisplayPort IP core structure 716 * @train_set: A set of training values 717 * 718 * Update the training values based on the request from sink. The mapped values 719 * are predefined, and values(vs, pe, pc) are from the device manual. 720 * 721 * Return: 0 if vs and emph are updated successfully, or the error code returned 722 * by drm_dp_dpcd_write(). 723 */ 724 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set) 725 { 726 unsigned int i; 727 int ret; 728 729 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, 730 dp->mode.lane_cnt); 731 if (ret < 0) 732 return ret; 733 734 for (i = 0; i < dp->mode.lane_cnt; i++) { 735 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4; 736 union phy_configure_opts opts = { 0 }; 737 u8 train = train_set[i]; 738 739 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK) 740 >> DP_TRAIN_VOLTAGE_SWING_SHIFT; 741 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) 742 >> DP_TRAIN_PRE_EMPHASIS_SHIFT; 743 744 phy_configure(dp->phy[i], &opts); 745 746 zynqmp_dp_write(dp, reg, 0x2); 747 } 748 749 return 0; 750 } 751 752 /** 753 * zynqmp_dp_link_train_cr - Train clock recovery 754 * @dp: DisplayPort IP core structure 755 * 756 * Return: 0 if clock recovery train is done successfully, or corresponding 757 * error code. 758 */ 759 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) 760 { 761 u8 link_status[DP_LINK_STATUS_SIZE]; 762 u8 lane_cnt = dp->mode.lane_cnt; 763 u8 vs = 0, tries = 0; 764 u16 max_tries, i; 765 bool cr_done; 766 int ret; 767 768 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, 769 DP_TRAINING_PATTERN_1); 770 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 771 DP_TRAINING_PATTERN_1 | 772 DP_LINK_SCRAMBLING_DISABLE); 773 if (ret < 0) 774 return ret; 775 776 /* 777 * 256 loops should be maximum iterations for 4 lanes and 4 values. 778 * So, This loop should exit before 512 iterations 779 */ 780 for (max_tries = 0; max_tries < 512; max_tries++) { 781 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set); 782 if (ret) 783 return ret; 784 785 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); 786 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); 787 if (ret < 0) 788 return ret; 789 790 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt); 791 if (cr_done) 792 break; 793 794 for (i = 0; i < lane_cnt; i++) 795 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) 796 break; 797 if (i == lane_cnt) 798 break; 799 800 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) 801 tries++; 802 else 803 tries = 0; 804 805 if (tries == DP_MAX_TRAINING_TRIES) 806 break; 807 808 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 809 zynqmp_dp_adjust_train(dp, link_status); 810 } 811 812 if (!cr_done) 813 return -EIO; 814 815 return 0; 816 } 817 818 /** 819 * zynqmp_dp_link_train_ce - Train channel equalization 820 * @dp: DisplayPort IP core structure 821 * 822 * Return: 0 if channel equalization train is done successfully, or 823 * corresponding error code. 824 */ 825 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) 826 { 827 u8 link_status[DP_LINK_STATUS_SIZE]; 828 u8 lane_cnt = dp->mode.lane_cnt; 829 u32 pat, tries; 830 int ret; 831 bool ce_done; 832 833 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && 834 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) 835 pat = DP_TRAINING_PATTERN_3; 836 else 837 pat = DP_TRAINING_PATTERN_2; 838 839 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat); 840 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 841 pat | DP_LINK_SCRAMBLING_DISABLE); 842 if (ret < 0) 843 return ret; 844 845 for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) { 846 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set); 847 if (ret) 848 return ret; 849 850 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); 851 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); 852 if (ret < 0) 853 return ret; 854 855 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt); 856 if (ce_done) 857 break; 858 859 zynqmp_dp_adjust_train(dp, link_status); 860 } 861 862 if (!ce_done) 863 return -EIO; 864 865 return 0; 866 } 867 868 /** 869 * zynqmp_dp_setup() - Set up major link parameters 870 * @dp: DisplayPort IP core structure 871 * @bw_code: The link bandwidth as a multiple of 270 MHz 872 * @lane_cnt: The number of lanes to use 873 * @enhanced: Use enhanced framing 874 * @downspread: Enable spread-spectrum clocking 875 * 876 * Return: 0 on success, or -errno on failure 877 */ 878 static int zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, 879 bool enhanced, bool downspread) 880 { 881 u32 reg; 882 u8 aux_lane_cnt = lane_cnt; 883 int ret; 884 885 zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt); 886 if (enhanced) { 887 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1); 888 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 889 } 890 891 if (downspread) { 892 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1); 893 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 894 DP_SPREAD_AMP_0_5); 895 } else { 896 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0); 897 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0); 898 } 899 900 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt); 901 if (ret < 0) { 902 dev_err(dp->dev, "failed to set lane count\n"); 903 return ret; 904 } 905 906 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 907 DP_SET_ANSI_8B10B); 908 if (ret < 0) { 909 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n"); 910 return ret; 911 } 912 913 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code); 914 if (ret < 0) { 915 dev_err(dp->dev, "failed to set DP bandwidth\n"); 916 return ret; 917 } 918 919 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code); 920 switch (bw_code) { 921 case DP_LINK_BW_1_62: 922 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G; 923 break; 924 case DP_LINK_BW_2_7: 925 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G; 926 break; 927 case DP_LINK_BW_5_4: 928 default: 929 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G; 930 break; 931 } 932 933 zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg); 934 return zynqmp_dp_phy_ready(dp); 935 } 936 937 /** 938 * zynqmp_dp_train - Train the link 939 * @dp: DisplayPort IP core structure 940 * 941 * Return: 0 if all trains are done successfully, or corresponding error code. 942 */ 943 static int zynqmp_dp_train(struct zynqmp_dp *dp) 944 { 945 int ret; 946 947 ret = zynqmp_dp_setup(dp, dp->mode.bw_code, dp->mode.lane_cnt, 948 drm_dp_enhanced_frame_cap(dp->dpcd), 949 dp->dpcd[DP_MAX_DOWNSPREAD] & 950 DP_MAX_DOWNSPREAD_0_5); 951 if (ret) 952 return ret; 953 954 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1); 955 memset(dp->train_set, 0, sizeof(dp->train_set)); 956 ret = zynqmp_dp_link_train_cr(dp); 957 if (ret) 958 return ret; 959 960 ret = zynqmp_dp_link_train_ce(dp); 961 if (ret) 962 return ret; 963 964 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 965 DP_TRAINING_PATTERN_DISABLE); 966 if (ret < 0) { 967 dev_err(dp->dev, "failed to disable training pattern\n"); 968 return ret; 969 } 970 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, 971 DP_TRAINING_PATTERN_DISABLE); 972 973 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0); 974 975 return 0; 976 } 977 978 /** 979 * zynqmp_dp_train_loop - Downshift the link rate during training 980 * @dp: DisplayPort IP core structure 981 * 982 * Train the link by downshifting the link rate if training is not successful. 983 */ 984 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp) 985 { 986 struct zynqmp_dp_mode *mode = &dp->mode; 987 u8 bw = mode->bw_code; 988 int ret; 989 990 do { 991 if (dp->status == connector_status_disconnected || 992 !dp->enabled) 993 return; 994 995 ret = zynqmp_dp_train(dp); 996 if (!ret) 997 return; 998 999 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw); 1000 if (ret < 0) 1001 goto err_out; 1002 1003 bw = ret; 1004 } while (bw >= DP_LINK_BW_1_62); 1005 1006 err_out: 1007 dev_err(dp->dev, "failed to train the DP link\n"); 1008 } 1009 1010 /* ----------------------------------------------------------------------------- 1011 * DisplayPort AUX 1012 */ 1013 1014 #define AUX_READ_BIT 0x1 1015 1016 /** 1017 * zynqmp_dp_aux_cmd_submit - Submit aux command 1018 * @dp: DisplayPort IP core structure 1019 * @cmd: aux command 1020 * @addr: aux address 1021 * @buf: buffer for command data 1022 * @bytes: number of bytes for @buf 1023 * @reply: reply code to be returned 1024 * 1025 * Submit an aux command. All aux related commands, native or i2c aux 1026 * read/write, are submitted through this function. The function is mapped to 1027 * the transfer function of struct drm_dp_aux. This function involves in 1028 * multiple register reads/writes, thus synchronization is needed, and it is 1029 * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep 1030 * if there's no immediate reply to the command submission. The reply code is 1031 * returned at @reply if @reply != NULL. 1032 * 1033 * Return: 0 if the command is submitted properly, or corresponding error code: 1034 * -EBUSY when there is any request already being processed 1035 * -ETIMEDOUT when receiving reply is timed out 1036 * -EIO when received bytes are less than requested 1037 */ 1038 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, 1039 u8 *buf, u8 bytes, u8 *reply) 1040 { 1041 bool is_read = (cmd & AUX_READ_BIT) ? true : false; 1042 unsigned long time_left; 1043 u32 reg, i; 1044 1045 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1046 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST) 1047 return -EBUSY; 1048 1049 reinit_completion(&dp->aux_done); 1050 1051 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr); 1052 if (!is_read) 1053 for (i = 0; i < bytes; i++) 1054 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO, 1055 buf[i]); 1056 1057 reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT; 1058 if (!buf || !bytes) 1059 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY; 1060 else 1061 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT; 1062 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg); 1063 1064 /* Wait for reply to be delivered upto 2ms */ 1065 time_left = wait_for_completion_timeout(&dp->aux_done, 1066 msecs_to_jiffies(2)); 1067 if (!time_left) 1068 return -ETIMEDOUT; 1069 1070 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1071 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT) 1072 return -ETIMEDOUT; 1073 1074 reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE); 1075 if (reply) 1076 *reply = reg; 1077 1078 if (is_read && 1079 (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK || 1080 reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) { 1081 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT); 1082 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes) 1083 return -EIO; 1084 1085 for (i = 0; i < bytes; i++) 1086 buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA); 1087 } 1088 1089 return 0; 1090 } 1091 1092 static ssize_t 1093 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1094 { 1095 struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux); 1096 int ret; 1097 unsigned int i, iter; 1098 1099 /* Number of loops = timeout in msec / aux delay (400 usec) */ 1100 iter = zynqmp_dp_aux_timeout_ms * 1000 / 400; 1101 iter = iter ? iter : 1; 1102 1103 for (i = 0; i < iter; i++) { 1104 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address, 1105 msg->buffer, msg->size, 1106 &msg->reply); 1107 if (!ret) { 1108 dev_vdbg(dp->dev, "aux %d retries\n", i); 1109 return msg->size; 1110 } 1111 1112 if (dp->status == connector_status_disconnected) { 1113 dev_dbg(dp->dev, "no connected aux device\n"); 1114 if (dp->ignore_aux_errors) 1115 goto fake_response; 1116 return -ENODEV; 1117 } 1118 1119 usleep_range(400, 500); 1120 } 1121 1122 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret); 1123 1124 if (!dp->ignore_aux_errors) 1125 return ret; 1126 1127 fake_response: 1128 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 1129 memset(msg->buffer, 0, msg->size); 1130 return msg->size; 1131 } 1132 1133 /** 1134 * zynqmp_dp_aux_init - Initialize and register the DP AUX 1135 * @dp: DisplayPort IP core structure 1136 * 1137 * Program the AUX clock divider and filter and register the DP AUX adapter. 1138 * 1139 * Return: 0 on success, error value otherwise 1140 */ 1141 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp) 1142 { 1143 unsigned long rate; 1144 unsigned int w; 1145 1146 /* 1147 * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles 1148 * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32, 1149 * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs, 1150 * compute the w / 8 value corresponding to 0.4µs rounded up, and make 1151 * sure it stays below 0.6µs and within the allowable values. 1152 */ 1153 rate = clk_get_rate(dp->dpsub->apb_clk); 1154 w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8; 1155 if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) { 1156 dev_err(dp->dev, "aclk frequency too high\n"); 1157 return -EINVAL; 1158 } 1159 1160 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER, 1161 (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) | 1162 (rate / (1000 * 1000))); 1163 1164 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_REPLY_RECEIVED | 1165 ZYNQMP_DP_INT_REPLY_TIMEOUT); 1166 1167 dp->aux.name = "ZynqMP DP AUX"; 1168 dp->aux.dev = dp->dev; 1169 dp->aux.drm_dev = dp->bridge.dev; 1170 dp->aux.transfer = zynqmp_dp_aux_transfer; 1171 1172 return drm_dp_aux_register(&dp->aux); 1173 } 1174 1175 /** 1176 * zynqmp_dp_aux_cleanup - Cleanup the DP AUX 1177 * @dp: DisplayPort IP core structure 1178 * 1179 * Unregister the DP AUX adapter. 1180 */ 1181 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp) 1182 { 1183 drm_dp_aux_unregister(&dp->aux); 1184 1185 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_REPLY_RECEIVED | 1186 ZYNQMP_DP_INT_REPLY_TIMEOUT); 1187 } 1188 1189 /* ----------------------------------------------------------------------------- 1190 * DisplayPort Generic Support 1191 */ 1192 1193 /** 1194 * zynqmp_dp_update_misc - Write the misc registers 1195 * @dp: DisplayPort IP core structure 1196 * 1197 * The misc register values are stored in the structure, and this 1198 * function applies the values into the registers. 1199 */ 1200 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp) 1201 { 1202 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0); 1203 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1); 1204 } 1205 1206 /** 1207 * zynqmp_dp_set_format - Set the input format 1208 * @dp: DisplayPort IP core structure 1209 * @info: Display info 1210 * @format: input format 1211 * @bpc: bits per component 1212 * 1213 * Update misc register values based on input @format and @bpc. 1214 * 1215 * Return: 0 on success, or -EINVAL. 1216 */ 1217 static int zynqmp_dp_set_format(struct zynqmp_dp *dp, 1218 const struct drm_display_info *info, 1219 enum zynqmp_dpsub_format format, 1220 unsigned int bpc) 1221 { 1222 struct zynqmp_dp_config *config = &dp->config; 1223 unsigned int num_colors; 1224 1225 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK; 1226 config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; 1227 1228 switch (format) { 1229 case ZYNQMP_DPSUB_FORMAT_RGB: 1230 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB; 1231 num_colors = 3; 1232 break; 1233 1234 case ZYNQMP_DPSUB_FORMAT_YCRCB444: 1235 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444; 1236 num_colors = 3; 1237 break; 1238 1239 case ZYNQMP_DPSUB_FORMAT_YCRCB422: 1240 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422; 1241 num_colors = 2; 1242 break; 1243 1244 case ZYNQMP_DPSUB_FORMAT_YONLY: 1245 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; 1246 num_colors = 1; 1247 break; 1248 1249 default: 1250 dev_err(dp->dev, "Invalid colormetry in DT\n"); 1251 return -EINVAL; 1252 } 1253 1254 if (info && info->bpc && bpc > info->bpc) { 1255 dev_warn(dp->dev, 1256 "downgrading requested %ubpc to display limit %ubpc\n", 1257 bpc, info->bpc); 1258 bpc = info->bpc; 1259 } 1260 1261 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK; 1262 1263 switch (bpc) { 1264 case 6: 1265 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6; 1266 break; 1267 case 8: 1268 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; 1269 break; 1270 case 10: 1271 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10; 1272 break; 1273 case 12: 1274 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12; 1275 break; 1276 case 16: 1277 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16; 1278 break; 1279 default: 1280 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n", 1281 bpc); 1282 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; 1283 bpc = 8; 1284 break; 1285 } 1286 1287 /* Update the current bpp based on the format. */ 1288 config->bpp = bpc * num_colors; 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values 1295 * @dp: DisplayPort IP core structure 1296 * @mode: requested display mode 1297 * 1298 * Set the transfer unit, and calculate all transfer unit size related values. 1299 * Calculation is based on DP and IP core specification. 1300 */ 1301 static void 1302 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, 1303 const struct drm_display_mode *mode) 1304 { 1305 u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF; 1306 u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait; 1307 1308 /* Use the max transfer unit size (default) */ 1309 zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu); 1310 1311 vid_kbytes = mode->clock * (dp->config.bpp / 8); 1312 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1313 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000); 1314 zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU, 1315 avg_bytes_per_tu / 1000); 1316 zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU, 1317 avg_bytes_per_tu % 1000); 1318 1319 /* Configure the initial wait cycle based on transfer unit size */ 1320 if (tu < (avg_bytes_per_tu / 1000)) 1321 init_wait = 0; 1322 else if ((avg_bytes_per_tu / 1000) <= 4) 1323 init_wait = tu; 1324 else 1325 init_wait = tu - avg_bytes_per_tu / 1000; 1326 1327 zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait); 1328 } 1329 1330 /** 1331 * zynqmp_dp_encoder_mode_set_stream - Configure the main stream 1332 * @dp: DisplayPort IP core structure 1333 * @mode: requested display mode 1334 * 1335 * Configure the main stream based on the requested mode @mode. Calculation is 1336 * based on IP core specification. 1337 */ 1338 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, 1339 const struct drm_display_mode *mode) 1340 { 1341 u8 lane_cnt = dp->mode.lane_cnt; 1342 u32 reg, wpl; 1343 1344 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal); 1345 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal); 1346 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY, 1347 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) << 1348 ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) | 1349 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) << 1350 ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT)); 1351 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH, 1352 mode->hsync_end - mode->hsync_start); 1353 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH, 1354 mode->vsync_end - mode->vsync_start); 1355 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay); 1356 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay); 1357 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART, 1358 mode->htotal - mode->hsync_start); 1359 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART, 1360 mode->vtotal - mode->vsync_start); 1361 1362 /* In synchronous mode, set the dividers */ 1363 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) { 1364 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1365 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg); 1366 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock); 1367 } 1368 1369 zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1); 1370 1371 /* Translate to the native 16 bit datapath based on IP core spec */ 1372 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16; 1373 reg = wpl + wpl % lane_cnt - lane_cnt; 1374 zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg); 1375 } 1376 1377 /* ----------------------------------------------------------------------------- 1378 * Audio 1379 */ 1380 1381 void zynqmp_dp_audio_set_channels(struct zynqmp_dp *dp, 1382 unsigned int num_channels) 1383 { 1384 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, num_channels - 1); 1385 } 1386 1387 void zynqmp_dp_audio_enable(struct zynqmp_dp *dp) 1388 { 1389 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1); 1390 } 1391 1392 void zynqmp_dp_audio_disable(struct zynqmp_dp *dp) 1393 { 1394 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0); 1395 } 1396 1397 void zynqmp_dp_audio_write_n_m(struct zynqmp_dp *dp) 1398 { 1399 unsigned int rate; 1400 u32 link_rate; 1401 1402 if (!(dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK)) 1403 return; 1404 1405 link_rate = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1406 1407 rate = clk_get_rate(dp->dpsub->aud_clk); 1408 1409 dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512); 1410 1411 zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, link_rate); 1412 zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000); 1413 } 1414 1415 /* ----------------------------------------------------------------------------- 1416 * DISP Configuration 1417 */ 1418 1419 /** 1420 * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer 1421 * @dp: DisplayPort IP core structure 1422 * 1423 * Return: The first connected live display layer or NULL if none of the live 1424 * layers are connected. 1425 */ 1426 static struct zynqmp_disp_layer * 1427 zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp) 1428 { 1429 if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) 1430 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID]; 1431 else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX)) 1432 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX]; 1433 else 1434 return NULL; 1435 } 1436 1437 static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, 1438 struct drm_atomic_commit *state) 1439 { 1440 struct zynqmp_disp_layer *layer; 1441 struct drm_bridge_state *bridge_state; 1442 u32 bus_fmt; 1443 1444 layer = zynqmp_dp_disp_connected_live_layer(dp); 1445 if (!layer) 1446 return; 1447 1448 bridge_state = drm_atomic_get_new_bridge_state(state, &dp->bridge); 1449 if (WARN_ON(!bridge_state)) 1450 return; 1451 1452 bus_fmt = bridge_state->input_bus_cfg.format; 1453 zynqmp_disp_layer_set_live_format(layer, bus_fmt); 1454 zynqmp_disp_layer_enable(layer); 1455 1456 if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX]) 1457 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255); 1458 else 1459 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, false, 0); 1460 1461 zynqmp_disp_enable(dp->dpsub->disp); 1462 } 1463 1464 static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp, 1465 struct drm_bridge_state *old_bridge_state) 1466 { 1467 struct zynqmp_disp_layer *layer; 1468 1469 layer = zynqmp_dp_disp_connected_live_layer(dp); 1470 if (!layer) 1471 return; 1472 1473 zynqmp_disp_disable(dp->dpsub->disp); 1474 zynqmp_disp_layer_disable(layer); 1475 } 1476 1477 /* ----------------------------------------------------------------------------- 1478 * DRM Bridge 1479 */ 1480 1481 static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge, 1482 struct drm_encoder *encoder, 1483 enum drm_bridge_attach_flags flags) 1484 { 1485 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1486 int ret; 1487 1488 /* Initialize and register the AUX adapter. */ 1489 ret = zynqmp_dp_aux_init(dp); 1490 if (ret) { 1491 dev_err(dp->dev, "failed to initialize DP aux\n"); 1492 return ret; 1493 } 1494 1495 if (dp->bridge.next_bridge) { 1496 ret = drm_bridge_attach(encoder, dp->bridge.next_bridge, 1497 bridge, flags); 1498 if (ret < 0) 1499 goto error; 1500 } 1501 1502 /* Now that initialisation is complete, enable interrupts. */ 1503 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL); 1504 1505 return 0; 1506 1507 error: 1508 zynqmp_dp_aux_cleanup(dp); 1509 return ret; 1510 } 1511 1512 static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge) 1513 { 1514 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1515 1516 zynqmp_dp_aux_cleanup(dp); 1517 } 1518 1519 static enum drm_mode_status 1520 zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge, 1521 const struct drm_display_info *info, 1522 const struct drm_display_mode *mode) 1523 { 1524 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1525 int rate; 1526 1527 if (mode->clock > ZYNQMP_MAX_FREQ) { 1528 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n", 1529 mode->name); 1530 drm_mode_debug_printmodeline(mode); 1531 return MODE_CLOCK_HIGH; 1532 } 1533 1534 /* Check with link rate and lane count */ 1535 scoped_guard(mutex, &dp->lock) 1536 rate = zynqmp_dp_max_rate(dp->link_config.max_rate, 1537 dp->link_config.max_lanes, 1538 dp->config.bpp); 1539 if (mode->clock > rate) { 1540 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n", 1541 mode->name); 1542 drm_mode_debug_printmodeline(mode); 1543 return MODE_CLOCK_HIGH; 1544 } 1545 1546 return MODE_OK; 1547 } 1548 1549 static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge, 1550 struct drm_atomic_commit *state) 1551 { 1552 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1553 const struct drm_crtc_state *crtc_state; 1554 const struct drm_display_mode *adjusted_mode; 1555 const struct drm_display_mode *mode; 1556 struct drm_connector *connector; 1557 struct drm_crtc *crtc; 1558 unsigned int i; 1559 int rate; 1560 int ret; 1561 1562 pm_runtime_get_sync(dp->dev); 1563 1564 guard(mutex)(&dp->lock); 1565 zynqmp_dp_disp_enable(dp, state); 1566 1567 /* 1568 * Retrieve the CRTC mode and adjusted mode. This requires a little 1569 * dance to go from the bridge to the encoder, to the connector and to 1570 * the CRTC. 1571 */ 1572 connector = drm_atomic_get_new_connector_for_encoder(state, 1573 bridge->encoder); 1574 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 1575 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1576 adjusted_mode = &crtc_state->adjusted_mode; 1577 mode = &crtc_state->mode; 1578 1579 zynqmp_dp_set_format(dp, &connector->display_info, 1580 ZYNQMP_DPSUB_FORMAT_RGB, 8); 1581 1582 /* Check again as bpp or format might have been changed */ 1583 rate = zynqmp_dp_max_rate(dp->link_config.max_rate, 1584 dp->link_config.max_lanes, dp->config.bpp); 1585 if (mode->clock > rate) { 1586 dev_err(dp->dev, "mode %s has too high pixel rate\n", 1587 mode->name); 1588 drm_mode_debug_printmodeline(mode); 1589 } 1590 1591 /* Configure the mode */ 1592 ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0); 1593 if (ret < 0) { 1594 pm_runtime_put_sync(dp->dev); 1595 return; 1596 } 1597 1598 zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode); 1599 zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode); 1600 1601 /* Enable the encoder */ 1602 dp->enabled = true; 1603 zynqmp_dp_update_misc(dp); 1604 1605 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0); 1606 if (dp->status == connector_status_connected) { 1607 for (i = 0; i < 3; i++) { 1608 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, 1609 DP_SET_POWER_D0); 1610 if (ret == 1) 1611 break; 1612 usleep_range(300, 500); 1613 } 1614 /* Some monitors take time to wake up properly */ 1615 msleep(zynqmp_dp_power_on_delay_ms); 1616 } 1617 if (ret != 1) 1618 dev_dbg(dp->dev, "DP aux failed\n"); 1619 else 1620 zynqmp_dp_train_loop(dp); 1621 zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET, 1622 ZYNQMP_DP_SOFTWARE_RESET_ALL); 1623 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1); 1624 } 1625 1626 static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge, 1627 struct drm_atomic_commit *state) 1628 { 1629 struct drm_bridge_state *old_bridge_state = drm_atomic_get_old_bridge_state(state, 1630 bridge); 1631 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1632 1633 mutex_lock(&dp->lock); 1634 dp->enabled = false; 1635 cancel_work(&dp->hpd_work); 1636 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0); 1637 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3); 1638 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 1639 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL); 1640 1641 zynqmp_dp_disp_disable(dp, old_bridge_state); 1642 mutex_unlock(&dp->lock); 1643 1644 pm_runtime_put_sync(dp->dev); 1645 } 1646 1647 #define ZYNQMP_DP_MIN_H_BACKPORCH 20 1648 1649 static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge, 1650 struct drm_bridge_state *bridge_state, 1651 struct drm_crtc_state *crtc_state, 1652 struct drm_connector_state *conn_state) 1653 { 1654 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1655 struct drm_display_mode *mode = &crtc_state->mode; 1656 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1657 int diff = mode->htotal - mode->hsync_end; 1658 1659 /* 1660 * ZynqMP DP requires horizontal backporch to be greater than 12. 1661 * This limitation may not be compatible with the sink device. 1662 */ 1663 if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) { 1664 int vrefresh = (adjusted_mode->clock * 1000) / 1665 (adjusted_mode->vtotal * adjusted_mode->htotal); 1666 1667 dev_dbg(dp->dev, "hbackporch adjusted: %d to %d", 1668 diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff); 1669 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff; 1670 adjusted_mode->htotal += diff; 1671 adjusted_mode->clock = adjusted_mode->vtotal * 1672 adjusted_mode->htotal * vrefresh / 1000; 1673 } 1674 1675 return 0; 1676 } 1677 1678 static enum drm_connector_status __zynqmp_dp_bridge_detect(struct zynqmp_dp *dp) 1679 { 1680 struct zynqmp_dp_link_config *link_config = &dp->link_config; 1681 u32 state, i; 1682 int ret; 1683 1684 lockdep_assert_held(&dp->lock); 1685 1686 /* 1687 * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to 1688 * get the HPD signal with some monitors. 1689 */ 1690 for (i = 0; i < 10; i++) { 1691 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1692 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) 1693 break; 1694 msleep(100); 1695 } 1696 1697 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) { 1698 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, 1699 sizeof(dp->dpcd)); 1700 if (ret < 0) { 1701 dev_dbg(dp->dev, "DPCD read failed"); 1702 goto disconnected; 1703 } 1704 1705 link_config->max_rate = min_t(int, 1706 drm_dp_max_link_rate(dp->dpcd), 1707 DP_HIGH_BIT_RATE2); 1708 link_config->max_lanes = min_t(u8, 1709 drm_dp_max_lane_count(dp->dpcd), 1710 dp->num_lanes); 1711 1712 dp->status = connector_status_connected; 1713 return connector_status_connected; 1714 } 1715 1716 disconnected: 1717 dp->status = connector_status_disconnected; 1718 return connector_status_disconnected; 1719 } 1720 1721 static enum drm_connector_status 1722 zynqmp_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 1723 { 1724 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1725 1726 guard(mutex)(&dp->lock); 1727 return __zynqmp_dp_bridge_detect(dp); 1728 } 1729 1730 static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge, 1731 struct drm_connector *connector) 1732 { 1733 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1734 1735 return drm_edid_read_ddc(connector, &dp->aux.ddc); 1736 } 1737 1738 static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts) 1739 { 1740 u32 *formats = kzalloc_obj(*formats); 1741 1742 if (formats) 1743 *formats = MEDIA_BUS_FMT_FIXED; 1744 *num_input_fmts = !!formats; 1745 1746 return formats; 1747 } 1748 1749 static u32 * 1750 zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge, 1751 struct drm_bridge_state *bridge_state, 1752 struct drm_crtc_state *crtc_state, 1753 struct drm_connector_state *conn_state, 1754 u32 output_fmt, 1755 unsigned int *num_input_fmts) 1756 { 1757 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1758 struct zynqmp_disp_layer *layer; 1759 1760 layer = zynqmp_dp_disp_connected_live_layer(dp); 1761 if (layer) 1762 return zynqmp_disp_live_layer_formats(layer, num_input_fmts); 1763 else 1764 return zynqmp_dp_bridge_default_bus_fmts(num_input_fmts); 1765 } 1766 1767 /* ----------------------------------------------------------------------------- 1768 * debugfs 1769 */ 1770 1771 /** 1772 * zynqmp_dp_set_test_pattern() - Configure the link for a test pattern 1773 * @dp: DisplayPort IP core structure 1774 * @pattern: The test pattern to configure 1775 * @custom: The custom pattern to use if @pattern is %TEST_80BIT_CUSTOM 1776 * 1777 * Return: 0 on success, or negative errno on (DPCD) failure 1778 */ 1779 static int zynqmp_dp_set_test_pattern(struct zynqmp_dp *dp, 1780 enum test_pattern pattern, 1781 u8 *const custom) 1782 { 1783 bool scramble = false; 1784 u32 train_pattern = 0; 1785 u32 link_pattern = 0; 1786 u8 dpcd_train = 0; 1787 u8 dpcd_link = 0; 1788 int ret; 1789 1790 switch (pattern) { 1791 case TEST_TPS1: 1792 train_pattern = 1; 1793 break; 1794 case TEST_TPS2: 1795 train_pattern = 2; 1796 break; 1797 case TEST_TPS3: 1798 train_pattern = 3; 1799 break; 1800 case TEST_SYMBOL_ERROR: 1801 scramble = true; 1802 link_pattern = DP_PHY_TEST_PATTERN_ERROR_COUNT; 1803 break; 1804 case TEST_PRBS7: 1805 /* We use a dedicated register to enable PRBS7 */ 1806 dpcd_link = DP_LINK_QUAL_PATTERN_ERROR_RATE; 1807 break; 1808 case TEST_80BIT_CUSTOM: { 1809 const u8 *p = custom; 1810 1811 link_pattern = DP_LINK_QUAL_PATTERN_80BIT_CUSTOM; 1812 1813 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_1, 1814 (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); 1815 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_2, 1816 (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]); 1817 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_3, 1818 (p[9] << 8) | p[8]); 1819 break; 1820 } 1821 case TEST_CP2520: 1822 link_pattern = DP_LINK_QUAL_PATTERN_CP2520_PAT_1; 1823 break; 1824 default: 1825 WARN_ON_ONCE(1); 1826 fallthrough; 1827 case TEST_VIDEO: 1828 scramble = true; 1829 } 1830 1831 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, !scramble); 1832 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, train_pattern); 1833 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_QUAL_PATTERN_SET, link_pattern); 1834 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMIT_PRBS7, pattern == TEST_PRBS7); 1835 1836 dpcd_link = dpcd_link ?: link_pattern; 1837 dpcd_train = train_pattern; 1838 if (!scramble) 1839 dpcd_train |= DP_LINK_SCRAMBLING_DISABLE; 1840 1841 if (dp->dpcd[DP_DPCD_REV] < 0x12) { 1842 if (pattern == TEST_CP2520) 1843 dev_warn(dp->dev, 1844 "can't set sink link quality pattern to CP2520 for DPCD < r1.2; error counters will be invalid\n"); 1845 else 1846 dpcd_train |= FIELD_PREP(DP_LINK_QUAL_PATTERN_11_MASK, 1847 dpcd_link); 1848 } else { 1849 u8 dpcd_link_lane[ZYNQMP_DP_MAX_LANES]; 1850 1851 memset(dpcd_link_lane, dpcd_link, ZYNQMP_DP_MAX_LANES); 1852 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_QUAL_LANE0_SET, 1853 dpcd_link_lane, ZYNQMP_DP_MAX_LANES); 1854 if (ret < 0) 1855 return ret; 1856 } 1857 1858 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, dpcd_train); 1859 return ret < 0 ? ret : 0; 1860 } 1861 1862 static int zynqmp_dp_test_setup(struct zynqmp_dp *dp) 1863 { 1864 return zynqmp_dp_setup(dp, dp->test.bw_code, dp->test.link_cnt, 1865 dp->test.enhanced, dp->test.downspread); 1866 } 1867 1868 static ssize_t zynqmp_dp_pattern_read(struct file *file, char __user *user_buf, 1869 size_t count, loff_t *ppos) 1870 { 1871 struct zynqmp_dp *dp = file->private_data; 1872 char buf[16]; 1873 ssize_t ret; 1874 1875 scoped_guard(mutex, &dp->lock) 1876 ret = snprintf(buf, sizeof(buf), "%s\n", 1877 test_pattern_str[dp->test.pattern]); 1878 1879 return simple_read_from_buffer(user_buf, count, ppos, buf, ret); 1880 } 1881 1882 static ssize_t zynqmp_dp_pattern_write(struct file *file, 1883 const char __user *user_buf, 1884 size_t count, loff_t *ppos) 1885 { 1886 struct zynqmp_dp *dp = file->private_data; 1887 char buf[16]; 1888 ssize_t ret; 1889 int pattern; 1890 1891 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, 1892 count); 1893 if (ret < 0) 1894 return ret; 1895 buf[ret] = '\0'; 1896 1897 pattern = sysfs_match_string(test_pattern_str, buf); 1898 if (pattern < 0) 1899 return -EINVAL; 1900 1901 mutex_lock(&dp->lock); 1902 dp->test.pattern = pattern; 1903 if (dp->test.active) 1904 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern, 1905 dp->test.custom) ?: ret; 1906 mutex_unlock(&dp->lock); 1907 1908 return ret; 1909 } 1910 1911 static const struct file_operations fops_zynqmp_dp_pattern = { 1912 .read = zynqmp_dp_pattern_read, 1913 .write = zynqmp_dp_pattern_write, 1914 .open = simple_open, 1915 .llseek = noop_llseek, 1916 }; 1917 1918 static int zynqmp_dp_enhanced_get(void *data, u64 *val) 1919 { 1920 struct zynqmp_dp *dp = data; 1921 1922 guard(mutex)(&dp->lock); 1923 *val = dp->test.enhanced; 1924 return 0; 1925 } 1926 1927 static int zynqmp_dp_enhanced_set(void *data, u64 val) 1928 { 1929 struct zynqmp_dp *dp = data; 1930 1931 guard(mutex)(&dp->lock); 1932 dp->test.enhanced = val; 1933 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 1934 } 1935 1936 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_enhanced, zynqmp_dp_enhanced_get, 1937 zynqmp_dp_enhanced_set, "%llu\n"); 1938 1939 static int zynqmp_dp_downspread_get(void *data, u64 *val) 1940 { 1941 struct zynqmp_dp *dp = data; 1942 1943 guard(mutex)(&dp->lock); 1944 *val = dp->test.downspread; 1945 return 0; 1946 } 1947 1948 static int zynqmp_dp_downspread_set(void *data, u64 val) 1949 { 1950 struct zynqmp_dp *dp = data; 1951 1952 guard(mutex)(&dp->lock); 1953 dp->test.downspread = val; 1954 1955 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 1956 } 1957 1958 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_downspread, zynqmp_dp_downspread_get, 1959 zynqmp_dp_downspread_set, "%llu\n"); 1960 1961 static int zynqmp_dp_active_get(void *data, u64 *val) 1962 { 1963 struct zynqmp_dp *dp = data; 1964 1965 guard(mutex)(&dp->lock); 1966 *val = dp->test.active; 1967 return 0; 1968 } 1969 1970 static int zynqmp_dp_active_set(void *data, u64 val) 1971 { 1972 struct zynqmp_dp *dp = data; 1973 int ret; 1974 1975 guard(mutex)(&dp->lock); 1976 if (val) { 1977 if (val < 2) { 1978 ret = zynqmp_dp_test_setup(dp); 1979 if (ret) 1980 return ret; 1981 } 1982 1983 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern, 1984 dp->test.custom); 1985 if (ret) 1986 return ret; 1987 1988 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set); 1989 if (ret) 1990 return ret; 1991 1992 dp->test.active = true; 1993 } else { 1994 int err; 1995 1996 dp->test.active = false; 1997 err = zynqmp_dp_set_test_pattern(dp, TEST_VIDEO, NULL); 1998 if (err) 1999 dev_warn(dp->dev, "could not clear test pattern: %d\n", 2000 err); 2001 zynqmp_dp_train_loop(dp); 2002 } 2003 2004 return 0; 2005 } 2006 2007 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_active, zynqmp_dp_active_get, 2008 zynqmp_dp_active_set, "%llu\n"); 2009 2010 static ssize_t zynqmp_dp_custom_read(struct file *file, char __user *user_buf, 2011 size_t count, loff_t *ppos) 2012 { 2013 struct zynqmp_dp *dp = file->private_data; 2014 ssize_t ret; 2015 2016 mutex_lock(&dp->lock); 2017 ret = simple_read_from_buffer(user_buf, count, ppos, &dp->test.custom, 2018 sizeof(dp->test.custom)); 2019 mutex_unlock(&dp->lock); 2020 return ret; 2021 } 2022 2023 static ssize_t zynqmp_dp_custom_write(struct file *file, 2024 const char __user *user_buf, 2025 size_t count, loff_t *ppos) 2026 { 2027 struct zynqmp_dp *dp = file->private_data; 2028 ssize_t ret; 2029 char buf[sizeof(dp->test.custom)]; 2030 2031 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 2032 if (ret < 0) 2033 return ret; 2034 2035 mutex_lock(&dp->lock); 2036 memcpy(dp->test.custom, buf, ret); 2037 if (dp->test.active) 2038 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern, 2039 dp->test.custom) ?: ret; 2040 mutex_unlock(&dp->lock); 2041 return ret; 2042 } 2043 2044 static const struct file_operations fops_zynqmp_dp_custom = { 2045 .read = zynqmp_dp_custom_read, 2046 .write = zynqmp_dp_custom_write, 2047 .open = simple_open, 2048 .llseek = noop_llseek, 2049 }; 2050 2051 static int zynqmp_dp_swing_get(void *data, u64 *val) 2052 { 2053 struct zynqmp_dp_train_set_priv *priv = data; 2054 struct zynqmp_dp *dp = priv->dp; 2055 2056 guard(mutex)(&dp->lock); 2057 *val = dp->test.train_set[priv->lane] & DP_TRAIN_VOLTAGE_SWING_MASK; 2058 return 0; 2059 } 2060 2061 static int zynqmp_dp_swing_set(void *data, u64 val) 2062 { 2063 struct zynqmp_dp_train_set_priv *priv = data; 2064 struct zynqmp_dp *dp = priv->dp; 2065 u8 *train_set = &dp->test.train_set[priv->lane]; 2066 2067 if (val > 3) 2068 return -EINVAL; 2069 2070 guard(mutex)(&dp->lock); 2071 *train_set &= ~(DP_TRAIN_MAX_SWING_REACHED | 2072 DP_TRAIN_VOLTAGE_SWING_MASK); 2073 *train_set |= val; 2074 if (val == 3) 2075 *train_set |= DP_TRAIN_MAX_SWING_REACHED; 2076 2077 if (dp->test.active) 2078 return zynqmp_dp_update_vs_emph(dp, dp->test.train_set); 2079 2080 return 0; 2081 } 2082 2083 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_swing, zynqmp_dp_swing_get, 2084 zynqmp_dp_swing_set, "%llu\n"); 2085 2086 static int zynqmp_dp_preemphasis_get(void *data, u64 *val) 2087 { 2088 struct zynqmp_dp_train_set_priv *priv = data; 2089 struct zynqmp_dp *dp = priv->dp; 2090 2091 guard(mutex)(&dp->lock); 2092 *val = FIELD_GET(DP_TRAIN_PRE_EMPHASIS_MASK, 2093 dp->test.train_set[priv->lane]); 2094 return 0; 2095 } 2096 2097 static int zynqmp_dp_preemphasis_set(void *data, u64 val) 2098 { 2099 struct zynqmp_dp_train_set_priv *priv = data; 2100 struct zynqmp_dp *dp = priv->dp; 2101 u8 *train_set = &dp->test.train_set[priv->lane]; 2102 2103 if (val > 2) 2104 return -EINVAL; 2105 2106 guard(mutex)(&dp->lock); 2107 *train_set &= ~(DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | 2108 DP_TRAIN_PRE_EMPHASIS_MASK); 2109 *train_set |= val; 2110 if (val == 2) 2111 *train_set |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2112 2113 if (dp->test.active) 2114 return zynqmp_dp_update_vs_emph(dp, dp->test.train_set); 2115 2116 return 0; 2117 } 2118 2119 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_preemphasis, zynqmp_dp_preemphasis_get, 2120 zynqmp_dp_preemphasis_set, "%llu\n"); 2121 2122 static int zynqmp_dp_lanes_get(void *data, u64 *val) 2123 { 2124 struct zynqmp_dp *dp = data; 2125 2126 guard(mutex)(&dp->lock); 2127 *val = dp->test.link_cnt; 2128 return 0; 2129 } 2130 2131 static int zynqmp_dp_lanes_set(void *data, u64 val) 2132 { 2133 struct zynqmp_dp *dp = data; 2134 2135 if (val > ZYNQMP_DP_MAX_LANES) 2136 return -EINVAL; 2137 2138 guard(mutex)(&dp->lock); 2139 if (val > dp->num_lanes) 2140 return -EINVAL; 2141 2142 dp->test.link_cnt = val; 2143 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 2144 } 2145 2146 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_lanes, zynqmp_dp_lanes_get, 2147 zynqmp_dp_lanes_set, "%llu\n"); 2148 2149 static int zynqmp_dp_rate_get(void *data, u64 *val) 2150 { 2151 struct zynqmp_dp *dp = data; 2152 2153 guard(mutex)(&dp->lock); 2154 *val = drm_dp_bw_code_to_link_rate(dp->test.bw_code) * 10000ULL; 2155 return 0; 2156 } 2157 2158 static int zynqmp_dp_rate_set(void *data, u64 val) 2159 { 2160 struct zynqmp_dp *dp = data; 2161 int link_rate; 2162 u8 bw_code; 2163 2164 if (do_div(val, 10000)) 2165 return -EINVAL; 2166 2167 bw_code = drm_dp_link_rate_to_bw_code(val); 2168 link_rate = drm_dp_bw_code_to_link_rate(bw_code); 2169 if (val != link_rate) 2170 return -EINVAL; 2171 2172 if (bw_code != DP_LINK_BW_1_62 && bw_code != DP_LINK_BW_2_7 && 2173 bw_code != DP_LINK_BW_5_4) 2174 return -EINVAL; 2175 2176 guard(mutex)(&dp->lock); 2177 dp->test.bw_code = bw_code; 2178 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 2179 } 2180 2181 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_rate, zynqmp_dp_rate_get, 2182 zynqmp_dp_rate_set, "%llu\n"); 2183 2184 static int zynqmp_dp_ignore_aux_errors_get(void *data, u64 *val) 2185 { 2186 struct zynqmp_dp *dp = data; 2187 2188 guard(mutex)(&dp->lock); 2189 *val = dp->ignore_aux_errors; 2190 return 0; 2191 } 2192 2193 static int zynqmp_dp_ignore_aux_errors_set(void *data, u64 val) 2194 { 2195 struct zynqmp_dp *dp = data; 2196 2197 if (val != !!val) 2198 return -EINVAL; 2199 2200 guard(mutex)(&dp->lock); 2201 dp->ignore_aux_errors = val; 2202 return 0; 2203 } 2204 2205 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_aux_errors, 2206 zynqmp_dp_ignore_aux_errors_get, 2207 zynqmp_dp_ignore_aux_errors_set, "%llu\n"); 2208 2209 static int zynqmp_dp_ignore_hpd_get(void *data, u64 *val) 2210 { 2211 struct zynqmp_dp *dp = data; 2212 2213 guard(mutex)(&dp->lock); 2214 *val = dp->ignore_hpd; 2215 return 0; 2216 } 2217 2218 static int zynqmp_dp_ignore_hpd_set(void *data, u64 val) 2219 { 2220 struct zynqmp_dp *dp = data; 2221 2222 if (val != !!val) 2223 return -EINVAL; 2224 2225 guard(mutex)(&dp->lock); 2226 dp->ignore_hpd = val; 2227 return 0; 2228 } 2229 2230 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_hpd, zynqmp_dp_ignore_hpd_get, 2231 zynqmp_dp_ignore_hpd_set, "%llu\n"); 2232 2233 static void zynqmp_dp_bridge_debugfs_init(struct drm_bridge *bridge, 2234 struct dentry *root) 2235 { 2236 struct zynqmp_dp *dp = bridge_to_dp(bridge); 2237 struct dentry *test; 2238 int i; 2239 2240 dp->test.bw_code = DP_LINK_BW_5_4; 2241 dp->test.link_cnt = dp->num_lanes; 2242 2243 test = debugfs_create_dir("test", root); 2244 #define CREATE_FILE(name) \ 2245 debugfs_create_file(#name, 0600, test, dp, &fops_zynqmp_dp_##name) 2246 CREATE_FILE(pattern); 2247 CREATE_FILE(enhanced); 2248 CREATE_FILE(downspread); 2249 CREATE_FILE(active); 2250 CREATE_FILE(custom); 2251 CREATE_FILE(rate); 2252 CREATE_FILE(lanes); 2253 CREATE_FILE(ignore_aux_errors); 2254 CREATE_FILE(ignore_hpd); 2255 2256 for (i = 0; i < dp->num_lanes; i++) { 2257 static const char fmt[] = "lane%d_preemphasis"; 2258 char name[sizeof(fmt)]; 2259 2260 dp->debugfs_train_set[i].dp = dp; 2261 dp->debugfs_train_set[i].lane = i; 2262 2263 snprintf(name, sizeof(name), fmt, i); 2264 debugfs_create_file(name, 0600, test, 2265 &dp->debugfs_train_set[i], 2266 &fops_zynqmp_dp_preemphasis); 2267 2268 snprintf(name, sizeof(name), "lane%d_swing", i); 2269 debugfs_create_file(name, 0600, test, 2270 &dp->debugfs_train_set[i], 2271 &fops_zynqmp_dp_swing); 2272 } 2273 } 2274 2275 static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = { 2276 .attach = zynqmp_dp_bridge_attach, 2277 .detach = zynqmp_dp_bridge_detach, 2278 .mode_valid = zynqmp_dp_bridge_mode_valid, 2279 .atomic_enable = zynqmp_dp_bridge_atomic_enable, 2280 .atomic_disable = zynqmp_dp_bridge_atomic_disable, 2281 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2282 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2283 .atomic_reset = drm_atomic_helper_bridge_reset, 2284 .atomic_check = zynqmp_dp_bridge_atomic_check, 2285 .detect = zynqmp_dp_bridge_detect, 2286 .edid_read = zynqmp_dp_bridge_edid_read, 2287 .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts, 2288 .debugfs_init = zynqmp_dp_bridge_debugfs_init, 2289 }; 2290 2291 /* ----------------------------------------------------------------------------- 2292 * Interrupt Handling 2293 */ 2294 2295 /** 2296 * zynqmp_dp_enable_vblank - Enable vblank 2297 * @dp: DisplayPort IP core structure 2298 * 2299 * Enable vblank interrupt 2300 */ 2301 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp) 2302 { 2303 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START); 2304 } 2305 2306 /** 2307 * zynqmp_dp_disable_vblank - Disable vblank 2308 * @dp: DisplayPort IP core structure 2309 * 2310 * Disable vblank interrupt 2311 */ 2312 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp) 2313 { 2314 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START); 2315 } 2316 2317 static void zynqmp_dp_hpd_work_func(struct work_struct *work) 2318 { 2319 struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, hpd_work); 2320 enum drm_connector_status status; 2321 2322 scoped_guard(mutex, &dp->lock) { 2323 if (dp->ignore_hpd) 2324 return; 2325 2326 status = __zynqmp_dp_bridge_detect(dp); 2327 } 2328 2329 drm_bridge_hpd_notify(&dp->bridge, status); 2330 } 2331 2332 static void zynqmp_dp_hpd_irq_work_func(struct work_struct *work) 2333 { 2334 struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, 2335 hpd_irq_work); 2336 u8 status[DP_LINK_STATUS_SIZE + 2]; 2337 int err; 2338 2339 guard(mutex)(&dp->lock); 2340 if (dp->ignore_hpd) 2341 return; 2342 2343 err = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status, 2344 DP_LINK_STATUS_SIZE + 2); 2345 if (err < 0) { 2346 dev_dbg_ratelimited(dp->dev, 2347 "could not read sink status: %d\n", err); 2348 } else { 2349 if (status[4] & DP_LINK_STATUS_UPDATED || 2350 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) || 2351 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) { 2352 zynqmp_dp_train_loop(dp); 2353 } 2354 } 2355 } 2356 2357 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data) 2358 { 2359 struct zynqmp_dp *dp = (struct zynqmp_dp *)data; 2360 u32 status, mask; 2361 2362 status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS); 2363 /* clear status register as soon as we read it */ 2364 zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); 2365 mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); 2366 2367 /* 2368 * Status register may report some events, which corresponding interrupts 2369 * have been disabled. Filter out those events against interrupts' mask. 2370 */ 2371 status &= ~mask; 2372 2373 if (!status) 2374 return IRQ_NONE; 2375 2376 /* dbg for diagnostic, but not much that the driver can do */ 2377 if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK) 2378 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n"); 2379 if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) 2380 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); 2381 2382 if (status & ZYNQMP_DP_INT_VBLANK_START) 2383 zynqmp_dpsub_drm_handle_vblank(dp->dpsub); 2384 2385 if (status & ZYNQMP_DP_INT_HPD_EVENT) 2386 schedule_work(&dp->hpd_work); 2387 2388 if (status & ZYNQMP_DP_INT_HPD_IRQ) 2389 schedule_work(&dp->hpd_irq_work); 2390 2391 if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY) 2392 complete(&dp->aux_done); 2393 2394 if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT) 2395 complete(&dp->aux_done); 2396 2397 return IRQ_HANDLED; 2398 } 2399 2400 /* ----------------------------------------------------------------------------- 2401 * Initialization & Cleanup 2402 */ 2403 2404 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub) 2405 { 2406 struct platform_device *pdev = to_platform_device(dpsub->dev); 2407 struct drm_bridge *bridge; 2408 struct zynqmp_dp *dp; 2409 int ret; 2410 2411 dp = devm_drm_bridge_alloc(&pdev->dev, struct zynqmp_dp, bridge, &zynqmp_dp_bridge_funcs); 2412 if (IS_ERR(dp)) 2413 return PTR_ERR(dp); 2414 2415 dp->dev = &pdev->dev; 2416 dp->dpsub = dpsub; 2417 dp->status = connector_status_disconnected; 2418 mutex_init(&dp->lock); 2419 init_completion(&dp->aux_done); 2420 2421 INIT_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func); 2422 INIT_WORK(&dp->hpd_irq_work, zynqmp_dp_hpd_irq_work_func); 2423 2424 /* Acquire all resources (IOMEM, IRQ and PHYs). */ 2425 dp->iomem = devm_platform_ioremap_resource_byname(pdev, "dp"); 2426 if (IS_ERR(dp->iomem)) 2427 return PTR_ERR(dp->iomem); 2428 2429 dp->irq = platform_get_irq(pdev, 0); 2430 if (dp->irq < 0) 2431 return dp->irq; 2432 2433 dp->reset = devm_reset_control_get(dp->dev, NULL); 2434 if (IS_ERR(dp->reset)) 2435 return dev_err_probe(dp->dev, PTR_ERR(dp->reset), 2436 "failed to get reset\n"); 2437 2438 ret = zynqmp_dp_reset(dp, true); 2439 if (ret < 0) 2440 return ret; 2441 2442 ret = zynqmp_dp_reset(dp, false); 2443 if (ret < 0) 2444 return ret; 2445 2446 ret = zynqmp_dp_phy_probe(dp); 2447 if (ret) 2448 goto err_reset; 2449 2450 /* Initialize the bridge. */ 2451 bridge = &dp->bridge; 2452 bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 2453 | DRM_BRIDGE_OP_HPD; 2454 bridge->type = DRM_MODE_CONNECTOR_DisplayPort; 2455 bridge->of_node = dp->dev->of_node; 2456 dpsub->bridge = bridge; 2457 2458 /* 2459 * Acquire the next bridge in the chain. Ignore errors caused by port@5 2460 * not being connected for backward-compatibility with older DTs. 2461 */ 2462 dp->bridge.next_bridge = of_drm_get_bridge_by_endpoint(dp->dev->of_node, 5, 0); 2463 if (IS_ERR(dp->bridge.next_bridge)) { 2464 if (PTR_ERR(dp->bridge.next_bridge) != -ENODEV) { 2465 ret = PTR_ERR(dp->bridge.next_bridge); 2466 goto err_reset; 2467 } 2468 2469 dp->bridge.next_bridge = NULL; 2470 } 2471 2472 /* Initialize the hardware. */ 2473 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK; 2474 zynqmp_dp_set_format(dp, NULL, ZYNQMP_DPSUB_FORMAT_RGB, 8); 2475 2476 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 2477 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL); 2478 zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); 2479 zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1); 2480 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); 2481 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); 2482 2483 ret = zynqmp_dp_phy_init(dp); 2484 if (ret) 2485 goto err_reset; 2486 2487 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1); 2488 2489 /* 2490 * Now that the hardware is initialized and won't generate spurious 2491 * interrupts, request the IRQ. 2492 */ 2493 ret = devm_request_irq(dp->dev, dp->irq, zynqmp_dp_irq_handler, 2494 IRQF_SHARED, dev_name(dp->dev), dp); 2495 if (ret < 0) 2496 goto err_phy_exit; 2497 2498 dpsub->dp = dp; 2499 2500 dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n", 2501 dp->num_lanes); 2502 2503 return 0; 2504 2505 err_phy_exit: 2506 zynqmp_dp_phy_exit(dp); 2507 err_reset: 2508 zynqmp_dp_reset(dp, true); 2509 return ret; 2510 } 2511 2512 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub) 2513 { 2514 struct zynqmp_dp *dp = dpsub->dp; 2515 2516 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL); 2517 devm_free_irq(dp->dev, dp->irq, dp); 2518 2519 cancel_work_sync(&dp->hpd_irq_work); 2520 cancel_work_sync(&dp->hpd_work); 2521 2522 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); 2523 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); 2524 2525 zynqmp_dp_phy_exit(dp); 2526 zynqmp_dp_reset(dp, true); 2527 mutex_destroy(&dp->lock); 2528 } 2529