1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP DisplayPort Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/display/drm_dp_helper.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_device.h> 16 #include <drm/drm_edid.h> 17 #include <drm/drm_fourcc.h> 18 #include <drm/drm_modes.h> 19 #include <drm/drm_of.h> 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/io.h> 25 #include <linux/media-bus-format.h> 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/phy/phy.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 #include "zynqmp_disp.h" 34 #include "zynqmp_dp.h" 35 #include "zynqmp_dpsub.h" 36 #include "zynqmp_kms.h" 37 38 static uint zynqmp_dp_aux_timeout_ms = 50; 39 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); 40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); 41 42 /* 43 * Some sink requires a delay after power on request 44 */ 45 static uint zynqmp_dp_power_on_delay_ms = 4; 46 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); 47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)"); 48 49 /* Link configuration registers */ 50 #define ZYNQMP_DP_LINK_BW_SET 0x0 51 #define ZYNQMP_DP_LANE_COUNT_SET 0x4 52 #define ZYNQMP_DP_ENHANCED_FRAME_EN 0x8 53 #define ZYNQMP_DP_TRAINING_PATTERN_SET 0xc 54 #define ZYNQMP_DP_SCRAMBLING_DISABLE 0x14 55 #define ZYNQMP_DP_DOWNSPREAD_CTL 0x18 56 #define ZYNQMP_DP_SOFTWARE_RESET 0x1c 57 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1 BIT(0) 58 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2 BIT(1) 59 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3 BIT(2) 60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4 BIT(3) 61 #define ZYNQMP_DP_SOFTWARE_RESET_AUX BIT(7) 62 #define ZYNQMP_DP_SOFTWARE_RESET_ALL (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \ 63 ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \ 64 ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \ 65 ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \ 66 ZYNQMP_DP_SOFTWARE_RESET_AUX) 67 68 /* Core enable registers */ 69 #define ZYNQMP_DP_TRANSMITTER_ENABLE 0x80 70 #define ZYNQMP_DP_MAIN_STREAM_ENABLE 0x84 71 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET 0xc0 72 #define ZYNQMP_DP_VERSION 0xf8 73 #define ZYNQMP_DP_VERSION_MAJOR_MASK GENMASK(31, 24) 74 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT 24 75 #define ZYNQMP_DP_VERSION_MINOR_MASK GENMASK(23, 16) 76 #define ZYNQMP_DP_VERSION_MINOR_SHIFT 16 77 #define ZYNQMP_DP_VERSION_REVISION_MASK GENMASK(15, 12) 78 #define ZYNQMP_DP_VERSION_REVISION_SHIFT 12 79 #define ZYNQMP_DP_VERSION_PATCH_MASK GENMASK(11, 8) 80 #define ZYNQMP_DP_VERSION_PATCH_SHIFT 8 81 #define ZYNQMP_DP_VERSION_INTERNAL_MASK GENMASK(7, 0) 82 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT 0 83 84 /* Core ID registers */ 85 #define ZYNQMP_DP_CORE_ID 0xfc 86 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK GENMASK(31, 24) 87 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT 24 88 #define ZYNQMP_DP_CORE_ID_MINOR_MASK GENMASK(23, 16) 89 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT 16 90 #define ZYNQMP_DP_CORE_ID_REVISION_MASK GENMASK(15, 8) 91 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT 8 92 #define ZYNQMP_DP_CORE_ID_DIRECTION GENMASK(1) 93 94 /* AUX channel interface registers */ 95 #define ZYNQMP_DP_AUX_COMMAND 0x100 96 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT 8 97 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY BIT(12) 98 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT 0 99 #define ZYNQMP_DP_AUX_WRITE_FIFO 0x104 100 #define ZYNQMP_DP_AUX_ADDRESS 0x108 101 #define ZYNQMP_DP_AUX_CLK_DIVIDER 0x10c 102 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT 8 103 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE 0x130 104 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD BIT(0) 105 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST BIT(1) 106 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY BIT(2) 107 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT BIT(3) 108 #define ZYNQMP_DP_AUX_REPLY_DATA 0x134 109 #define ZYNQMP_DP_AUX_REPLY_CODE 0x138 110 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK (0) 111 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK BIT(0) 112 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER BIT(1) 113 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK (0) 114 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK BIT(2) 115 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER BIT(3) 116 #define ZYNQMP_DP_AUX_REPLY_COUNT 0x13c 117 #define ZYNQMP_DP_REPLY_DATA_COUNT 0x148 118 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK 0xff 119 #define ZYNQMP_DP_INT_STATUS 0x3a0 120 #define ZYNQMP_DP_INT_MASK 0x3a4 121 #define ZYNQMP_DP_INT_EN 0x3a8 122 #define ZYNQMP_DP_INT_DS 0x3ac 123 #define ZYNQMP_DP_INT_HPD_IRQ BIT(0) 124 #define ZYNQMP_DP_INT_HPD_EVENT BIT(1) 125 #define ZYNQMP_DP_INT_REPLY_RECEIVED BIT(2) 126 #define ZYNQMP_DP_INT_REPLY_TIMEOUT BIT(3) 127 #define ZYNQMP_DP_INT_HPD_PULSE_DET BIT(4) 128 #define ZYNQMP_DP_INT_EXT_PKT_TXD BIT(5) 129 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW BIT(12) 130 #define ZYNQMP_DP_INT_VBLANK_START BIT(13) 131 #define ZYNQMP_DP_INT_PIXEL1_MATCH BIT(14) 132 #define ZYNQMP_DP_INT_PIXEL0_MATCH BIT(15) 133 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK 0x3f0000 134 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK 0xfc00000 135 #define ZYNQMP_DP_INT_CUST_TS_2 BIT(28) 136 #define ZYNQMP_DP_INT_CUST_TS BIT(29) 137 #define ZYNQMP_DP_INT_EXT_VSYNC_TS BIT(30) 138 #define ZYNQMP_DP_INT_VSYNC_TS BIT(31) 139 #define ZYNQMP_DP_INT_ALL (ZYNQMP_DP_INT_HPD_IRQ | \ 140 ZYNQMP_DP_INT_HPD_EVENT | \ 141 ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \ 142 ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) 143 144 /* Main stream attribute registers */ 145 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL 0x180 146 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL 0x184 147 #define ZYNQMP_DP_MAIN_STREAM_POLARITY 0x188 148 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0 149 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1 150 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH 0x18c 151 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH 0x190 152 #define ZYNQMP_DP_MAIN_STREAM_HRES 0x194 153 #define ZYNQMP_DP_MAIN_STREAM_VRES 0x198 154 #define ZYNQMP_DP_MAIN_STREAM_HSTART 0x19c 155 #define ZYNQMP_DP_MAIN_STREAM_VSTART 0x1a0 156 #define ZYNQMP_DP_MAIN_STREAM_MISC0 0x1a4 157 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK BIT(0) 158 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB (0 << 1) 159 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422 (5 << 1) 160 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444 (6 << 1) 161 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK (7 << 1) 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE BIT(3) 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR BIT(4) 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6 (0 << 5) 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8 (1 << 5) 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10 (2 << 5) 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12 (3 << 5) 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16 (4 << 5) 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK (7 << 5) 170 #define ZYNQMP_DP_MAIN_STREAM_MISC1 0x1a8 171 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN BIT(7) 172 #define ZYNQMP_DP_MAIN_STREAM_M_VID 0x1ac 173 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE 0x1b0 174 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF 64 175 #define ZYNQMP_DP_MAIN_STREAM_N_VID 0x1b4 176 #define ZYNQMP_DP_USER_PIX_WIDTH 0x1b8 177 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE 0x1bc 178 #define ZYNQMP_DP_MIN_BYTES_PER_TU 0x1c4 179 #define ZYNQMP_DP_FRAC_BYTES_PER_TU 0x1c8 180 #define ZYNQMP_DP_INIT_WAIT 0x1cc 181 182 /* PHY configuration and status registers */ 183 #define ZYNQMP_DP_PHY_RESET 0x200 184 #define ZYNQMP_DP_PHY_RESET_PHY_RESET BIT(0) 185 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET BIT(1) 186 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET BIT(8) 187 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET BIT(9) 188 #define ZYNQMP_DP_PHY_RESET_ALL_RESET (ZYNQMP_DP_PHY_RESET_PHY_RESET | \ 189 ZYNQMP_DP_PHY_RESET_GTTX_RESET | \ 190 ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \ 191 ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET) 192 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0 0x210 193 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1 0x214 194 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2 0x218 195 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3 0x21c 196 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0 0x220 197 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1 0x224 198 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2 0x228 199 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3 0x22c 200 #define ZYNQMP_DP_PHY_CLOCK_SELECT 0x234 201 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G 0x1 202 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G 0x3 203 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G 0x5 204 #define ZYNQMP_DP_TX_PHY_POWER_DOWN 0x238 205 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0 BIT(0) 206 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1 BIT(1) 207 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2 BIT(2) 208 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3 BIT(3) 209 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL 0xf 210 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0 0x23c 211 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1 0x240 212 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2 0x244 213 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3 0x248 214 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0 0x24c 215 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1 0x250 216 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2 0x254 217 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3 0x258 218 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c 219 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250 220 #define ZYNQMP_DP_PHY_STATUS 0x280 221 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT 4 222 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED BIT(6) 223 224 /* Audio registers */ 225 #define ZYNQMP_DP_TX_AUDIO_CONTROL 0x300 226 #define ZYNQMP_DP_TX_AUDIO_CHANNELS 0x304 227 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA 0x308 228 #define ZYNQMP_DP_TX_M_AUD 0x328 229 #define ZYNQMP_DP_TX_N_AUD 0x32c 230 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA 0x330 231 232 #define ZYNQMP_DP_MAX_LANES 2 233 #define ZYNQMP_MAX_FREQ 3000000 234 235 #define DP_REDUCED_BIT_RATE 162000 236 #define DP_HIGH_BIT_RATE 270000 237 #define DP_HIGH_BIT_RATE2 540000 238 #define DP_MAX_TRAINING_TRIES 5 239 #define DP_V1_2 0x12 240 241 /** 242 * struct zynqmp_dp_link_config - Common link config between source and sink 243 * @max_rate: maximum link rate 244 * @max_lanes: maximum number of lanes 245 */ 246 struct zynqmp_dp_link_config { 247 int max_rate; 248 u8 max_lanes; 249 }; 250 251 /** 252 * struct zynqmp_dp_mode - Configured mode of DisplayPort 253 * @bw_code: code for bandwidth(link rate) 254 * @lane_cnt: number of lanes 255 * @pclock: pixel clock frequency of current mode 256 * @fmt: format identifier string 257 */ 258 struct zynqmp_dp_mode { 259 u8 bw_code; 260 u8 lane_cnt; 261 int pclock; 262 const char *fmt; 263 }; 264 265 /** 266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS 267 * @misc0: misc0 configuration (per DP v1.2 spec) 268 * @misc1: misc1 configuration (per DP v1.2 spec) 269 * @bpp: bits per pixel 270 */ 271 struct zynqmp_dp_config { 272 u8 misc0; 273 u8 misc1; 274 u8 bpp; 275 }; 276 277 /** 278 * struct zynqmp_dp - Xilinx DisplayPort core 279 * @dev: device structure 280 * @dpsub: Display subsystem 281 * @iomem: device I/O memory for register access 282 * @reset: reset controller 283 * @irq: irq 284 * @bridge: DRM bridge for the DP encoder 285 * @next_bridge: The downstream bridge 286 * @config: IP core configuration from DTS 287 * @aux: aux channel 288 * @phy: PHY handles for DP lanes 289 * @num_lanes: number of enabled phy lanes 290 * @hpd_work: hot plug detection worker 291 * @status: connection status 292 * @enabled: flag to indicate if the device is enabled 293 * @dpcd: DP configuration data from currently connected sink device 294 * @link_config: common link configuration between IP core and sink device 295 * @mode: current mode between IP core and sink device 296 * @train_set: set of training data 297 */ 298 struct zynqmp_dp { 299 struct device *dev; 300 struct zynqmp_dpsub *dpsub; 301 void __iomem *iomem; 302 struct reset_control *reset; 303 int irq; 304 305 struct drm_bridge bridge; 306 struct drm_bridge *next_bridge; 307 308 struct zynqmp_dp_config config; 309 struct drm_dp_aux aux; 310 struct phy *phy[ZYNQMP_DP_MAX_LANES]; 311 u8 num_lanes; 312 struct delayed_work hpd_work; 313 enum drm_connector_status status; 314 bool enabled; 315 316 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 317 struct zynqmp_dp_link_config link_config; 318 struct zynqmp_dp_mode mode; 319 u8 train_set[ZYNQMP_DP_MAX_LANES]; 320 }; 321 322 static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge) 323 { 324 return container_of(bridge, struct zynqmp_dp, bridge); 325 } 326 327 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val) 328 { 329 writel(val, dp->iomem + offset); 330 } 331 332 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset) 333 { 334 return readl(dp->iomem + offset); 335 } 336 337 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr) 338 { 339 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr); 340 } 341 342 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set) 343 { 344 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set); 345 } 346 347 /* ----------------------------------------------------------------------------- 348 * PHY Handling 349 */ 350 351 #define RST_TIMEOUT_MS 1000 352 353 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert) 354 { 355 unsigned long timeout; 356 357 if (assert) 358 reset_control_assert(dp->reset); 359 else 360 reset_control_deassert(dp->reset); 361 362 /* Wait for the (de)assert to complete. */ 363 timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS); 364 while (!time_after_eq(jiffies, timeout)) { 365 bool status = !!reset_control_status(dp->reset); 366 367 if (assert == status) 368 return 0; 369 370 cpu_relax(); 371 } 372 373 dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert"); 374 return -ETIMEDOUT; 375 } 376 377 /** 378 * zynqmp_dp_phy_init - Initialize the phy 379 * @dp: DisplayPort IP core structure 380 * 381 * Initialize the phy. 382 * 383 * Return: 0 if the phy instances are initialized correctly, or the error code 384 * returned from the callee functions. 385 */ 386 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp) 387 { 388 int ret; 389 int i; 390 391 for (i = 0; i < dp->num_lanes; i++) { 392 ret = phy_init(dp->phy[i]); 393 if (ret) { 394 dev_err(dp->dev, "failed to init phy lane %d\n", i); 395 return ret; 396 } 397 } 398 399 zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); 400 401 /* 402 * Power on lanes in reverse order as only lane 0 waits for the PLL to 403 * lock. 404 */ 405 for (i = dp->num_lanes - 1; i >= 0; i--) { 406 ret = phy_power_on(dp->phy[i]); 407 if (ret) { 408 dev_err(dp->dev, "failed to power on phy lane %d\n", i); 409 return ret; 410 } 411 } 412 413 return 0; 414 } 415 416 /** 417 * zynqmp_dp_phy_exit - Exit the phy 418 * @dp: DisplayPort IP core structure 419 * 420 * Exit the phy. 421 */ 422 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp) 423 { 424 unsigned int i; 425 int ret; 426 427 for (i = 0; i < dp->num_lanes; i++) { 428 ret = phy_power_off(dp->phy[i]); 429 if (ret) 430 dev_err(dp->dev, "failed to power off phy(%d) %d\n", i, 431 ret); 432 } 433 434 for (i = 0; i < dp->num_lanes; i++) { 435 ret = phy_exit(dp->phy[i]); 436 if (ret) 437 dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret); 438 } 439 } 440 441 /** 442 * zynqmp_dp_phy_probe - Probe the PHYs 443 * @dp: DisplayPort IP core structure 444 * 445 * Probe PHYs for all lanes. Less PHYs may be available than the number of 446 * lanes, which is not considered an error as long as at least one PHY is 447 * found. The caller can check dp->num_lanes to check how many PHYs were found. 448 * 449 * Return: 450 * * 0 - Success 451 * * -ENXIO - No PHY found 452 * * -EPROBE_DEFER - Probe deferral requested 453 * * Other negative value - PHY retrieval failure 454 */ 455 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp) 456 { 457 unsigned int i; 458 459 for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) { 460 char phy_name[16]; 461 struct phy *phy; 462 463 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i); 464 phy = devm_phy_get(dp->dev, phy_name); 465 466 if (IS_ERR(phy)) { 467 switch (PTR_ERR(phy)) { 468 case -ENODEV: 469 if (dp->num_lanes) 470 return 0; 471 472 dev_err(dp->dev, "no PHY found\n"); 473 return -ENXIO; 474 475 case -EPROBE_DEFER: 476 return -EPROBE_DEFER; 477 478 default: 479 dev_err(dp->dev, "failed to get PHY lane %u\n", 480 i); 481 return PTR_ERR(phy); 482 } 483 } 484 485 dp->phy[i] = phy; 486 dp->num_lanes++; 487 } 488 489 return 0; 490 } 491 492 /** 493 * zynqmp_dp_phy_ready - Check if PHY is ready 494 * @dp: DisplayPort IP core structure 495 * 496 * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. 497 * This amount of delay was suggested by IP designer. 498 * 499 * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready. 500 */ 501 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp) 502 { 503 u32 i, reg, ready; 504 505 ready = (1 << dp->num_lanes) - 1; 506 507 /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */ 508 for (i = 0; ; i++) { 509 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS); 510 if ((reg & ready) == ready) 511 return 0; 512 513 if (i == 100) { 514 dev_err(dp->dev, "PHY isn't ready\n"); 515 return -ENODEV; 516 } 517 518 usleep_range(1000, 1100); 519 } 520 521 return 0; 522 } 523 524 /* ----------------------------------------------------------------------------- 525 * DisplayPort Link Training 526 */ 527 528 /** 529 * zynqmp_dp_max_rate - Calculate and return available max pixel clock 530 * @link_rate: link rate (Kilo-bytes / sec) 531 * @lane_num: number of lanes 532 * @bpp: bits per pixel 533 * 534 * Return: max pixel clock (KHz) supported by current link config. 535 */ 536 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp) 537 { 538 return link_rate * lane_num * 8 / bpp; 539 } 540 541 /** 542 * zynqmp_dp_mode_configure - Configure the link values 543 * @dp: DisplayPort IP core structure 544 * @pclock: pixel clock for requested display mode 545 * @current_bw: current link rate 546 * 547 * Find the link configuration values, rate and lane count for requested pixel 548 * clock @pclock. The @pclock is stored in the mode to be used in other 549 * functions later. The returned rate is downshifted from the current rate 550 * @current_bw. 551 * 552 * Return: Current link rate code, or -EINVAL. 553 */ 554 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, 555 u8 current_bw) 556 { 557 int max_rate = dp->link_config.max_rate; 558 u8 bw_code; 559 u8 max_lanes = dp->link_config.max_lanes; 560 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate); 561 u8 bpp = dp->config.bpp; 562 u8 lane_cnt; 563 564 /* Downshift from current bandwidth */ 565 switch (current_bw) { 566 case DP_LINK_BW_5_4: 567 bw_code = DP_LINK_BW_2_7; 568 break; 569 case DP_LINK_BW_2_7: 570 bw_code = DP_LINK_BW_1_62; 571 break; 572 case DP_LINK_BW_1_62: 573 dev_err(dp->dev, "can't downshift. already lowest link rate\n"); 574 return -EINVAL; 575 default: 576 /* If not given, start with max supported */ 577 bw_code = max_link_rate_code; 578 break; 579 } 580 581 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { 582 int bw; 583 u32 rate; 584 585 bw = drm_dp_bw_code_to_link_rate(bw_code); 586 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp); 587 if (pclock <= rate) { 588 dp->mode.bw_code = bw_code; 589 dp->mode.lane_cnt = lane_cnt; 590 dp->mode.pclock = pclock; 591 return dp->mode.bw_code; 592 } 593 } 594 595 dev_err(dp->dev, "failed to configure link values\n"); 596 597 return -EINVAL; 598 } 599 600 /** 601 * zynqmp_dp_adjust_train - Adjust train values 602 * @dp: DisplayPort IP core structure 603 * @link_status: link status from sink which contains requested training values 604 */ 605 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp, 606 u8 link_status[DP_LINK_STATUS_SIZE]) 607 { 608 u8 *train_set = dp->train_set; 609 u8 voltage = 0, preemphasis = 0; 610 u8 i; 611 612 for (i = 0; i < dp->mode.lane_cnt; i++) { 613 u8 v = drm_dp_get_adjust_request_voltage(link_status, i); 614 u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i); 615 616 if (v > voltage) 617 voltage = v; 618 619 if (p > preemphasis) 620 preemphasis = p; 621 } 622 623 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3) 624 voltage |= DP_TRAIN_MAX_SWING_REACHED; 625 626 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2) 627 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 628 629 for (i = 0; i < dp->mode.lane_cnt; i++) 630 train_set[i] = voltage | preemphasis; 631 } 632 633 /** 634 * zynqmp_dp_update_vs_emph - Update the training values 635 * @dp: DisplayPort IP core structure 636 * 637 * Update the training values based on the request from sink. The mapped values 638 * are predefined, and values(vs, pe, pc) are from the device manual. 639 * 640 * Return: 0 if vs and emph are updated successfully, or the error code returned 641 * by drm_dp_dpcd_write(). 642 */ 643 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp) 644 { 645 unsigned int i; 646 int ret; 647 648 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, 649 dp->mode.lane_cnt); 650 if (ret < 0) 651 return ret; 652 653 for (i = 0; i < dp->mode.lane_cnt; i++) { 654 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4; 655 union phy_configure_opts opts = { 0 }; 656 u8 train = dp->train_set[i]; 657 658 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK) 659 >> DP_TRAIN_VOLTAGE_SWING_SHIFT; 660 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) 661 >> DP_TRAIN_PRE_EMPHASIS_SHIFT; 662 663 phy_configure(dp->phy[i], &opts); 664 665 zynqmp_dp_write(dp, reg, 0x2); 666 } 667 668 return 0; 669 } 670 671 /** 672 * zynqmp_dp_link_train_cr - Train clock recovery 673 * @dp: DisplayPort IP core structure 674 * 675 * Return: 0 if clock recovery train is done successfully, or corresponding 676 * error code. 677 */ 678 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) 679 { 680 u8 link_status[DP_LINK_STATUS_SIZE]; 681 u8 lane_cnt = dp->mode.lane_cnt; 682 u8 vs = 0, tries = 0; 683 u16 max_tries, i; 684 bool cr_done; 685 int ret; 686 687 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, 688 DP_TRAINING_PATTERN_1); 689 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 690 DP_TRAINING_PATTERN_1 | 691 DP_LINK_SCRAMBLING_DISABLE); 692 if (ret < 0) 693 return ret; 694 695 /* 696 * 256 loops should be maximum iterations for 4 lanes and 4 values. 697 * So, This loop should exit before 512 iterations 698 */ 699 for (max_tries = 0; max_tries < 512; max_tries++) { 700 ret = zynqmp_dp_update_vs_emph(dp); 701 if (ret) 702 return ret; 703 704 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); 705 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); 706 if (ret < 0) 707 return ret; 708 709 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt); 710 if (cr_done) 711 break; 712 713 for (i = 0; i < lane_cnt; i++) 714 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) 715 break; 716 if (i == lane_cnt) 717 break; 718 719 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) 720 tries++; 721 else 722 tries = 0; 723 724 if (tries == DP_MAX_TRAINING_TRIES) 725 break; 726 727 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 728 zynqmp_dp_adjust_train(dp, link_status); 729 } 730 731 if (!cr_done) 732 return -EIO; 733 734 return 0; 735 } 736 737 /** 738 * zynqmp_dp_link_train_ce - Train channel equalization 739 * @dp: DisplayPort IP core structure 740 * 741 * Return: 0 if channel equalization train is done successfully, or 742 * corresponding error code. 743 */ 744 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) 745 { 746 u8 link_status[DP_LINK_STATUS_SIZE]; 747 u8 lane_cnt = dp->mode.lane_cnt; 748 u32 pat, tries; 749 int ret; 750 bool ce_done; 751 752 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && 753 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) 754 pat = DP_TRAINING_PATTERN_3; 755 else 756 pat = DP_TRAINING_PATTERN_2; 757 758 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat); 759 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 760 pat | DP_LINK_SCRAMBLING_DISABLE); 761 if (ret < 0) 762 return ret; 763 764 for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) { 765 ret = zynqmp_dp_update_vs_emph(dp); 766 if (ret) 767 return ret; 768 769 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); 770 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); 771 if (ret < 0) 772 return ret; 773 774 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt); 775 if (ce_done) 776 break; 777 778 zynqmp_dp_adjust_train(dp, link_status); 779 } 780 781 if (!ce_done) 782 return -EIO; 783 784 return 0; 785 } 786 787 /** 788 * zynqmp_dp_train - Train the link 789 * @dp: DisplayPort IP core structure 790 * 791 * Return: 0 if all trains are done successfully, or corresponding error code. 792 */ 793 static int zynqmp_dp_train(struct zynqmp_dp *dp) 794 { 795 u32 reg; 796 u8 bw_code = dp->mode.bw_code; 797 u8 lane_cnt = dp->mode.lane_cnt; 798 u8 aux_lane_cnt = lane_cnt; 799 bool enhanced; 800 int ret; 801 802 zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt); 803 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd); 804 if (enhanced) { 805 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1); 806 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 807 } 808 809 if (dp->dpcd[3] & 0x1) { 810 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1); 811 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 812 DP_SPREAD_AMP_0_5); 813 } else { 814 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0); 815 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0); 816 } 817 818 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt); 819 if (ret < 0) { 820 dev_err(dp->dev, "failed to set lane count\n"); 821 return ret; 822 } 823 824 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 825 DP_SET_ANSI_8B10B); 826 if (ret < 0) { 827 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n"); 828 return ret; 829 } 830 831 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code); 832 if (ret < 0) { 833 dev_err(dp->dev, "failed to set DP bandwidth\n"); 834 return ret; 835 } 836 837 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code); 838 switch (bw_code) { 839 case DP_LINK_BW_1_62: 840 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G; 841 break; 842 case DP_LINK_BW_2_7: 843 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G; 844 break; 845 case DP_LINK_BW_5_4: 846 default: 847 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G; 848 break; 849 } 850 851 zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg); 852 ret = zynqmp_dp_phy_ready(dp); 853 if (ret < 0) 854 return ret; 855 856 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1); 857 memset(dp->train_set, 0, sizeof(dp->train_set)); 858 ret = zynqmp_dp_link_train_cr(dp); 859 if (ret) 860 return ret; 861 862 ret = zynqmp_dp_link_train_ce(dp); 863 if (ret) 864 return ret; 865 866 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 867 DP_TRAINING_PATTERN_DISABLE); 868 if (ret < 0) { 869 dev_err(dp->dev, "failed to disable training pattern\n"); 870 return ret; 871 } 872 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, 873 DP_TRAINING_PATTERN_DISABLE); 874 875 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0); 876 877 return 0; 878 } 879 880 /** 881 * zynqmp_dp_train_loop - Downshift the link rate during training 882 * @dp: DisplayPort IP core structure 883 * 884 * Train the link by downshifting the link rate if training is not successful. 885 */ 886 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp) 887 { 888 struct zynqmp_dp_mode *mode = &dp->mode; 889 u8 bw = mode->bw_code; 890 int ret; 891 892 do { 893 if (dp->status == connector_status_disconnected || 894 !dp->enabled) 895 return; 896 897 ret = zynqmp_dp_train(dp); 898 if (!ret) 899 return; 900 901 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw); 902 if (ret < 0) 903 goto err_out; 904 905 bw = ret; 906 } while (bw >= DP_LINK_BW_1_62); 907 908 err_out: 909 dev_err(dp->dev, "failed to train the DP link\n"); 910 } 911 912 /* ----------------------------------------------------------------------------- 913 * DisplayPort AUX 914 */ 915 916 #define AUX_READ_BIT 0x1 917 918 /** 919 * zynqmp_dp_aux_cmd_submit - Submit aux command 920 * @dp: DisplayPort IP core structure 921 * @cmd: aux command 922 * @addr: aux address 923 * @buf: buffer for command data 924 * @bytes: number of bytes for @buf 925 * @reply: reply code to be returned 926 * 927 * Submit an aux command. All aux related commands, native or i2c aux 928 * read/write, are submitted through this function. The function is mapped to 929 * the transfer function of struct drm_dp_aux. This function involves in 930 * multiple register reads/writes, thus synchronization is needed, and it is 931 * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep 932 * if there's no immediate reply to the command submission. The reply code is 933 * returned at @reply if @reply != NULL. 934 * 935 * Return: 0 if the command is submitted properly, or corresponding error code: 936 * -EBUSY when there is any request already being processed 937 * -ETIMEDOUT when receiving reply is timed out 938 * -EIO when received bytes are less than requested 939 */ 940 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, 941 u8 *buf, u8 bytes, u8 *reply) 942 { 943 bool is_read = (cmd & AUX_READ_BIT) ? true : false; 944 u32 reg, i; 945 946 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 947 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST) 948 return -EBUSY; 949 950 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr); 951 if (!is_read) 952 for (i = 0; i < bytes; i++) 953 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO, 954 buf[i]); 955 956 reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT; 957 if (!buf || !bytes) 958 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY; 959 else 960 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT; 961 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg); 962 963 /* Wait for reply to be delivered upto 2ms */ 964 for (i = 0; ; i++) { 965 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 966 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY) 967 break; 968 969 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT || 970 i == 2) 971 return -ETIMEDOUT; 972 973 usleep_range(1000, 1100); 974 } 975 976 reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE); 977 if (reply) 978 *reply = reg; 979 980 if (is_read && 981 (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK || 982 reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) { 983 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT); 984 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes) 985 return -EIO; 986 987 for (i = 0; i < bytes; i++) 988 buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA); 989 } 990 991 return 0; 992 } 993 994 static ssize_t 995 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 996 { 997 struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux); 998 int ret; 999 unsigned int i, iter; 1000 1001 /* Number of loops = timeout in msec / aux delay (400 usec) */ 1002 iter = zynqmp_dp_aux_timeout_ms * 1000 / 400; 1003 iter = iter ? iter : 1; 1004 1005 for (i = 0; i < iter; i++) { 1006 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address, 1007 msg->buffer, msg->size, 1008 &msg->reply); 1009 if (!ret) { 1010 dev_dbg(dp->dev, "aux %d retries\n", i); 1011 return msg->size; 1012 } 1013 1014 if (dp->status == connector_status_disconnected) { 1015 dev_dbg(dp->dev, "no connected aux device\n"); 1016 return -ENODEV; 1017 } 1018 1019 usleep_range(400, 500); 1020 } 1021 1022 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret); 1023 1024 return ret; 1025 } 1026 1027 /** 1028 * zynqmp_dp_aux_init - Initialize and register the DP AUX 1029 * @dp: DisplayPort IP core structure 1030 * 1031 * Program the AUX clock divider and filter and register the DP AUX adapter. 1032 * 1033 * Return: 0 on success, error value otherwise 1034 */ 1035 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp) 1036 { 1037 unsigned long rate; 1038 unsigned int w; 1039 1040 /* 1041 * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles 1042 * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32, 1043 * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs, 1044 * compute the w / 8 value corresponding to 0.4µs rounded up, and make 1045 * sure it stays below 0.6µs and within the allowable values. 1046 */ 1047 rate = clk_get_rate(dp->dpsub->apb_clk); 1048 w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8; 1049 if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) { 1050 dev_err(dp->dev, "aclk frequency too high\n"); 1051 return -EINVAL; 1052 } 1053 1054 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER, 1055 (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) | 1056 (rate / (1000 * 1000))); 1057 1058 dp->aux.name = "ZynqMP DP AUX"; 1059 dp->aux.dev = dp->dev; 1060 dp->aux.drm_dev = dp->bridge.dev; 1061 dp->aux.transfer = zynqmp_dp_aux_transfer; 1062 1063 return drm_dp_aux_register(&dp->aux); 1064 } 1065 1066 /** 1067 * zynqmp_dp_aux_cleanup - Cleanup the DP AUX 1068 * @dp: DisplayPort IP core structure 1069 * 1070 * Unregister the DP AUX adapter. 1071 */ 1072 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp) 1073 { 1074 drm_dp_aux_unregister(&dp->aux); 1075 } 1076 1077 /* ----------------------------------------------------------------------------- 1078 * DisplayPort Generic Support 1079 */ 1080 1081 /** 1082 * zynqmp_dp_update_misc - Write the misc registers 1083 * @dp: DisplayPort IP core structure 1084 * 1085 * The misc register values are stored in the structure, and this 1086 * function applies the values into the registers. 1087 */ 1088 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp) 1089 { 1090 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0); 1091 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1); 1092 } 1093 1094 /** 1095 * zynqmp_dp_set_format - Set the input format 1096 * @dp: DisplayPort IP core structure 1097 * @info: Display info 1098 * @format: input format 1099 * @bpc: bits per component 1100 * 1101 * Update misc register values based on input @format and @bpc. 1102 * 1103 * Return: 0 on success, or -EINVAL. 1104 */ 1105 static int zynqmp_dp_set_format(struct zynqmp_dp *dp, 1106 const struct drm_display_info *info, 1107 enum zynqmp_dpsub_format format, 1108 unsigned int bpc) 1109 { 1110 struct zynqmp_dp_config *config = &dp->config; 1111 unsigned int num_colors; 1112 1113 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK; 1114 config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; 1115 1116 switch (format) { 1117 case ZYNQMP_DPSUB_FORMAT_RGB: 1118 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB; 1119 num_colors = 3; 1120 break; 1121 1122 case ZYNQMP_DPSUB_FORMAT_YCRCB444: 1123 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444; 1124 num_colors = 3; 1125 break; 1126 1127 case ZYNQMP_DPSUB_FORMAT_YCRCB422: 1128 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422; 1129 num_colors = 2; 1130 break; 1131 1132 case ZYNQMP_DPSUB_FORMAT_YONLY: 1133 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; 1134 num_colors = 1; 1135 break; 1136 1137 default: 1138 dev_err(dp->dev, "Invalid colormetry in DT\n"); 1139 return -EINVAL; 1140 } 1141 1142 if (info && info->bpc && bpc > info->bpc) { 1143 dev_warn(dp->dev, 1144 "downgrading requested %ubpc to display limit %ubpc\n", 1145 bpc, info->bpc); 1146 bpc = info->bpc; 1147 } 1148 1149 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK; 1150 1151 switch (bpc) { 1152 case 6: 1153 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6; 1154 break; 1155 case 8: 1156 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; 1157 break; 1158 case 10: 1159 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10; 1160 break; 1161 case 12: 1162 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12; 1163 break; 1164 case 16: 1165 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16; 1166 break; 1167 default: 1168 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n", 1169 bpc); 1170 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; 1171 bpc = 8; 1172 break; 1173 } 1174 1175 /* Update the current bpp based on the format. */ 1176 config->bpp = bpc * num_colors; 1177 1178 return 0; 1179 } 1180 1181 /** 1182 * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values 1183 * @dp: DisplayPort IP core structure 1184 * @mode: requested display mode 1185 * 1186 * Set the transfer unit, and calculate all transfer unit size related values. 1187 * Calculation is based on DP and IP core specification. 1188 */ 1189 static void 1190 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, 1191 const struct drm_display_mode *mode) 1192 { 1193 u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF; 1194 u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait; 1195 1196 /* Use the max transfer unit size (default) */ 1197 zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu); 1198 1199 vid_kbytes = mode->clock * (dp->config.bpp / 8); 1200 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1201 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000); 1202 zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU, 1203 avg_bytes_per_tu / 1000); 1204 zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU, 1205 avg_bytes_per_tu % 1000); 1206 1207 /* Configure the initial wait cycle based on transfer unit size */ 1208 if (tu < (avg_bytes_per_tu / 1000)) 1209 init_wait = 0; 1210 else if ((avg_bytes_per_tu / 1000) <= 4) 1211 init_wait = tu; 1212 else 1213 init_wait = tu - avg_bytes_per_tu / 1000; 1214 1215 zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait); 1216 } 1217 1218 /** 1219 * zynqmp_dp_encoder_mode_set_stream - Configure the main stream 1220 * @dp: DisplayPort IP core structure 1221 * @mode: requested display mode 1222 * 1223 * Configure the main stream based on the requested mode @mode. Calculation is 1224 * based on IP core specification. 1225 */ 1226 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, 1227 const struct drm_display_mode *mode) 1228 { 1229 u8 lane_cnt = dp->mode.lane_cnt; 1230 u32 reg, wpl; 1231 unsigned int rate; 1232 1233 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal); 1234 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal); 1235 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY, 1236 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) << 1237 ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) | 1238 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) << 1239 ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT)); 1240 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH, 1241 mode->hsync_end - mode->hsync_start); 1242 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH, 1243 mode->vsync_end - mode->vsync_start); 1244 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay); 1245 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay); 1246 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART, 1247 mode->htotal - mode->hsync_start); 1248 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART, 1249 mode->vtotal - mode->vsync_start); 1250 1251 /* In synchronous mode, set the dividers */ 1252 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) { 1253 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1254 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg); 1255 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock); 1256 rate = zynqmp_dpsub_get_audio_clk_rate(dp->dpsub); 1257 if (rate) { 1258 dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512); 1259 zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg); 1260 zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000); 1261 } 1262 } 1263 1264 /* Only 2 channel audio is supported now */ 1265 if (zynqmp_dpsub_audio_enabled(dp->dpsub)) 1266 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1); 1267 1268 zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1); 1269 1270 /* Translate to the native 16 bit datapath based on IP core spec */ 1271 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16; 1272 reg = wpl + wpl % lane_cnt - lane_cnt; 1273 zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg); 1274 } 1275 1276 /* ----------------------------------------------------------------------------- 1277 * DISP Configuration 1278 */ 1279 1280 /** 1281 * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer 1282 * @dp: DisplayPort IP core structure 1283 * 1284 * Return: The first connected live display layer or NULL if none of the live 1285 * layers are connected. 1286 */ 1287 static struct zynqmp_disp_layer * 1288 zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp) 1289 { 1290 if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) 1291 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID]; 1292 else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX)) 1293 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX]; 1294 else 1295 return NULL; 1296 } 1297 1298 static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, 1299 struct drm_bridge_state *old_bridge_state) 1300 { 1301 struct zynqmp_disp_layer *layer; 1302 struct drm_bridge_state *bridge_state; 1303 u32 bus_fmt; 1304 1305 layer = zynqmp_dp_disp_connected_live_layer(dp); 1306 if (!layer) 1307 return; 1308 1309 bridge_state = drm_atomic_get_new_bridge_state(old_bridge_state->base.state, 1310 old_bridge_state->bridge); 1311 if (WARN_ON(!bridge_state)) 1312 return; 1313 1314 bus_fmt = bridge_state->input_bus_cfg.format; 1315 zynqmp_disp_layer_set_live_format(layer, bus_fmt); 1316 zynqmp_disp_layer_enable(layer); 1317 1318 if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX]) 1319 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255); 1320 else 1321 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, false, 0); 1322 1323 zynqmp_disp_enable(dp->dpsub->disp); 1324 } 1325 1326 static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp, 1327 struct drm_bridge_state *old_bridge_state) 1328 { 1329 struct zynqmp_disp_layer *layer; 1330 1331 layer = zynqmp_dp_disp_connected_live_layer(dp); 1332 if (!layer) 1333 return; 1334 1335 zynqmp_disp_disable(dp->dpsub->disp); 1336 zynqmp_disp_layer_disable(layer); 1337 } 1338 1339 /* ----------------------------------------------------------------------------- 1340 * DRM Bridge 1341 */ 1342 1343 static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge, 1344 enum drm_bridge_attach_flags flags) 1345 { 1346 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1347 int ret; 1348 1349 /* Initialize and register the AUX adapter. */ 1350 ret = zynqmp_dp_aux_init(dp); 1351 if (ret) { 1352 dev_err(dp->dev, "failed to initialize DP aux\n"); 1353 return ret; 1354 } 1355 1356 if (dp->next_bridge) { 1357 ret = drm_bridge_attach(bridge->encoder, dp->next_bridge, 1358 bridge, flags); 1359 if (ret < 0) 1360 goto error; 1361 } 1362 1363 /* Now that initialisation is complete, enable interrupts. */ 1364 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL); 1365 1366 return 0; 1367 1368 error: 1369 zynqmp_dp_aux_cleanup(dp); 1370 return ret; 1371 } 1372 1373 static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge) 1374 { 1375 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1376 1377 zynqmp_dp_aux_cleanup(dp); 1378 } 1379 1380 static enum drm_mode_status 1381 zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge, 1382 const struct drm_display_info *info, 1383 const struct drm_display_mode *mode) 1384 { 1385 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1386 int rate; 1387 1388 if (mode->clock > ZYNQMP_MAX_FREQ) { 1389 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n", 1390 mode->name); 1391 drm_mode_debug_printmodeline(mode); 1392 return MODE_CLOCK_HIGH; 1393 } 1394 1395 /* Check with link rate and lane count */ 1396 rate = zynqmp_dp_max_rate(dp->link_config.max_rate, 1397 dp->link_config.max_lanes, dp->config.bpp); 1398 if (mode->clock > rate) { 1399 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n", 1400 mode->name); 1401 drm_mode_debug_printmodeline(mode); 1402 return MODE_CLOCK_HIGH; 1403 } 1404 1405 return MODE_OK; 1406 } 1407 1408 static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge, 1409 struct drm_bridge_state *old_bridge_state) 1410 { 1411 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1412 struct drm_atomic_state *state = old_bridge_state->base.state; 1413 const struct drm_crtc_state *crtc_state; 1414 const struct drm_display_mode *adjusted_mode; 1415 const struct drm_display_mode *mode; 1416 struct drm_connector *connector; 1417 struct drm_crtc *crtc; 1418 unsigned int i; 1419 int rate; 1420 int ret; 1421 1422 pm_runtime_get_sync(dp->dev); 1423 1424 zynqmp_dp_disp_enable(dp, old_bridge_state); 1425 1426 /* 1427 * Retrieve the CRTC mode and adjusted mode. This requires a little 1428 * dance to go from the bridge to the encoder, to the connector and to 1429 * the CRTC. 1430 */ 1431 connector = drm_atomic_get_new_connector_for_encoder(state, 1432 bridge->encoder); 1433 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 1434 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1435 adjusted_mode = &crtc_state->adjusted_mode; 1436 mode = &crtc_state->mode; 1437 1438 zynqmp_dp_set_format(dp, &connector->display_info, 1439 ZYNQMP_DPSUB_FORMAT_RGB, 8); 1440 1441 /* Check again as bpp or format might have been changed */ 1442 rate = zynqmp_dp_max_rate(dp->link_config.max_rate, 1443 dp->link_config.max_lanes, dp->config.bpp); 1444 if (mode->clock > rate) { 1445 dev_err(dp->dev, "mode %s has too high pixel rate\n", 1446 mode->name); 1447 drm_mode_debug_printmodeline(mode); 1448 } 1449 1450 /* Configure the mode */ 1451 ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0); 1452 if (ret < 0) { 1453 pm_runtime_put_sync(dp->dev); 1454 return; 1455 } 1456 1457 zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode); 1458 zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode); 1459 1460 /* Enable the encoder */ 1461 dp->enabled = true; 1462 zynqmp_dp_update_misc(dp); 1463 if (zynqmp_dpsub_audio_enabled(dp->dpsub)) 1464 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1); 1465 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0); 1466 if (dp->status == connector_status_connected) { 1467 for (i = 0; i < 3; i++) { 1468 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, 1469 DP_SET_POWER_D0); 1470 if (ret == 1) 1471 break; 1472 usleep_range(300, 500); 1473 } 1474 /* Some monitors take time to wake up properly */ 1475 msleep(zynqmp_dp_power_on_delay_ms); 1476 } 1477 if (ret != 1) 1478 dev_dbg(dp->dev, "DP aux failed\n"); 1479 else 1480 zynqmp_dp_train_loop(dp); 1481 zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET, 1482 ZYNQMP_DP_SOFTWARE_RESET_ALL); 1483 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1); 1484 } 1485 1486 static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge, 1487 struct drm_bridge_state *old_bridge_state) 1488 { 1489 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1490 1491 dp->enabled = false; 1492 cancel_delayed_work(&dp->hpd_work); 1493 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0); 1494 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3); 1495 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 1496 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL); 1497 if (zynqmp_dpsub_audio_enabled(dp->dpsub)) 1498 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0); 1499 1500 zynqmp_dp_disp_disable(dp, old_bridge_state); 1501 1502 pm_runtime_put_sync(dp->dev); 1503 } 1504 1505 #define ZYNQMP_DP_MIN_H_BACKPORCH 20 1506 1507 static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge, 1508 struct drm_bridge_state *bridge_state, 1509 struct drm_crtc_state *crtc_state, 1510 struct drm_connector_state *conn_state) 1511 { 1512 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1513 struct drm_display_mode *mode = &crtc_state->mode; 1514 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1515 int diff = mode->htotal - mode->hsync_end; 1516 1517 /* 1518 * ZynqMP DP requires horizontal backporch to be greater than 12. 1519 * This limitation may not be compatible with the sink device. 1520 */ 1521 if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) { 1522 int vrefresh = (adjusted_mode->clock * 1000) / 1523 (adjusted_mode->vtotal * adjusted_mode->htotal); 1524 1525 dev_dbg(dp->dev, "hbackporch adjusted: %d to %d", 1526 diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff); 1527 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff; 1528 adjusted_mode->htotal += diff; 1529 adjusted_mode->clock = adjusted_mode->vtotal * 1530 adjusted_mode->htotal * vrefresh / 1000; 1531 } 1532 1533 return 0; 1534 } 1535 1536 static enum drm_connector_status zynqmp_dp_bridge_detect(struct drm_bridge *bridge) 1537 { 1538 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1539 struct zynqmp_dp_link_config *link_config = &dp->link_config; 1540 u32 state, i; 1541 int ret; 1542 1543 /* 1544 * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to 1545 * get the HPD signal with some monitors. 1546 */ 1547 for (i = 0; i < 10; i++) { 1548 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1549 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) 1550 break; 1551 msleep(100); 1552 } 1553 1554 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) { 1555 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, 1556 sizeof(dp->dpcd)); 1557 if (ret < 0) { 1558 dev_dbg(dp->dev, "DPCD read failed"); 1559 goto disconnected; 1560 } 1561 1562 link_config->max_rate = min_t(int, 1563 drm_dp_max_link_rate(dp->dpcd), 1564 DP_HIGH_BIT_RATE2); 1565 link_config->max_lanes = min_t(u8, 1566 drm_dp_max_lane_count(dp->dpcd), 1567 dp->num_lanes); 1568 1569 dp->status = connector_status_connected; 1570 return connector_status_connected; 1571 } 1572 1573 disconnected: 1574 dp->status = connector_status_disconnected; 1575 return connector_status_disconnected; 1576 } 1577 1578 static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge, 1579 struct drm_connector *connector) 1580 { 1581 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1582 1583 return drm_edid_read_ddc(connector, &dp->aux.ddc); 1584 } 1585 1586 static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts) 1587 { 1588 u32 *formats = kzalloc(sizeof(*formats), GFP_KERNEL); 1589 1590 if (formats) 1591 *formats = MEDIA_BUS_FMT_FIXED; 1592 *num_input_fmts = !!formats; 1593 1594 return formats; 1595 } 1596 1597 static u32 * 1598 zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge, 1599 struct drm_bridge_state *bridge_state, 1600 struct drm_crtc_state *crtc_state, 1601 struct drm_connector_state *conn_state, 1602 u32 output_fmt, 1603 unsigned int *num_input_fmts) 1604 { 1605 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1606 struct zynqmp_disp_layer *layer; 1607 1608 layer = zynqmp_dp_disp_connected_live_layer(dp); 1609 if (layer) 1610 return zynqmp_disp_live_layer_formats(layer, num_input_fmts); 1611 else 1612 return zynqmp_dp_bridge_default_bus_fmts(num_input_fmts); 1613 } 1614 1615 static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = { 1616 .attach = zynqmp_dp_bridge_attach, 1617 .detach = zynqmp_dp_bridge_detach, 1618 .mode_valid = zynqmp_dp_bridge_mode_valid, 1619 .atomic_enable = zynqmp_dp_bridge_atomic_enable, 1620 .atomic_disable = zynqmp_dp_bridge_atomic_disable, 1621 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1622 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1623 .atomic_reset = drm_atomic_helper_bridge_reset, 1624 .atomic_check = zynqmp_dp_bridge_atomic_check, 1625 .detect = zynqmp_dp_bridge_detect, 1626 .edid_read = zynqmp_dp_bridge_edid_read, 1627 .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts, 1628 }; 1629 1630 /* ----------------------------------------------------------------------------- 1631 * Interrupt Handling 1632 */ 1633 1634 /** 1635 * zynqmp_dp_enable_vblank - Enable vblank 1636 * @dp: DisplayPort IP core structure 1637 * 1638 * Enable vblank interrupt 1639 */ 1640 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp) 1641 { 1642 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START); 1643 } 1644 1645 /** 1646 * zynqmp_dp_disable_vblank - Disable vblank 1647 * @dp: DisplayPort IP core structure 1648 * 1649 * Disable vblank interrupt 1650 */ 1651 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp) 1652 { 1653 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START); 1654 } 1655 1656 static void zynqmp_dp_hpd_work_func(struct work_struct *work) 1657 { 1658 struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, 1659 hpd_work.work); 1660 enum drm_connector_status status; 1661 1662 status = zynqmp_dp_bridge_detect(&dp->bridge); 1663 drm_bridge_hpd_notify(&dp->bridge, status); 1664 } 1665 1666 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data) 1667 { 1668 struct zynqmp_dp *dp = (struct zynqmp_dp *)data; 1669 u32 status, mask; 1670 1671 status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS); 1672 /* clear status register as soon as we read it */ 1673 zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); 1674 mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); 1675 1676 /* 1677 * Status register may report some events, which corresponding interrupts 1678 * have been disabled. Filter out those events against interrupts' mask. 1679 */ 1680 status &= ~mask; 1681 1682 if (!status) 1683 return IRQ_NONE; 1684 1685 /* dbg for diagnostic, but not much that the driver can do */ 1686 if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK) 1687 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n"); 1688 if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) 1689 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); 1690 1691 if (status & ZYNQMP_DP_INT_VBLANK_START) 1692 zynqmp_dpsub_drm_handle_vblank(dp->dpsub); 1693 1694 if (status & ZYNQMP_DP_INT_HPD_EVENT) 1695 schedule_delayed_work(&dp->hpd_work, 0); 1696 1697 if (status & ZYNQMP_DP_INT_HPD_IRQ) { 1698 int ret; 1699 u8 status[DP_LINK_STATUS_SIZE + 2]; 1700 1701 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status, 1702 DP_LINK_STATUS_SIZE + 2); 1703 if (ret < 0) 1704 goto handled; 1705 1706 if (status[4] & DP_LINK_STATUS_UPDATED || 1707 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) || 1708 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) { 1709 zynqmp_dp_train_loop(dp); 1710 } 1711 } 1712 1713 handled: 1714 return IRQ_HANDLED; 1715 } 1716 1717 /* ----------------------------------------------------------------------------- 1718 * Initialization & Cleanup 1719 */ 1720 1721 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub) 1722 { 1723 struct platform_device *pdev = to_platform_device(dpsub->dev); 1724 struct drm_bridge *bridge; 1725 struct zynqmp_dp *dp; 1726 struct resource *res; 1727 int ret; 1728 1729 dp = kzalloc(sizeof(*dp), GFP_KERNEL); 1730 if (!dp) 1731 return -ENOMEM; 1732 1733 dp->dev = &pdev->dev; 1734 dp->dpsub = dpsub; 1735 dp->status = connector_status_disconnected; 1736 1737 INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func); 1738 1739 /* Acquire all resources (IOMEM, IRQ and PHYs). */ 1740 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp"); 1741 dp->iomem = devm_ioremap_resource(dp->dev, res); 1742 if (IS_ERR(dp->iomem)) { 1743 ret = PTR_ERR(dp->iomem); 1744 goto err_free; 1745 } 1746 1747 dp->irq = platform_get_irq(pdev, 0); 1748 if (dp->irq < 0) { 1749 ret = dp->irq; 1750 goto err_free; 1751 } 1752 1753 dp->reset = devm_reset_control_get(dp->dev, NULL); 1754 if (IS_ERR(dp->reset)) { 1755 if (PTR_ERR(dp->reset) != -EPROBE_DEFER) 1756 dev_err(dp->dev, "failed to get reset: %ld\n", 1757 PTR_ERR(dp->reset)); 1758 ret = PTR_ERR(dp->reset); 1759 goto err_free; 1760 } 1761 1762 ret = zynqmp_dp_reset(dp, true); 1763 if (ret < 0) 1764 goto err_free; 1765 1766 ret = zynqmp_dp_reset(dp, false); 1767 if (ret < 0) 1768 goto err_free; 1769 1770 ret = zynqmp_dp_phy_probe(dp); 1771 if (ret) 1772 goto err_reset; 1773 1774 /* Initialize the bridge. */ 1775 bridge = &dp->bridge; 1776 bridge->funcs = &zynqmp_dp_bridge_funcs; 1777 bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 1778 | DRM_BRIDGE_OP_HPD; 1779 bridge->type = DRM_MODE_CONNECTOR_DisplayPort; 1780 bridge->of_node = dp->dev->of_node; 1781 dpsub->bridge = bridge; 1782 1783 /* 1784 * Acquire the next bridge in the chain. Ignore errors caused by port@5 1785 * not being connected for backward-compatibility with older DTs. 1786 */ 1787 ret = drm_of_find_panel_or_bridge(dp->dev->of_node, 5, 0, NULL, 1788 &dp->next_bridge); 1789 if (ret < 0 && ret != -ENODEV) 1790 goto err_reset; 1791 1792 /* Initialize the hardware. */ 1793 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK; 1794 zynqmp_dp_set_format(dp, NULL, ZYNQMP_DPSUB_FORMAT_RGB, 8); 1795 1796 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 1797 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL); 1798 zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); 1799 zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1); 1800 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); 1801 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); 1802 1803 ret = zynqmp_dp_phy_init(dp); 1804 if (ret) 1805 goto err_reset; 1806 1807 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1); 1808 1809 /* 1810 * Now that the hardware is initialized and won't generate spurious 1811 * interrupts, request the IRQ. 1812 */ 1813 ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL, 1814 zynqmp_dp_irq_handler, IRQF_ONESHOT, 1815 dev_name(dp->dev), dp); 1816 if (ret < 0) 1817 goto err_phy_exit; 1818 1819 dpsub->dp = dp; 1820 1821 dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n", 1822 dp->num_lanes); 1823 1824 return 0; 1825 1826 err_phy_exit: 1827 zynqmp_dp_phy_exit(dp); 1828 err_reset: 1829 zynqmp_dp_reset(dp, true); 1830 err_free: 1831 kfree(dp); 1832 return ret; 1833 } 1834 1835 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub) 1836 { 1837 struct zynqmp_dp *dp = dpsub->dp; 1838 1839 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL); 1840 disable_irq(dp->irq); 1841 1842 cancel_delayed_work_sync(&dp->hpd_work); 1843 1844 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); 1845 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); 1846 1847 zynqmp_dp_phy_exit(dp); 1848 zynqmp_dp_reset(dp, true); 1849 } 1850