1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP Display Controller Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/drm_fb_dma_helper.h> 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_framebuffer.h> 15 #include <drm/drm_plane.h> 16 17 #include <linux/clk.h> 18 #include <linux/dma/xilinx_dpdma.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/dmaengine.h> 21 #include <linux/media-bus-format.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 27 #include "zynqmp_disp.h" 28 #include "zynqmp_disp_regs.h" 29 #include "zynqmp_dp.h" 30 #include "zynqmp_dpsub.h" 31 32 /* 33 * Overview 34 * -------- 35 * 36 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video 37 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer. 38 * 39 * +------------------------------------------------------------+ 40 * +--------+ | +----------------+ +-----------+ | 41 * | DPDMA | --->| | --> | Video | Video +-------------+ | 42 * | 4x vid | | | | | Rendering | -+--> | | | +------+ 43 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 44 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 45 * | | and STC | +-----------+ | | Controller | | +------+ 46 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 47 * | | | | Mixer | --+-> | | | +------+ 48 * Live Audio --->| | --> | | || +-------------+ | 49 * | +----------------+ +-----------+ || | 50 * +---------------------------------------||-------------------+ 51 * vv 52 * Blended Video and 53 * Mixed Audio to PL 54 * 55 * Only non-live input from the DPDMA and output to the DisplayPort Source 56 * Controller are currently supported. Interface with the programmable logic 57 * for live streams is not implemented. 58 * 59 * The display controller code creates planes for the DPDMA video and graphics 60 * layers, and a CRTC for the Video Rendering Pipeline. 61 */ 62 63 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4 64 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6 65 66 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3 67 68 /** 69 * enum zynqmp_dpsub_layer_mode - Layer mode 70 * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode 71 * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode 72 */ 73 enum zynqmp_dpsub_layer_mode { 74 ZYNQMP_DPSUB_LAYER_NONLIVE, 75 ZYNQMP_DPSUB_LAYER_LIVE, 76 }; 77 78 /** 79 * struct zynqmp_disp_format - Display subsystem format information 80 * @drm_fmt: DRM format (4CC) 81 * @bus_fmt: Media bus format 82 * @buf_fmt: AV buffer format 83 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats 84 * @sf: Scaling factors for color components 85 */ 86 struct zynqmp_disp_format { 87 u32 drm_fmt; 88 u32 bus_fmt; 89 u32 buf_fmt; 90 bool swap; 91 const u32 *sf; 92 }; 93 94 /** 95 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer 96 * @chan: DMA channel 97 * @xt: Interleaved DMA descriptor template 98 * @sgl: Data chunk for dma_interleaved_template 99 */ 100 struct zynqmp_disp_layer_dma { 101 struct dma_chan *chan; 102 struct dma_interleaved_template xt; 103 struct data_chunk sgl; 104 }; 105 106 /** 107 * struct zynqmp_disp_layer_info - Static layer information 108 * @formats: Array of supported formats 109 * @num_formats: Number of formats in @formats array 110 * @num_channels: Number of DMA channels 111 */ 112 struct zynqmp_disp_layer_info { 113 const struct zynqmp_disp_format *formats; 114 unsigned int num_formats; 115 unsigned int num_channels; 116 }; 117 118 /** 119 * struct zynqmp_disp_layer - Display layer 120 * @id: Layer ID 121 * @disp: Back pointer to struct zynqmp_disp 122 * @info: Static layer information 123 * @dmas: DMA channels 124 * @disp_fmt: Current format information 125 * @drm_fmt: Current DRM format information 126 * @mode: Current operation mode 127 */ 128 struct zynqmp_disp_layer { 129 enum zynqmp_dpsub_layer_id id; 130 struct zynqmp_disp *disp; 131 const struct zynqmp_disp_layer_info *info; 132 133 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; 134 135 const struct zynqmp_disp_format *disp_fmt; 136 const struct drm_format_info *drm_fmt; 137 enum zynqmp_dpsub_layer_mode mode; 138 }; 139 140 /** 141 * struct zynqmp_disp - Display controller 142 * @dev: Device structure 143 * @dpsub: Display subsystem 144 * @blend.base: Register I/O base address for the blender 145 * @avbuf.base: Register I/O base address for the audio/video buffer manager 146 * @audio.base: Registers I/O base address for the audio mixer 147 * @layers: Layers (planes) 148 */ 149 struct zynqmp_disp { 150 struct device *dev; 151 struct zynqmp_dpsub *dpsub; 152 153 struct { 154 void __iomem *base; 155 } blend; 156 struct { 157 void __iomem *base; 158 } avbuf; 159 struct { 160 void __iomem *base; 161 } audio; 162 163 struct zynqmp_disp_layer layers[ZYNQMP_DPSUB_NUM_LAYERS]; 164 }; 165 166 /* ----------------------------------------------------------------------------- 167 * Audio/Video Buffer Manager 168 */ 169 170 static const u32 scaling_factors_444[] = { 171 ZYNQMP_DISP_AV_BUF_4BIT_SF, 172 ZYNQMP_DISP_AV_BUF_4BIT_SF, 173 ZYNQMP_DISP_AV_BUF_4BIT_SF, 174 }; 175 176 static const u32 scaling_factors_555[] = { 177 ZYNQMP_DISP_AV_BUF_5BIT_SF, 178 ZYNQMP_DISP_AV_BUF_5BIT_SF, 179 ZYNQMP_DISP_AV_BUF_5BIT_SF, 180 }; 181 182 static const u32 scaling_factors_565[] = { 183 ZYNQMP_DISP_AV_BUF_5BIT_SF, 184 ZYNQMP_DISP_AV_BUF_6BIT_SF, 185 ZYNQMP_DISP_AV_BUF_5BIT_SF, 186 }; 187 188 static const u32 scaling_factors_666[] = { 189 ZYNQMP_DISP_AV_BUF_6BIT_SF, 190 ZYNQMP_DISP_AV_BUF_6BIT_SF, 191 ZYNQMP_DISP_AV_BUF_6BIT_SF, 192 }; 193 194 static const u32 scaling_factors_888[] = { 195 ZYNQMP_DISP_AV_BUF_8BIT_SF, 196 ZYNQMP_DISP_AV_BUF_8BIT_SF, 197 ZYNQMP_DISP_AV_BUF_8BIT_SF, 198 }; 199 200 static const u32 scaling_factors_101010[] = { 201 ZYNQMP_DISP_AV_BUF_10BIT_SF, 202 ZYNQMP_DISP_AV_BUF_10BIT_SF, 203 ZYNQMP_DISP_AV_BUF_10BIT_SF, 204 }; 205 206 /* List of video layer formats */ 207 static const struct zynqmp_disp_format avbuf_vid_fmts[] = { 208 { 209 .drm_fmt = DRM_FORMAT_VYUY, 210 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 211 .swap = true, 212 .sf = scaling_factors_888, 213 }, { 214 .drm_fmt = DRM_FORMAT_UYVY, 215 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 216 .swap = false, 217 .sf = scaling_factors_888, 218 }, { 219 .drm_fmt = DRM_FORMAT_YUYV, 220 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 221 .swap = false, 222 .sf = scaling_factors_888, 223 }, { 224 .drm_fmt = DRM_FORMAT_YVYU, 225 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 226 .swap = true, 227 .sf = scaling_factors_888, 228 }, { 229 .drm_fmt = DRM_FORMAT_YUV422, 230 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 231 .swap = false, 232 .sf = scaling_factors_888, 233 }, { 234 .drm_fmt = DRM_FORMAT_YVU422, 235 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 236 .swap = true, 237 .sf = scaling_factors_888, 238 }, { 239 .drm_fmt = DRM_FORMAT_YUV444, 240 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 241 .swap = false, 242 .sf = scaling_factors_888, 243 }, { 244 .drm_fmt = DRM_FORMAT_YVU444, 245 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 246 .swap = true, 247 .sf = scaling_factors_888, 248 }, { 249 .drm_fmt = DRM_FORMAT_NV16, 250 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 251 .swap = false, 252 .sf = scaling_factors_888, 253 }, { 254 .drm_fmt = DRM_FORMAT_NV61, 255 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 256 .swap = true, 257 .sf = scaling_factors_888, 258 }, { 259 .drm_fmt = DRM_FORMAT_BGR888, 260 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 261 .swap = false, 262 .sf = scaling_factors_888, 263 }, { 264 .drm_fmt = DRM_FORMAT_RGB888, 265 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 266 .swap = true, 267 .sf = scaling_factors_888, 268 }, { 269 .drm_fmt = DRM_FORMAT_XBGR8888, 270 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 271 .swap = false, 272 .sf = scaling_factors_888, 273 }, { 274 .drm_fmt = DRM_FORMAT_XRGB8888, 275 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 276 .swap = true, 277 .sf = scaling_factors_888, 278 }, { 279 .drm_fmt = DRM_FORMAT_XBGR2101010, 280 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 281 .swap = false, 282 .sf = scaling_factors_101010, 283 }, { 284 .drm_fmt = DRM_FORMAT_XRGB2101010, 285 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 286 .swap = true, 287 .sf = scaling_factors_101010, 288 }, { 289 .drm_fmt = DRM_FORMAT_YUV420, 290 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 291 .swap = false, 292 .sf = scaling_factors_888, 293 }, { 294 .drm_fmt = DRM_FORMAT_YVU420, 295 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 296 .swap = true, 297 .sf = scaling_factors_888, 298 }, { 299 .drm_fmt = DRM_FORMAT_NV12, 300 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 301 .swap = false, 302 .sf = scaling_factors_888, 303 }, { 304 .drm_fmt = DRM_FORMAT_NV21, 305 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 306 .swap = true, 307 .sf = scaling_factors_888, 308 }, 309 }; 310 311 /* List of graphics layer formats */ 312 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { 313 { 314 .drm_fmt = DRM_FORMAT_ABGR8888, 315 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 316 .swap = false, 317 .sf = scaling_factors_888, 318 }, { 319 .drm_fmt = DRM_FORMAT_ARGB8888, 320 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 321 .swap = true, 322 .sf = scaling_factors_888, 323 }, { 324 .drm_fmt = DRM_FORMAT_RGBA8888, 325 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 326 .swap = false, 327 .sf = scaling_factors_888, 328 }, { 329 .drm_fmt = DRM_FORMAT_BGRA8888, 330 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 331 .swap = true, 332 .sf = scaling_factors_888, 333 }, { 334 .drm_fmt = DRM_FORMAT_BGR888, 335 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888, 336 .swap = false, 337 .sf = scaling_factors_888, 338 }, { 339 .drm_fmt = DRM_FORMAT_RGB888, 340 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888, 341 .swap = false, 342 .sf = scaling_factors_888, 343 }, { 344 .drm_fmt = DRM_FORMAT_RGBA5551, 345 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 346 .swap = false, 347 .sf = scaling_factors_555, 348 }, { 349 .drm_fmt = DRM_FORMAT_BGRA5551, 350 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 351 .swap = true, 352 .sf = scaling_factors_555, 353 }, { 354 .drm_fmt = DRM_FORMAT_RGBA4444, 355 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 356 .swap = false, 357 .sf = scaling_factors_444, 358 }, { 359 .drm_fmt = DRM_FORMAT_BGRA4444, 360 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 361 .swap = true, 362 .sf = scaling_factors_444, 363 }, { 364 .drm_fmt = DRM_FORMAT_RGB565, 365 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 366 .swap = false, 367 .sf = scaling_factors_565, 368 }, { 369 .drm_fmt = DRM_FORMAT_BGR565, 370 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 371 .swap = true, 372 .sf = scaling_factors_565, 373 }, 374 }; 375 376 /* List of live video layer formats */ 377 static const struct zynqmp_disp_format avbuf_live_fmts[] = { 378 { 379 .drm_fmt = DRM_FORMAT_RGB565, 380 .bus_fmt = MEDIA_BUS_FMT_RGB666_1X18, 381 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 | 382 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB, 383 .sf = scaling_factors_666, 384 }, { 385 .drm_fmt = DRM_FORMAT_RGB888, 386 .bus_fmt = MEDIA_BUS_FMT_RGB888_1X24, 387 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | 388 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB, 389 .sf = scaling_factors_888, 390 }, { 391 .drm_fmt = DRM_FORMAT_YUV422, 392 .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X16, 393 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | 394 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422, 395 .sf = scaling_factors_888, 396 }, { 397 .drm_fmt = DRM_FORMAT_YUV444, 398 .bus_fmt = MEDIA_BUS_FMT_VUY8_1X24, 399 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | 400 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444, 401 .sf = scaling_factors_888, 402 }, { 403 .drm_fmt = DRM_FORMAT_P210, 404 .bus_fmt = MEDIA_BUS_FMT_UYVY10_1X20, 405 .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 | 406 ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422, 407 .sf = scaling_factors_101010, 408 }, 409 }; 410 411 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg) 412 { 413 return readl(disp->avbuf.base + reg); 414 } 415 416 static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val) 417 { 418 writel(val, disp->avbuf.base + reg); 419 } 420 421 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) 422 { 423 return layer->id == ZYNQMP_DPSUB_LAYER_VID; 424 } 425 426 /** 427 * zynqmp_disp_avbuf_set_format - Set the input format for a layer 428 * @disp: Display controller 429 * @layer: The layer 430 * @fmt: The format information 431 * 432 * Set the video buffer manager format for @layer to @fmt. 433 */ 434 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp, 435 struct zynqmp_disp_layer *layer, 436 const struct zynqmp_disp_format *fmt) 437 { 438 unsigned int i; 439 u32 val, reg; 440 441 layer->disp_fmt = fmt; 442 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { 443 reg = ZYNQMP_DISP_AV_BUF_FMT; 444 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT); 445 val &= zynqmp_disp_layer_is_video(layer) 446 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK 447 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; 448 val |= fmt->buf_fmt; 449 zynqmp_disp_avbuf_write(disp, reg, val); 450 } else { 451 reg = zynqmp_disp_layer_is_video(layer) 452 ? ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG 453 : ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG; 454 val = fmt->buf_fmt; 455 zynqmp_disp_avbuf_write(disp, reg, val); 456 } 457 458 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { 459 reg = zynqmp_disp_layer_is_video(layer) 460 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) 461 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); 462 463 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]); 464 } 465 } 466 467 /** 468 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources 469 * @disp: Display controller 470 * @video_from_ps: True if the video clock originates from the PS 471 * @audio_from_ps: True if the audio clock originates from the PS 472 * @timings_internal: True if video timings are generated internally 473 * 474 * Set the source for the video and audio clocks, as well as for the video 475 * timings. Clocks can originate from the PS or PL, and timings can be 476 * generated internally or externally. 477 */ 478 static void 479 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp, 480 bool video_from_ps, bool audio_from_ps, 481 bool timings_internal) 482 { 483 u32 val = 0; 484 485 if (video_from_ps) 486 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS; 487 if (audio_from_ps) 488 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS; 489 if (timings_internal) 490 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING; 491 492 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val); 493 } 494 495 /** 496 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels 497 * @disp: Display controller 498 * 499 * Enable all (video and audio) buffer channels. 500 */ 501 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp) 502 { 503 unsigned int i; 504 u32 val; 505 506 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 507 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX << 508 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 509 510 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++) 511 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 512 val); 513 514 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 515 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX << 516 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 517 518 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 519 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 520 val); 521 } 522 523 /** 524 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels 525 * @disp: Display controller 526 * 527 * Disable all (video and audio) buffer channels. 528 */ 529 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp) 530 { 531 unsigned int i; 532 533 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 534 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 535 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH); 536 } 537 538 /** 539 * zynqmp_disp_avbuf_enable_audio - Enable audio 540 * @disp: Display controller 541 * 542 * Enable all audio buffers with a non-live (memory) source. 543 */ 544 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp) 545 { 546 u32 val; 547 548 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 549 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 550 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM; 551 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 552 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 553 } 554 555 /** 556 * zynqmp_disp_avbuf_disable_audio - Disable audio 557 * @disp: Display controller 558 * 559 * Disable all audio buffers. 560 */ 561 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp) 562 { 563 u32 val; 564 565 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 566 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 567 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE; 568 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 569 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 570 } 571 572 /** 573 * zynqmp_disp_avbuf_enable_video - Enable a video layer 574 * @disp: Display controller 575 * @layer: The layer 576 * 577 * Enable the video/graphics buffer for @layer. 578 */ 579 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp, 580 struct zynqmp_disp_layer *layer) 581 { 582 u32 val; 583 584 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 585 if (zynqmp_disp_layer_is_video(layer)) { 586 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 587 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) 588 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; 589 else 590 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE; 591 } else { 592 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 593 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 594 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) 595 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 596 else 597 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE; 598 } 599 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 600 } 601 602 /** 603 * zynqmp_disp_avbuf_disable_video - Disable a video layer 604 * @disp: Display controller 605 * @layer: The layer 606 * 607 * Disable the video/graphics buffer for @layer. 608 */ 609 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp, 610 struct zynqmp_disp_layer *layer) 611 { 612 u32 val; 613 614 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 615 if (zynqmp_disp_layer_is_video(layer)) { 616 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 617 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; 618 } else { 619 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 620 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE; 621 } 622 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 623 } 624 625 /** 626 * zynqmp_disp_avbuf_enable - Enable the video pipe 627 * @disp: Display controller 628 * 629 * De-assert the video pipe reset. 630 */ 631 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp) 632 { 633 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0); 634 } 635 636 /** 637 * zynqmp_disp_avbuf_disable - Disable the video pipe 638 * @disp: Display controller 639 * 640 * Assert the video pipe reset. 641 */ 642 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp) 643 { 644 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 645 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST); 646 } 647 648 /* ----------------------------------------------------------------------------- 649 * Blender (Video Pipeline) 650 */ 651 652 static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val) 653 { 654 writel(val, disp->blend.base + reg); 655 } 656 657 /* 658 * Colorspace conversion matrices. 659 * 660 * Hardcode RGB <-> YUV conversion to full-range SDTV for now. 661 */ 662 static const u16 csc_zero_matrix[] = { 663 0x0, 0x0, 0x0, 664 0x0, 0x0, 0x0, 665 0x0, 0x0, 0x0 666 }; 667 668 static const u16 csc_identity_matrix[] = { 669 0x1000, 0x0, 0x0, 670 0x0, 0x1000, 0x0, 671 0x0, 0x0, 0x1000 672 }; 673 674 static const u32 csc_zero_offsets[] = { 675 0, 0, 0 676 }; 677 678 static const u16 csc_rgb_to_sdtv_matrix[] = { 679 0x4c9, 0x864, 0x1d3, 680 0x7d4d, 0x7ab3, 0x800, 681 0x800, 0x794d, 0x7eb3 682 }; 683 684 static const u32 csc_rgb_to_sdtv_offsets[] = { 685 0x0, 0x8000000, 0x8000000 686 }; 687 688 static const u16 csc_sdtv_to_rgb_matrix[] = { 689 0x1000, 0x166f, 0x0, 690 0x1000, 0x7483, 0x7a7f, 691 0x1000, 0x0, 0x1c5a 692 }; 693 694 static const u32 csc_sdtv_to_rgb_offsets[] = { 695 0x0, 0x1800, 0x1800 696 }; 697 698 /** 699 * zynqmp_disp_blend_set_output_format - Set the output format of the blender 700 * @disp: Display controller 701 * @format: Output format 702 * 703 * Set the output format of the blender to @format. 704 */ 705 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp, 706 enum zynqmp_dpsub_format format) 707 { 708 static const unsigned int blend_output_fmts[] = { 709 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB, 710 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444, 711 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 712 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE, 713 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY, 714 }; 715 716 u32 fmt = blend_output_fmts[format]; 717 const u16 *coeffs; 718 const u32 *offsets; 719 unsigned int i; 720 721 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt); 722 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) { 723 coeffs = csc_identity_matrix; 724 offsets = csc_zero_offsets; 725 } else { 726 coeffs = csc_rgb_to_sdtv_matrix; 727 offsets = csc_rgb_to_sdtv_offsets; 728 } 729 730 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++) 731 zynqmp_disp_blend_write(disp, 732 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i), 733 coeffs[i]); 734 735 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 736 zynqmp_disp_blend_write(disp, 737 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i), 738 offsets[i]); 739 } 740 741 /** 742 * zynqmp_disp_blend_set_bg_color - Set the background color 743 * @disp: Display controller 744 * @rcr: Red/Cr color component 745 * @gy: Green/Y color component 746 * @bcb: Blue/Cb color component 747 * 748 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and 749 * B or Cr, Y and Cb components respectively depending on the selected output 750 * format. 751 */ 752 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp, 753 u32 rcr, u32 gy, u32 bcb) 754 { 755 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr); 756 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy); 757 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb); 758 } 759 760 /** 761 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending 762 * @disp: Display controller 763 * @enable: True to enable global alpha blending 764 * @alpha: Global alpha value (ignored if @enabled is false) 765 */ 766 void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, 767 bool enable, u32 alpha) 768 { 769 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, 770 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) | 771 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0)); 772 } 773 774 /** 775 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer 776 * @disp: Display controller 777 * @layer: The layer 778 * @coeffs: Colorspace conversion matrix 779 * @offsets: Colorspace conversion offsets 780 * 781 * Configure the input colorspace conversion matrix and offsets for the @layer. 782 * Columns of the matrix are automatically swapped based on the input format to 783 * handle RGB and YCrCb components permutations. 784 */ 785 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp, 786 struct zynqmp_disp_layer *layer, 787 const u16 *coeffs, 788 const u32 *offsets) 789 { 790 unsigned int swap[3] = { 0, 1, 2 }; 791 unsigned int reg; 792 unsigned int i; 793 794 if (layer->disp_fmt->swap) { 795 if (layer->drm_fmt->is_yuv) { 796 /* Swap U and V. */ 797 swap[1] = 2; 798 swap[2] = 1; 799 } else { 800 /* Swap R and B. */ 801 swap[0] = 2; 802 swap[2] = 0; 803 } 804 } 805 806 if (zynqmp_disp_layer_is_video(layer)) 807 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0); 808 else 809 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0); 810 811 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) { 812 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]); 813 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]); 814 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]); 815 } 816 817 if (zynqmp_disp_layer_is_video(layer)) 818 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0); 819 else 820 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0); 821 822 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 823 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]); 824 } 825 826 /** 827 * zynqmp_disp_blend_layer_enable - Enable a layer 828 * @disp: Display controller 829 * @layer: The layer 830 */ 831 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp, 832 struct zynqmp_disp_layer *layer) 833 { 834 const u16 *coeffs; 835 const u32 *offsets; 836 u32 val; 837 838 val = (layer->drm_fmt->is_yuv ? 839 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) | 840 (layer->drm_fmt->hsub > 1 ? 841 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0); 842 843 zynqmp_disp_blend_write(disp, 844 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 845 val); 846 847 if (layer->drm_fmt->is_yuv) { 848 coeffs = csc_sdtv_to_rgb_matrix; 849 offsets = csc_sdtv_to_rgb_offsets; 850 } else { 851 coeffs = csc_identity_matrix; 852 offsets = csc_zero_offsets; 853 } 854 855 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets); 856 } 857 858 /** 859 * zynqmp_disp_blend_layer_disable - Disable a layer 860 * @disp: Display controller 861 * @layer: The layer 862 */ 863 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp, 864 struct zynqmp_disp_layer *layer) 865 { 866 zynqmp_disp_blend_write(disp, 867 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 868 0); 869 870 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix, 871 csc_zero_offsets); 872 } 873 874 /* ----------------------------------------------------------------------------- 875 * Audio Mixer 876 */ 877 878 static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val) 879 { 880 writel(val, disp->audio.base + reg); 881 } 882 883 /** 884 * zynqmp_disp_audio_enable - Enable the audio mixer 885 * @disp: Display controller 886 * 887 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to 888 * default values by the reset, set the default mixer volume explicitly. 889 */ 890 static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp) 891 { 892 /* Clear the audio soft reset register as it's an non-reset flop. */ 893 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0); 894 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME, 895 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE); 896 } 897 898 /** 899 * zynqmp_disp_audio_disable - Disable the audio mixer 900 * @disp: Display controller 901 * 902 * Disable the audio mixer by asserting its soft reset. 903 */ 904 static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp) 905 { 906 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 907 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST); 908 } 909 910 /* ----------------------------------------------------------------------------- 911 * ZynqMP Display Layer & DRM Plane 912 */ 913 914 /** 915 * zynqmp_disp_layer_find_format - Find format information for a DRM format 916 * @layer: The layer 917 * @drm_fmt: DRM format to search 918 * 919 * Search display subsystem format information corresponding to the given DRM 920 * format @drm_fmt for the @layer, and return a pointer to the format 921 * descriptor. 922 * 923 * Return: A pointer to the format descriptor if found, NULL otherwise 924 */ 925 static const struct zynqmp_disp_format * 926 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, 927 u32 drm_fmt) 928 { 929 unsigned int i; 930 931 for (i = 0; i < layer->info->num_formats; i++) { 932 if (layer->info->formats[i].drm_fmt == drm_fmt) 933 return &layer->info->formats[i]; 934 } 935 936 return NULL; 937 } 938 939 /** 940 * zynqmp_disp_layer_find_live_format - Find format information for given 941 * media bus format 942 * @layer: The layer 943 * @media_bus_format: Media bus format to search 944 * 945 * Search display subsystem format information corresponding to the given media 946 * bus format @media_bus_format for the @layer, and return a pointer to the 947 * format descriptor. 948 * 949 * Return: A pointer to the format descriptor if found, NULL otherwise 950 */ 951 static const struct zynqmp_disp_format * 952 zynqmp_disp_layer_find_live_format(struct zynqmp_disp_layer *layer, 953 u32 media_bus_format) 954 { 955 unsigned int i; 956 957 for (i = 0; i < layer->info->num_formats; i++) 958 if (layer->info->formats[i].bus_fmt == media_bus_format) 959 return &layer->info->formats[i]; 960 961 return NULL; 962 } 963 964 /** 965 * zynqmp_disp_layer_drm_formats - Return the DRM formats supported by the layer 966 * @layer: The layer 967 * @num_formats: Pointer to the returned number of formats 968 * 969 * NOTE: This function doesn't make sense for live video layers and will 970 * always return an empty list in such cases. zynqmp_disp_live_layer_formats() 971 * should be used to query a list of media bus formats supported by the live 972 * video input layer. 973 * 974 * Return: A newly allocated u32 array that stores all the DRM formats 975 * supported by the layer. The number of formats in the array is returned 976 * through the num_formats argument. 977 */ 978 u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, 979 unsigned int *num_formats) 980 { 981 unsigned int i; 982 u32 *formats; 983 984 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_NONLIVE)) { 985 *num_formats = 0; 986 return NULL; 987 } 988 989 formats = kcalloc(layer->info->num_formats, sizeof(*formats), 990 GFP_KERNEL); 991 if (!formats) { 992 *num_formats = 0; 993 return NULL; 994 } 995 996 for (i = 0; i < layer->info->num_formats; ++i) 997 formats[i] = layer->info->formats[i].drm_fmt; 998 999 *num_formats = layer->info->num_formats; 1000 return formats; 1001 } 1002 1003 /** 1004 * zynqmp_disp_live_layer_formats - Return the media bus formats supported by 1005 * the live video layer 1006 * @layer: The layer 1007 * @num_formats: Pointer to the returned number of formats 1008 * 1009 * NOTE: This function should be used only for live video input layers. 1010 * 1011 * Return: A newly allocated u32 array of media bus formats supported by the 1012 * layer. The number of formats in the array is returned through the 1013 * @num_formats argument. 1014 */ 1015 u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer, 1016 unsigned int *num_formats) 1017 { 1018 unsigned int i; 1019 u32 *formats; 1020 1021 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_LIVE)) { 1022 *num_formats = 0; 1023 return NULL; 1024 } 1025 1026 formats = kcalloc(layer->info->num_formats, sizeof(*formats), 1027 GFP_KERNEL); 1028 if (!formats) { 1029 *num_formats = 0; 1030 return NULL; 1031 } 1032 1033 for (i = 0; i < layer->info->num_formats; ++i) 1034 formats[i] = layer->info->formats[i].bus_fmt; 1035 1036 *num_formats = layer->info->num_formats; 1037 return formats; 1038 } 1039 1040 /** 1041 * zynqmp_disp_layer_enable - Enable a layer 1042 * @layer: The layer 1043 * 1044 * Enable the @layer in the audio/video buffer manager and the blender. DMA 1045 * channels are started separately by zynqmp_disp_layer_update(). 1046 */ 1047 void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) 1048 { 1049 zynqmp_disp_avbuf_enable_video(layer->disp, layer); 1050 zynqmp_disp_blend_layer_enable(layer->disp, layer); 1051 } 1052 1053 /** 1054 * zynqmp_disp_layer_disable - Disable the layer 1055 * @layer: The layer 1056 * 1057 * Disable the layer by stopping its DMA channels and disabling it in the 1058 * audio/video buffer manager and the blender. 1059 */ 1060 void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) 1061 { 1062 unsigned int i; 1063 1064 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { 1065 for (i = 0; i < layer->drm_fmt->num_planes; i++) 1066 dmaengine_terminate_sync(layer->dmas[i].chan); 1067 } 1068 1069 zynqmp_disp_avbuf_disable_video(layer->disp, layer); 1070 zynqmp_disp_blend_layer_disable(layer->disp, layer); 1071 } 1072 1073 /** 1074 * zynqmp_disp_layer_set_format - Set the layer format 1075 * @layer: The layer 1076 * @info: The format info 1077 * 1078 * NOTE: Use zynqmp_disp_layer_set_live_format() to set media bus format for 1079 * live video layers. 1080 * 1081 * Set the format for @layer to @info. The layer must be disabled. 1082 */ 1083 void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, 1084 const struct drm_format_info *info) 1085 { 1086 unsigned int i; 1087 1088 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_NONLIVE)) 1089 return; 1090 1091 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); 1092 if (WARN_ON(!layer->disp_fmt)) 1093 return; 1094 layer->drm_fmt = info; 1095 1096 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); 1097 1098 /* 1099 * Set pconfig for each DMA channel to indicate they're part of a 1100 * video group. 1101 */ 1102 for (i = 0; i < info->num_planes; i++) { 1103 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1104 struct xilinx_dpdma_peripheral_config pconfig = { 1105 .video_group = true, 1106 }; 1107 struct dma_slave_config config = { 1108 .direction = DMA_MEM_TO_DEV, 1109 .peripheral_config = &pconfig, 1110 .peripheral_size = sizeof(pconfig), 1111 }; 1112 1113 dmaengine_slave_config(dma->chan, &config); 1114 } 1115 } 1116 1117 /** 1118 * zynqmp_disp_layer_set_live_format - Set the live video layer format 1119 * @layer: The layer 1120 * @media_bus_format: Media bus format to set 1121 * 1122 * NOTE: This function should not be used to set format for non-live video 1123 * layer. Use zynqmp_disp_layer_set_format() instead. 1124 * 1125 * Set the display format for the live @layer. The layer must be disabled. 1126 */ 1127 void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer, 1128 u32 media_bus_format) 1129 { 1130 if (WARN_ON(layer->mode != ZYNQMP_DPSUB_LAYER_LIVE)) 1131 return; 1132 1133 layer->disp_fmt = zynqmp_disp_layer_find_live_format(layer, 1134 media_bus_format); 1135 if (WARN_ON(!layer->disp_fmt)) 1136 return; 1137 1138 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); 1139 1140 layer->drm_fmt = drm_format_info(layer->disp_fmt->drm_fmt); 1141 } 1142 1143 /** 1144 * zynqmp_disp_layer_update - Update the layer framebuffer 1145 * @layer: The layer 1146 * @state: The plane state 1147 * 1148 * Update the framebuffer for the layer by issuing a new DMA engine transaction 1149 * for the new framebuffer. 1150 * 1151 * Return: 0 on success, or the DMA descriptor failure error otherwise 1152 */ 1153 int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, 1154 struct drm_plane_state *state) 1155 { 1156 const struct drm_format_info *info = layer->drm_fmt; 1157 unsigned int i; 1158 1159 if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) 1160 return 0; 1161 1162 for (i = 0; i < info->num_planes; i++) { 1163 unsigned int width = state->crtc_w / (i ? info->hsub : 1); 1164 unsigned int height = state->crtc_h / (i ? info->vsub : 1); 1165 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1166 struct dma_async_tx_descriptor *desc; 1167 dma_addr_t dma_addr; 1168 1169 dma_addr = drm_fb_dma_get_gem_addr(state->fb, state, i); 1170 1171 dma->xt.numf = height; 1172 dma->sgl.size = width * info->cpp[i]; 1173 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size; 1174 dma->xt.src_start = dma_addr; 1175 dma->xt.frame_size = 1; 1176 dma->xt.dir = DMA_MEM_TO_DEV; 1177 dma->xt.src_sgl = true; 1178 dma->xt.dst_sgl = false; 1179 1180 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt, 1181 DMA_CTRL_ACK | 1182 DMA_PREP_REPEAT | 1183 DMA_PREP_LOAD_EOT); 1184 if (!desc) { 1185 dev_err(layer->disp->dev, 1186 "failed to prepare DMA descriptor\n"); 1187 return -ENOMEM; 1188 } 1189 1190 dmaengine_submit(desc); 1191 dma_async_issue_pending(dma->chan); 1192 } 1193 1194 return 0; 1195 } 1196 1197 /** 1198 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer 1199 * @disp: Display controller 1200 * @layer: The layer 1201 * 1202 * Release the DMA channels associated with @layer. 1203 */ 1204 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, 1205 struct zynqmp_disp_layer *layer) 1206 { 1207 unsigned int i; 1208 1209 for (i = 0; i < layer->info->num_channels; i++) { 1210 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1211 1212 if (!dma->chan) 1213 continue; 1214 1215 /* Make sure the channel is terminated before release. */ 1216 dmaengine_terminate_sync(dma->chan); 1217 dma_release_channel(dma->chan); 1218 } 1219 } 1220 1221 /** 1222 * zynqmp_disp_destroy_layers - Destroy all layers 1223 * @disp: Display controller 1224 */ 1225 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp) 1226 { 1227 unsigned int i; 1228 1229 for (i = 0; i < ARRAY_SIZE(disp->layers); i++) 1230 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]); 1231 } 1232 1233 /** 1234 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer 1235 * @disp: Display controller 1236 * @layer: The layer 1237 * 1238 * Request all DMA engine channels needed by @layer. 1239 * 1240 * Return: 0 on success, or the DMA channel request error otherwise 1241 */ 1242 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, 1243 struct zynqmp_disp_layer *layer) 1244 { 1245 static const char * const dma_names[] = { "vid", "gfx" }; 1246 unsigned int i; 1247 int ret; 1248 1249 for (i = 0; i < layer->info->num_channels; i++) { 1250 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1251 char dma_channel_name[16]; 1252 1253 snprintf(dma_channel_name, sizeof(dma_channel_name), 1254 "%s%u", dma_names[layer->id], i); 1255 dma->chan = dma_request_chan(disp->dev, dma_channel_name); 1256 if (IS_ERR(dma->chan)) { 1257 ret = dev_err_probe(disp->dev, PTR_ERR(dma->chan), 1258 "failed to request dma channel\n"); 1259 dma->chan = NULL; 1260 return ret; 1261 } 1262 } 1263 1264 return 0; 1265 } 1266 1267 /** 1268 * zynqmp_disp_create_layers - Create and initialize all layers 1269 * @disp: Display controller 1270 * 1271 * Return: 0 on success, or the DMA channel request error otherwise 1272 */ 1273 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) 1274 { 1275 static const struct zynqmp_disp_layer_info layer_info[] = { 1276 [ZYNQMP_DPSUB_LAYER_VID] = { 1277 .formats = avbuf_vid_fmts, 1278 .num_formats = ARRAY_SIZE(avbuf_vid_fmts), 1279 .num_channels = 3, 1280 }, 1281 [ZYNQMP_DPSUB_LAYER_GFX] = { 1282 .formats = avbuf_gfx_fmts, 1283 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts), 1284 .num_channels = 1, 1285 }, 1286 }; 1287 static const struct zynqmp_disp_layer_info live_layer_info = { 1288 .formats = avbuf_live_fmts, 1289 .num_formats = ARRAY_SIZE(avbuf_live_fmts), 1290 .num_channels = 0, 1291 }; 1292 1293 unsigned int i; 1294 int ret; 1295 1296 for (i = 0; i < ARRAY_SIZE(disp->layers); i++) { 1297 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1298 1299 layer->id = i; 1300 layer->disp = disp; 1301 /* 1302 * For now assume dpsub works in either live or non-live mode for both layers. 1303 * Hybrid mode is not supported yet. 1304 */ 1305 if (disp->dpsub->dma_enabled) { 1306 layer->mode = ZYNQMP_DPSUB_LAYER_NONLIVE; 1307 layer->info = &layer_info[i]; 1308 } else { 1309 layer->mode = ZYNQMP_DPSUB_LAYER_LIVE; 1310 layer->info = &live_layer_info; 1311 } 1312 1313 ret = zynqmp_disp_layer_request_dma(disp, layer); 1314 if (ret) 1315 goto err; 1316 1317 disp->dpsub->layers[i] = layer; 1318 } 1319 1320 return 0; 1321 1322 err: 1323 zynqmp_disp_destroy_layers(disp); 1324 return ret; 1325 } 1326 1327 /* ----------------------------------------------------------------------------- 1328 * ZynqMP Display 1329 */ 1330 1331 /** 1332 * zynqmp_disp_enable - Enable the display controller 1333 * @disp: Display controller 1334 */ 1335 void zynqmp_disp_enable(struct zynqmp_disp *disp) 1336 { 1337 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB); 1338 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0); 1339 1340 zynqmp_disp_avbuf_enable(disp); 1341 /* Choose clock source based on the DT clock handle. */ 1342 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->dpsub->vid_clk_from_ps, 1343 disp->dpsub->aud_clk_from_ps, 1344 disp->dpsub->vid_clk_from_ps); 1345 zynqmp_disp_avbuf_enable_channels(disp); 1346 zynqmp_disp_avbuf_enable_audio(disp); 1347 1348 zynqmp_disp_audio_enable(disp); 1349 } 1350 1351 /** 1352 * zynqmp_disp_disable - Disable the display controller 1353 * @disp: Display controller 1354 */ 1355 void zynqmp_disp_disable(struct zynqmp_disp *disp) 1356 { 1357 zynqmp_disp_audio_disable(disp); 1358 1359 zynqmp_disp_avbuf_disable_audio(disp); 1360 zynqmp_disp_avbuf_disable_channels(disp); 1361 zynqmp_disp_avbuf_disable(disp); 1362 } 1363 1364 /** 1365 * zynqmp_disp_setup_clock - Configure the display controller pixel clock rate 1366 * @disp: Display controller 1367 * @mode_clock: The pixel clock rate, in Hz 1368 * 1369 * Return: 0 on success, or a negative error clock otherwise 1370 */ 1371 int zynqmp_disp_setup_clock(struct zynqmp_disp *disp, 1372 unsigned long mode_clock) 1373 { 1374 unsigned long rate; 1375 long diff; 1376 int ret; 1377 1378 ret = clk_set_rate(disp->dpsub->vid_clk, mode_clock); 1379 if (ret) { 1380 dev_err(disp->dev, "failed to set the video clock\n"); 1381 return ret; 1382 } 1383 1384 rate = clk_get_rate(disp->dpsub->vid_clk); 1385 diff = rate - mode_clock; 1386 if (abs(diff) > mode_clock / 20) 1387 dev_info(disp->dev, 1388 "requested pixel rate: %lu actual rate: %lu\n", 1389 mode_clock, rate); 1390 else 1391 dev_dbg(disp->dev, 1392 "requested pixel rate: %lu actual rate: %lu\n", 1393 mode_clock, rate); 1394 1395 return 0; 1396 } 1397 1398 /* ----------------------------------------------------------------------------- 1399 * Initialization & Cleanup 1400 */ 1401 1402 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub) 1403 { 1404 struct platform_device *pdev = to_platform_device(dpsub->dev); 1405 struct zynqmp_disp *disp; 1406 int ret; 1407 1408 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 1409 if (!disp) 1410 return -ENOMEM; 1411 1412 disp->dev = &pdev->dev; 1413 disp->dpsub = dpsub; 1414 1415 disp->blend.base = devm_platform_ioremap_resource_byname(pdev, "blend"); 1416 if (IS_ERR(disp->blend.base)) { 1417 ret = PTR_ERR(disp->blend.base); 1418 goto error; 1419 } 1420 1421 disp->avbuf.base = devm_platform_ioremap_resource_byname(pdev, "av_buf"); 1422 if (IS_ERR(disp->avbuf.base)) { 1423 ret = PTR_ERR(disp->avbuf.base); 1424 goto error; 1425 } 1426 1427 disp->audio.base = devm_platform_ioremap_resource_byname(pdev, "aud"); 1428 if (IS_ERR(disp->audio.base)) { 1429 ret = PTR_ERR(disp->audio.base); 1430 goto error; 1431 } 1432 1433 ret = zynqmp_disp_create_layers(disp); 1434 if (ret) 1435 goto error; 1436 1437 if (disp->dpsub->dma_enabled) { 1438 struct zynqmp_disp_layer *layer; 1439 1440 layer = &disp->layers[ZYNQMP_DPSUB_LAYER_VID]; 1441 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align; 1442 } 1443 1444 dpsub->disp = disp; 1445 1446 return 0; 1447 1448 error: 1449 kfree(disp); 1450 return ret; 1451 } 1452 1453 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub) 1454 { 1455 struct zynqmp_disp *disp = dpsub->disp; 1456 1457 zynqmp_disp_destroy_layers(disp); 1458 } 1459