1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_wa_oob.h> 14 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_regs.h" 18 #include "xe_device_types.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt.h" 21 #include "xe_hw_engine_types.h" 22 #include "xe_mmio.h" 23 #include "xe_platform_types.h" 24 #include "xe_rtp.h" 25 #include "xe_sriov.h" 26 #include "xe_step.h" 27 28 /** 29 * DOC: Hardware workarounds 30 * 31 * Hardware workarounds are register programming documented to be executed in 32 * the driver that fall outside of the normal programming sequences for a 33 * platform. There are some basic categories of workarounds, depending on 34 * how/when they are applied: 35 * 36 * - LRC workarounds: workarounds that touch registers that are 37 * saved/restored to/from the HW context image. The list is emitted (via Load 38 * Register Immediate commands) once when initializing the device and saved in 39 * the default context. That default context is then used on every context 40 * creation to have a "primed golden context", i.e. a context image that 41 * already contains the changes needed to all the registers. 42 * 43 * - Engine workarounds: the list of these WAs is applied whenever the specific 44 * engine is reset. It's also possible that a set of engine classes share a 45 * common power domain and they are reset together. This happens on some 46 * platforms with render and compute engines. In this case (at least) one of 47 * them need to keeep the workaround programming: the approach taken in the 48 * driver is to tie those workarounds to the first compute/render engine that 49 * is registered. When executing with GuC submission, engine resets are 50 * outside of kernel driver control, hence the list of registers involved in 51 * written once, on engine initialization, and then passed to GuC, that 52 * saves/restores their values before/after the reset takes place. See 53 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. 54 * 55 * - GT workarounds: the list of these WAs is applied whenever these registers 56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 57 * 58 * - Register whitelist: some workarounds need to be implemented in userspace, 59 * but need to touch privileged registers. The whitelist in the kernel 60 * instructs the hardware to allow the access to happen. From the kernel side, 61 * this is just a special case of a MMIO workaround (as we write the list of 62 * these to/be-whitelisted registers to some special HW registers). 63 * 64 * - Workaround batchbuffers: buffers that get executed automatically by the 65 * hardware on every HW context restore. These buffers are created and 66 * programmed in the default context so the hardware always go through those 67 * programming sequences when switching contexts. The support for workaround 68 * batchbuffers is enabled these hardware mechanisms: 69 * 70 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 71 * context, pointing the hardware to jump to that location when that offset 72 * is reached in the context restore. Workaround batchbuffer in the driver 73 * currently uses this mechanism for all platforms. 74 * 75 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 76 * pointing the hardware to a buffer to continue executing after the 77 * engine registers are restored in a context restore sequence. This is 78 * currently not used in the driver. 79 * 80 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 81 * a central place. Those are peppered around the rest of the code, as needed. 82 * Workarounds related to the display IP are the main example. 83 * 84 * .. [1] Technically, some registers are powercontext saved & restored, so they 85 * survive a suspend/resume. In practice, writing them again is not too 86 * costly and simplifies things, so it's the approach taken in the driver. 87 * 88 * .. note:: 89 * Hardware workarounds in xe work the same way as in i915, with the 90 * difference of how they are maintained in the code. In xe it uses the 91 * xe_rtp infrastructure so the workarounds can be kept in tables, following 92 * a more declarative approach rather than procedural. 93 */ 94 95 #undef XE_REG_MCR 96 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 97 98 __diag_push(); 99 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 100 101 static const struct xe_rtp_entry_sr gt_was[] = { 102 { XE_RTP_NAME("14011060649"), 103 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 104 ENGINE_CLASS(VIDEO_DECODE), 105 FUNC(xe_rtp_match_even_instance)), 106 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 107 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 108 }, 109 { XE_RTP_NAME("14011059788"), 110 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 111 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 112 }, 113 { XE_RTP_NAME("14015795083"), 114 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 115 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 116 }, 117 118 /* DG1 */ 119 120 { XE_RTP_NAME("1409420604"), 121 XE_RTP_RULES(PLATFORM(DG1)), 122 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 123 }, 124 { XE_RTP_NAME("1408615072"), 125 XE_RTP_RULES(PLATFORM(DG1)), 126 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 127 }, 128 129 /* DG2 */ 130 131 { XE_RTP_NAME("22010523718"), 132 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 133 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 134 }, 135 { XE_RTP_NAME("14011006942"), 136 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 137 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 138 }, 139 { XE_RTP_NAME("14014830051"), 140 XE_RTP_RULES(PLATFORM(DG2)), 141 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 142 }, 143 { XE_RTP_NAME("18018781329"), 144 XE_RTP_RULES(PLATFORM(DG2)), 145 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 146 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 147 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 148 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 149 }, 150 { XE_RTP_NAME("1509235366"), 151 XE_RTP_RULES(PLATFORM(DG2)), 152 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 153 INVALIDATION_BROADCAST_MODE_DIS | 154 GLOBAL_INVALIDATION_MODE)) 155 }, 156 157 /* PVC */ 158 159 { XE_RTP_NAME("18018781329"), 160 XE_RTP_RULES(PLATFORM(PVC)), 161 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 162 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 163 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 164 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 165 }, 166 { XE_RTP_NAME("16016694945"), 167 XE_RTP_RULES(PLATFORM(PVC)), 168 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 169 }, 170 171 /* Xe_LPG */ 172 173 { XE_RTP_NAME("14015795083"), 174 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 175 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 176 }, 177 { XE_RTP_NAME("14018575942"), 178 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 179 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 180 }, 181 { XE_RTP_NAME("22016670082"), 182 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 183 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 184 }, 185 186 /* Xe_LPM+ */ 187 188 { XE_RTP_NAME("16021867713"), 189 XE_RTP_RULES(MEDIA_VERSION(1300), 190 ENGINE_CLASS(VIDEO_DECODE)), 191 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 192 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 193 }, 194 { XE_RTP_NAME("22016670082"), 195 XE_RTP_RULES(MEDIA_VERSION(1300)), 196 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 197 }, 198 199 /* Xe2_LPG */ 200 201 { XE_RTP_NAME("16020975621"), 202 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 203 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 204 }, 205 { XE_RTP_NAME("14018157293"), 206 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 207 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 208 SET(XEHPC_L3CLOS_MASK(1), ~0), 209 SET(XEHPC_L3CLOS_MASK(2), ~0), 210 SET(XEHPC_L3CLOS_MASK(3), ~0)) 211 }, 212 213 /* Xe2_LPM */ 214 215 { XE_RTP_NAME("14017421178"), 216 XE_RTP_RULES(MEDIA_VERSION(2000), 217 ENGINE_CLASS(VIDEO_DECODE)), 218 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 219 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 220 }, 221 { XE_RTP_NAME("16021867713"), 222 XE_RTP_RULES(MEDIA_VERSION(2000), 223 ENGINE_CLASS(VIDEO_DECODE)), 224 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 225 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 226 }, 227 { XE_RTP_NAME("14019449301"), 228 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 229 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 230 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 231 }, 232 233 /* Xe2_HPG */ 234 235 { XE_RTP_NAME("16025250150"), 236 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 237 XE_RTP_ACTIONS(SET(LSN_VC_REG2, 238 LSN_LNI_WGT(1) | 239 LSN_LNE_WGT(1) | 240 LSN_DIM_X_WGT(1) | 241 LSN_DIM_Y_WGT(1) | 242 LSN_DIM_Z_WGT(1))) 243 }, 244 245 /* Xe2_HPM */ 246 247 { XE_RTP_NAME("16021867713"), 248 XE_RTP_RULES(MEDIA_VERSION(1301), 249 ENGINE_CLASS(VIDEO_DECODE)), 250 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 251 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 252 }, 253 { XE_RTP_NAME("14020316580"), 254 XE_RTP_RULES(MEDIA_VERSION(1301)), 255 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE, 256 VDN_HCP_POWERGATE_ENABLE(0) | 257 VDN_MFXVDENC_POWERGATE_ENABLE(0) | 258 VDN_HCP_POWERGATE_ENABLE(2) | 259 VDN_MFXVDENC_POWERGATE_ENABLE(2))), 260 }, 261 { XE_RTP_NAME("14019449301"), 262 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 263 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 264 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 265 }, 266 267 /* Xe3_LPG */ 268 269 { XE_RTP_NAME("14021871409"), 270 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 271 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 272 }, 273 274 /* Xe3_LPM */ 275 276 { XE_RTP_NAME("16021867713"), 277 XE_RTP_RULES(MEDIA_VERSION(3000), 278 ENGINE_CLASS(VIDEO_DECODE)), 279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 281 }, 282 { XE_RTP_NAME("16021865536"), 283 XE_RTP_RULES(MEDIA_VERSION(3000), 284 ENGINE_CLASS(VIDEO_DECODE)), 285 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 286 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 287 }, 288 { XE_RTP_NAME("16021865536"), 289 XE_RTP_RULES(MEDIA_VERSION(3002), 290 ENGINE_CLASS(VIDEO_DECODE)), 291 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 292 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 293 }, 294 { XE_RTP_NAME("16021867713"), 295 XE_RTP_RULES(MEDIA_VERSION(3002), 296 ENGINE_CLASS(VIDEO_DECODE)), 297 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 298 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 299 }, 300 { XE_RTP_NAME("14021486841"), 301 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 302 ENGINE_CLASS(VIDEO_DECODE)), 303 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 304 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 305 }, 306 }; 307 308 static const struct xe_rtp_entry_sr engine_was[] = { 309 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 310 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 311 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 312 FF_TESSELATION_DOP_GATE_DISABLE)) 313 }, 314 { XE_RTP_NAME("1409804808"), 315 XE_RTP_RULES(GRAPHICS_VERSION(1200), 316 ENGINE_CLASS(RENDER), 317 IS_INTEGRATED), 318 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 319 }, 320 { XE_RTP_NAME("14010229206, 1409085225"), 321 XE_RTP_RULES(GRAPHICS_VERSION(1200), 322 ENGINE_CLASS(RENDER), 323 IS_INTEGRATED), 324 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 325 }, 326 { XE_RTP_NAME("1606931601"), 327 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 328 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 329 }, 330 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 331 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 332 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 333 FF_DOP_CLOCK_GATE_DISABLE)) 334 }, 335 { XE_RTP_NAME("1406941453"), 336 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 337 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 338 }, 339 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 340 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 341 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 342 FFSC_PERCTX_PREEMPT_CTRL)) 343 }, 344 345 /* TGL */ 346 347 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 348 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 349 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 350 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 351 RC_SEMA_IDLE_MSG_DISABLE)) 352 }, 353 354 /* RKL */ 355 356 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 357 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 358 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 359 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 360 RC_SEMA_IDLE_MSG_DISABLE)) 361 }, 362 363 /* ADL-P */ 364 365 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 366 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 367 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 368 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 369 RC_SEMA_IDLE_MSG_DISABLE)) 370 }, 371 372 /* DG2 */ 373 374 { XE_RTP_NAME("22013037850"), 375 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 376 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 377 DISABLE_128B_EVICTION_COMMAND_UDW)) 378 }, 379 { XE_RTP_NAME("22014226127"), 380 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 381 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 382 }, 383 { XE_RTP_NAME("18017747507"), 384 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 385 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 386 POLYGON_TRIFAN_LINELOOP_DISABLE)) 387 }, 388 { XE_RTP_NAME("22012826095, 22013059131"), 389 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 390 FUNC(xe_rtp_match_first_render_or_compute)), 391 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 392 MAXREQS_PER_BANK, 393 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 394 }, 395 { XE_RTP_NAME("22013059131"), 396 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 397 FUNC(xe_rtp_match_first_render_or_compute)), 398 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 399 }, 400 { XE_RTP_NAME("14015227452"), 401 XE_RTP_RULES(PLATFORM(DG2), 402 FUNC(xe_rtp_match_first_render_or_compute)), 403 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 404 }, 405 { XE_RTP_NAME("18028616096"), 406 XE_RTP_RULES(PLATFORM(DG2), 407 FUNC(xe_rtp_match_first_render_or_compute)), 408 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 409 }, 410 { XE_RTP_NAME("22015475538"), 411 XE_RTP_RULES(PLATFORM(DG2), 412 FUNC(xe_rtp_match_first_render_or_compute)), 413 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 414 }, 415 { XE_RTP_NAME("22012654132"), 416 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 417 FUNC(xe_rtp_match_first_render_or_compute)), 418 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 419 /* 420 * Register can't be read back for verification on 421 * DG2 due to Wa_14012342262 422 */ 423 .read_mask = 0)) 424 }, 425 { XE_RTP_NAME("1509727124"), 426 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 427 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 428 }, 429 { XE_RTP_NAME("22012856258"), 430 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 431 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 432 }, 433 { XE_RTP_NAME("22010960976, 14013347512"), 434 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 435 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 436 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 437 }, 438 { XE_RTP_NAME("14015150844"), 439 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 440 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 441 XE_RTP_NOCHECK)) 442 }, 443 444 /* PVC */ 445 446 { XE_RTP_NAME("22014226127"), 447 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 448 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 449 }, 450 { XE_RTP_NAME("14015227452"), 451 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 452 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 453 }, 454 { XE_RTP_NAME("18020744125"), 455 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 456 ENGINE_CLASS(COMPUTE)), 457 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 458 }, 459 { XE_RTP_NAME("14014999345"), 460 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 461 GRAPHICS_STEP(B0, C0)), 462 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 463 }, 464 465 /* Xe_LPG */ 466 467 { XE_RTP_NAME("14017856879"), 468 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 469 FUNC(xe_rtp_match_first_render_or_compute)), 470 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 471 }, 472 { XE_RTP_NAME("14015150844"), 473 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 474 FUNC(xe_rtp_match_first_render_or_compute)), 475 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 476 XE_RTP_NOCHECK)) 477 }, 478 { XE_RTP_NAME("14020495402"), 479 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 480 FUNC(xe_rtp_match_first_render_or_compute)), 481 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 482 }, 483 484 /* Xe2_LPG */ 485 486 { XE_RTP_NAME("18032247524"), 487 XE_RTP_RULES(GRAPHICS_VERSION(2004), 488 FUNC(xe_rtp_match_first_render_or_compute)), 489 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 490 }, 491 { XE_RTP_NAME("16018712365"), 492 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 493 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 494 }, 495 { XE_RTP_NAME("14018957109"), 496 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 497 FUNC(xe_rtp_match_first_render_or_compute)), 498 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 499 }, 500 { XE_RTP_NAME("14020338487"), 501 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 502 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 503 }, 504 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 505 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 506 FUNC(xe_rtp_match_first_render_or_compute)), 507 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 508 }, 509 { XE_RTP_NAME("14019322943"), 510 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 511 FUNC(xe_rtp_match_first_render_or_compute)), 512 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 513 }, 514 { XE_RTP_NAME("14018471104"), 515 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 516 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 517 }, 518 /* 519 * These two workarounds are the same, just applying to different 520 * engines. Although Wa_18032095049 (for the RCS) isn't required on 521 * all steppings, disabling these reports has no impact for our 522 * driver or the GuC, so we go ahead and treat it the same as 523 * Wa_16021639441 which does apply to all steppings. 524 */ 525 { XE_RTP_NAME("18032095049, 16021639441"), 526 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 527 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 528 GHWSP_CSB_REPORT_DIS | 529 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 530 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 531 }, 532 { XE_RTP_NAME("16018610683"), 533 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 534 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 535 }, 536 { XE_RTP_NAME("14021402888"), 537 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 538 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 539 }, 540 541 /* Xe2_HPG */ 542 543 { XE_RTP_NAME("16018712365"), 544 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 545 FUNC(xe_rtp_match_first_render_or_compute)), 546 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 547 }, 548 { XE_RTP_NAME("16018737384"), 549 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 550 FUNC(xe_rtp_match_first_render_or_compute)), 551 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 552 }, 553 { XE_RTP_NAME("14019988906"), 554 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 555 FUNC(xe_rtp_match_first_render_or_compute)), 556 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 557 }, 558 { XE_RTP_NAME("14019877138"), 559 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 560 FUNC(xe_rtp_match_first_render_or_compute)), 561 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 562 }, 563 { XE_RTP_NAME("14020338487"), 564 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 565 FUNC(xe_rtp_match_first_render_or_compute)), 566 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 567 }, 568 { XE_RTP_NAME("18032247524"), 569 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 570 FUNC(xe_rtp_match_first_render_or_compute)), 571 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 572 }, 573 { XE_RTP_NAME("14018471104"), 574 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 575 FUNC(xe_rtp_match_first_render_or_compute)), 576 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 577 }, 578 /* 579 * Although this workaround isn't required for the RCS, disabling these 580 * reports has no impact for our driver or the GuC, so we go ahead and 581 * apply this to all engines for simplicity. 582 */ 583 { XE_RTP_NAME("16021639441"), 584 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 585 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 586 GHWSP_CSB_REPORT_DIS | 587 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 588 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 589 }, 590 { XE_RTP_NAME("14019811474"), 591 XE_RTP_RULES(GRAPHICS_VERSION(2001), 592 FUNC(xe_rtp_match_first_render_or_compute)), 593 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 594 }, 595 { XE_RTP_NAME("14021402888"), 596 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 597 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 598 }, 599 { XE_RTP_NAME("14021821874, 14022954250"), 600 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 601 FUNC(xe_rtp_match_first_render_or_compute)), 602 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 603 }, 604 605 /* Xe2_LPM */ 606 607 { XE_RTP_NAME("16021639441"), 608 XE_RTP_RULES(MEDIA_VERSION(2000)), 609 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 610 GHWSP_CSB_REPORT_DIS | 611 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 612 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 613 }, 614 615 /* Xe2_HPM */ 616 617 { XE_RTP_NAME("16021639441"), 618 XE_RTP_RULES(MEDIA_VERSION(1301)), 619 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 620 GHWSP_CSB_REPORT_DIS | 621 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 622 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 623 }, 624 625 /* Xe3_LPG */ 626 627 { XE_RTP_NAME("14021402888"), 628 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 629 FUNC(xe_rtp_match_first_render_or_compute)), 630 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 631 }, 632 { XE_RTP_NAME("18034896535"), 633 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 634 FUNC(xe_rtp_match_first_render_or_compute)), 635 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 636 }, 637 { XE_RTP_NAME("16024792527"), 638 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 639 FUNC(xe_rtp_match_first_render_or_compute)), 640 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 641 SMP_FORCE_128B_OVERFETCH)) 642 }, 643 { XE_RTP_NAME("14023061436"), 644 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 645 FUNC(xe_rtp_match_first_render_or_compute)), 646 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 647 }, 648 { XE_RTP_NAME("13012615864"), 649 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 650 FUNC(xe_rtp_match_first_render_or_compute)), 651 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 652 }, 653 { XE_RTP_NAME("16023105232"), 654 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 655 GRAPHICS_VERSION_RANGE(2001, 3001)), 656 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 657 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 658 }, 659 { XE_RTP_NAME("14021402888"), 660 XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)), 661 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 662 }, 663 }; 664 665 static const struct xe_rtp_entry_sr lrc_was[] = { 666 { XE_RTP_NAME("16011163337"), 667 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 668 /* read verification is ignored due to 1608008084. */ 669 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 670 FF_MODE2_GS_TIMER_MASK, 671 FF_MODE2_GS_TIMER_224)) 672 }, 673 { XE_RTP_NAME("1604555607"), 674 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 675 /* read verification is ignored due to 1608008084. */ 676 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 677 FF_MODE2_TDS_TIMER_MASK, 678 FF_MODE2_TDS_TIMER_128)) 679 }, 680 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 681 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 682 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 683 DISABLE_CPS_AWARE_COLOR_PIPE)) 684 }, 685 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 686 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 687 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 688 PREEMPT_GPGPU_LEVEL_MASK, 689 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 690 }, 691 { XE_RTP_NAME("1806527549"), 692 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 693 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 694 }, 695 { XE_RTP_NAME("1606376872"), 696 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 697 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 698 }, 699 700 /* DG1 */ 701 702 { XE_RTP_NAME("1409044764"), 703 XE_RTP_RULES(PLATFORM(DG1)), 704 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 705 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 706 }, 707 { XE_RTP_NAME("22010493298"), 708 XE_RTP_RULES(PLATFORM(DG1)), 709 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 710 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 711 }, 712 713 /* DG2 */ 714 715 { XE_RTP_NAME("16013271637"), 716 XE_RTP_RULES(PLATFORM(DG2)), 717 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 718 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 719 }, 720 { XE_RTP_NAME("14014947963"), 721 XE_RTP_RULES(PLATFORM(DG2)), 722 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 723 PREEMPTION_VERTEX_COUNT, 724 0x4000)) 725 }, 726 { XE_RTP_NAME("18018764978"), 727 XE_RTP_RULES(PLATFORM(DG2)), 728 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 729 SCOREBOARD_STALL_FLUSH_CONTROL)) 730 }, 731 { XE_RTP_NAME("18019271663"), 732 XE_RTP_RULES(PLATFORM(DG2)), 733 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 734 }, 735 { XE_RTP_NAME("14019877138"), 736 XE_RTP_RULES(PLATFORM(DG2)), 737 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 738 }, 739 740 /* PVC */ 741 742 { XE_RTP_NAME("16017236439"), 743 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 744 FUNC(xe_rtp_match_even_instance)), 745 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 746 BCS_SWCTRL_DISABLE_256B, 747 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 748 }, 749 750 /* Xe_LPG */ 751 752 { XE_RTP_NAME("18019271663"), 753 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 754 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 755 }, 756 { XE_RTP_NAME("14019877138"), 757 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 758 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 759 }, 760 761 /* Xe2_LPG */ 762 763 { XE_RTP_NAME("16020518922"), 764 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 765 ENGINE_CLASS(RENDER)), 766 XE_RTP_ACTIONS(SET(FF_MODE, 767 DIS_TE_AUTOSTRIP | 768 DIS_MESH_PARTIAL_AUTOSTRIP | 769 DIS_MESH_AUTOSTRIP), 770 SET(VFLSKPD, 771 DIS_PARTIAL_AUTOSTRIP | 772 DIS_AUTOSTRIP)) 773 }, 774 { XE_RTP_NAME("14019386621"), 775 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 776 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 777 }, 778 { XE_RTP_NAME("14019877138"), 779 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 780 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 781 }, 782 { XE_RTP_NAME("14020013138"), 783 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 784 ENGINE_CLASS(RENDER)), 785 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 786 }, 787 { XE_RTP_NAME("14019988906"), 788 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 789 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 790 }, 791 { XE_RTP_NAME("16020183090"), 792 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 793 ENGINE_CLASS(RENDER)), 794 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 795 }, 796 { XE_RTP_NAME("18033852989"), 797 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 798 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 799 }, 800 { XE_RTP_NAME("14021567978"), 801 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 802 ENGINE_CLASS(RENDER)), 803 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 804 }, 805 { XE_RTP_NAME("14020756599"), 806 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 807 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 808 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 809 }, 810 { XE_RTP_NAME("14021490052"), 811 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 812 XE_RTP_ACTIONS(SET(FF_MODE, 813 DIS_MESH_PARTIAL_AUTOSTRIP | 814 DIS_MESH_AUTOSTRIP), 815 SET(VFLSKPD, 816 DIS_PARTIAL_AUTOSTRIP | 817 DIS_AUTOSTRIP)) 818 }, 819 { XE_RTP_NAME("15016589081"), 820 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 821 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 822 }, 823 824 /* Xe2_HPG */ 825 { XE_RTP_NAME("15010599737"), 826 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 827 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 828 }, 829 { XE_RTP_NAME("14019386621"), 830 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 831 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 832 }, 833 { XE_RTP_NAME("14020756599"), 834 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 835 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 836 }, 837 { XE_RTP_NAME("14021490052"), 838 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 839 XE_RTP_ACTIONS(SET(FF_MODE, 840 DIS_MESH_PARTIAL_AUTOSTRIP | 841 DIS_MESH_AUTOSTRIP), 842 SET(VFLSKPD, 843 DIS_PARTIAL_AUTOSTRIP | 844 DIS_AUTOSTRIP)) 845 }, 846 { XE_RTP_NAME("15016589081"), 847 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 848 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 849 }, 850 { XE_RTP_NAME("22021007897"), 851 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 852 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 853 }, 854 { XE_RTP_NAME("18033852989"), 855 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 856 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 857 }, 858 859 /* Xe3_LPG */ 860 { XE_RTP_NAME("14021490052"), 861 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 862 ENGINE_CLASS(RENDER)), 863 XE_RTP_ACTIONS(SET(FF_MODE, 864 DIS_MESH_PARTIAL_AUTOSTRIP | 865 DIS_MESH_AUTOSTRIP), 866 SET(VFLSKPD, 867 DIS_PARTIAL_AUTOSTRIP | 868 DIS_AUTOSTRIP)) 869 }, 870 }; 871 872 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 873 #include <generated/xe_wa_oob.c> 874 {} 875 }; 876 877 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 878 879 __diag_pop(); 880 881 /** 882 * xe_wa_process_oob - process OOB workaround table 883 * @gt: GT instance to process workarounds for 884 * 885 * Process OOB workaround table for this platform, marking in @gt the 886 * workarounds that are active. 887 */ 888 void xe_wa_process_oob(struct xe_gt *gt) 889 { 890 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 891 892 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 893 ARRAY_SIZE(oob_was)); 894 gt->wa_active.oob_initialized = true; 895 xe_rtp_process(&ctx, oob_was); 896 } 897 898 /** 899 * xe_wa_process_gt - process GT workaround table 900 * @gt: GT instance to process workarounds for 901 * 902 * Process GT workaround table for this platform, saving in @gt all the 903 * workarounds that need to be applied at the GT level. 904 */ 905 void xe_wa_process_gt(struct xe_gt *gt) 906 { 907 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 908 909 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 910 ARRAY_SIZE(gt_was)); 911 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 912 } 913 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 914 915 /** 916 * xe_wa_process_engine - process engine workaround table 917 * @hwe: engine instance to process workarounds for 918 * 919 * Process engine workaround table for this platform, saving in @hwe all the 920 * workarounds that need to be applied at the engine level that match this 921 * engine. 922 */ 923 void xe_wa_process_engine(struct xe_hw_engine *hwe) 924 { 925 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 926 927 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 928 ARRAY_SIZE(engine_was)); 929 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 930 } 931 932 /** 933 * xe_wa_process_lrc - process context workaround table 934 * @hwe: engine instance to process workarounds for 935 * 936 * Process context workaround table for this platform, saving in @hwe all the 937 * workarounds that need to be applied on context restore. These are workarounds 938 * touching registers that are part of the HW context image. 939 */ 940 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 941 { 942 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 943 944 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 945 ARRAY_SIZE(lrc_was)); 946 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 947 } 948 949 /** 950 * xe_wa_init - initialize gt with workaround bookkeeping 951 * @gt: GT instance to initialize 952 * 953 * Returns 0 for success, negative error code otherwise. 954 */ 955 int xe_wa_init(struct xe_gt *gt) 956 { 957 struct xe_device *xe = gt_to_xe(gt); 958 size_t n_oob, n_lrc, n_engine, n_gt, total; 959 unsigned long *p; 960 961 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 962 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 963 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 964 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 965 total = n_gt + n_engine + n_lrc + n_oob; 966 967 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 968 if (!p) 969 return -ENOMEM; 970 971 gt->wa_active.gt = p; 972 p += n_gt; 973 gt->wa_active.engine = p; 974 p += n_engine; 975 gt->wa_active.lrc = p; 976 p += n_lrc; 977 gt->wa_active.oob = p; 978 979 return 0; 980 } 981 ALLOW_ERROR_INJECTION(xe_wa_init, ERRNO); /* See xe_pci_probe() */ 982 983 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p) 984 { 985 size_t idx; 986 987 drm_printf(p, "GT Workarounds\n"); 988 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 989 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 990 991 drm_printf(p, "\nEngine Workarounds\n"); 992 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 993 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 994 995 drm_printf(p, "\nLRC Workarounds\n"); 996 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 997 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 998 999 drm_printf(p, "\nOOB Workarounds\n"); 1000 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1001 if (oob_was[idx].name) 1002 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1003 } 1004 1005 /* 1006 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1007 * adding anything to this function; most workarounds should be implemented 1008 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1009 * which are relatively rare. Since the registers these workarounds target are 1010 * outside the GT, they should only need to be applied once at device 1011 * probe/resume; they will not lose their values on any kind of GT or engine 1012 * reset. 1013 * 1014 * TODO: We may want to move this over to xe_rtp in the future once we have 1015 * enough workarounds to justify the work. 1016 */ 1017 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1018 { 1019 struct xe_mmio *mmio = &tile->mmio; 1020 1021 if (IS_SRIOV_VF(tile->xe)) 1022 return; 1023 1024 if (XE_WA(tile->primary_gt, 22010954014)) 1025 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1026 } 1027