1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "regs/xe_engine_regs.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_guc_regs.h" 19 #include "regs/xe_regs.h" 20 #include "xe_device_types.h" 21 #include "xe_force_wake.h" 22 #include "xe_gt_types.h" 23 #include "xe_hw_engine_types.h" 24 #include "xe_mmio.h" 25 #include "xe_platform_types.h" 26 #include "xe_rtp.h" 27 #include "xe_sriov.h" 28 #include "xe_step.h" 29 30 /** 31 * DOC: Hardware workarounds 32 * 33 * Hardware workarounds are register programming documented to be executed in 34 * the driver that fall outside of the normal programming sequences for a 35 * platform. There are some basic categories of workarounds, depending on 36 * how/when they are applied: 37 * 38 * - LRC workarounds: workarounds that touch registers that are 39 * saved/restored to/from the HW context image. The list is emitted (via Load 40 * Register Immediate commands) once when initializing the device and saved in 41 * the default context. That default context is then used on every context 42 * creation to have a "primed golden context", i.e. a context image that 43 * already contains the changes needed to all the registers. See 44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling. 45 * 46 * - Engine workarounds: the list of these WAs is applied whenever the specific 47 * engine is reset. It's also possible that a set of engine classes share a 48 * common power domain and they are reset together. This happens on some 49 * platforms with render and compute engines. In this case (at least) one of 50 * them need to keeep the workaround programming: the approach taken in the 51 * driver is to tie those workarounds to the first compute/render engine that 52 * is registered. When executing with GuC submission, engine resets are 53 * outside of kernel driver control, hence the list of registers involved is 54 * written once, on engine initialization, and then passed to GuC, that 55 * saves/restores their values before/after the reset takes place. See 56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference. 57 * 58 * - GT workarounds: the list of these WAs is applied whenever these registers 59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * - Workaround batchbuffers: buffers that get executed automatically by the 68 * hardware on every HW context restore. These buffers are created and 69 * programmed in the default context so the hardware always go through those 70 * programming sequences when switching contexts. The support for workaround 71 * batchbuffers is enabled via these hardware mechanisms: 72 * 73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer 74 * and an offset are provided in the default context, pointing the hardware 75 * to jump to that location when that offset is reached in the context 76 * restore. When a context is being restored, this is executed after the 77 * ring context, in the middle (or beginning) of the engine context image. 78 * 79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A 80 * batchbuffer is provided in the default context, pointing the hardware to 81 * a buffer to continue executing after the engine registers are restored 82 * in a context restore sequence. 83 * 84 * Below is the timeline for a context restore sequence: 85 * 86 * .. code:: 87 * 88 * INDIRECT_CTX_OFFSET 89 * |----------->| 90 * .------------.------------.-------------.------------.--------------.-----------. 91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring | 92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | 93 * `------------'------------'-------------'------------'--------------'-----------' 94 * 95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 96 * a central place. Those are peppered around the rest of the code, as needed. 97 * There's a central place to control which workarounds are enabled: 98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and 99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. 100 * These files only record which workarounds are enabled: during early device 101 * initialization those rules are evaluated and recorded by the driver. Then 102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to 103 * implement them. 104 * 105 * .. [1] Technically, some registers are powercontext saved & restored, so they 106 * survive a suspend/resume. In practice, writing them again is not too 107 * costly and simplifies things, so it's the approach taken in the driver. 108 * 109 * .. note:: 110 * Hardware workarounds in xe work the same way as in i915, with the 111 * difference of how they are maintained in the code. In xe it uses the 112 * xe_rtp infrastructure so the workarounds can be kept in tables, following 113 * a more declarative approach rather than procedural. 114 * 115 * .. note:: 116 * When a workaround applies to every single known IP version in a range, 117 * the preferred handling is to use a single range-based RTP entry rather 118 * than individual entries for each version, even if some of the intermediate 119 * version numbers are currently unused. If a new intermediate IP version 120 * appears in the future and is enabled in the driver, any existing 121 * range-based entries that contain the new version number will need to be 122 * analyzed to determine whether their workarounds should apply to the new 123 * version, or whether any existing range based entries needs to be split 124 * into two entries that do not include the new intermediate version. 125 */ 126 127 #undef XE_REG_MCR 128 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 129 130 __diag_push(); 131 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 132 133 static const struct xe_rtp_entry_sr gt_was[] = { 134 /* Workarounds applying over a range of IPs */ 135 136 { XE_RTP_NAME("14011060649"), 137 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 138 ENGINE_CLASS(VIDEO_DECODE), 139 FUNC(xe_rtp_match_even_instance)), 140 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 141 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 142 }, 143 { XE_RTP_NAME("14011059788"), 144 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 145 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 146 }, 147 { XE_RTP_NAME("14015795083"), 148 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 149 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 150 }, 151 { XE_RTP_NAME("16021867713"), 152 XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002), 153 ENGINE_CLASS(VIDEO_DECODE)), 154 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 155 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 156 }, 157 { XE_RTP_NAME("14019449301"), 158 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000), ENGINE_CLASS(VIDEO_DECODE)), 159 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 160 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 161 }, 162 { XE_RTP_NAME("16028005424"), 163 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR, 164 MEDIA_VERSION_RANGE(1301, 3500)), 165 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 166 }, 167 168 /* DG1 */ 169 170 { XE_RTP_NAME("1409420604"), 171 XE_RTP_RULES(PLATFORM(DG1)), 172 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 173 }, 174 { XE_RTP_NAME("1408615072"), 175 XE_RTP_RULES(PLATFORM(DG1)), 176 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 177 }, 178 179 /* DG2 */ 180 181 { XE_RTP_NAME("22010523718"), 182 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 183 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 184 }, 185 { XE_RTP_NAME("14011006942"), 186 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 187 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 188 }, 189 { XE_RTP_NAME("14014830051"), 190 XE_RTP_RULES(PLATFORM(DG2)), 191 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 192 }, 193 { XE_RTP_NAME("18018781329"), 194 XE_RTP_RULES(PLATFORM(DG2)), 195 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 196 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 197 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 198 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 199 }, 200 { XE_RTP_NAME("1509235366"), 201 XE_RTP_RULES(PLATFORM(DG2)), 202 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 203 INVALIDATION_BROADCAST_MODE_DIS | 204 GLOBAL_INVALIDATION_MODE)) 205 }, 206 207 /* PVC */ 208 209 { XE_RTP_NAME("18018781329"), 210 XE_RTP_RULES(PLATFORM(PVC)), 211 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 212 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 213 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 214 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 215 }, 216 { XE_RTP_NAME("16016694945"), 217 XE_RTP_RULES(PLATFORM(PVC)), 218 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 219 }, 220 221 /* Xe_LPG */ 222 223 { XE_RTP_NAME("14018575942"), 224 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 225 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 226 }, 227 { XE_RTP_NAME("22016670082"), 228 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 229 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 230 }, 231 232 /* Xe_LPM+ */ 233 234 { XE_RTP_NAME("22016670082"), 235 XE_RTP_RULES(MEDIA_VERSION(1300)), 236 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 237 }, 238 239 /* Xe2_LPM */ 240 241 { XE_RTP_NAME("14017421178"), 242 XE_RTP_RULES(MEDIA_VERSION(2000), 243 ENGINE_CLASS(VIDEO_DECODE)), 244 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 245 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 246 }, 247 248 /* Xe2_HPG */ 249 250 { XE_RTP_NAME("16025250150"), 251 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 252 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2, 253 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK | 254 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK | 255 LSN_DIM_Z_WGT_MASK, 256 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 257 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 258 LSN_DIM_Z_WGT(1))) 259 }, 260 261 /* Xe3_LPG */ 262 263 { XE_RTP_NAME("14021871409"), 264 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 265 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 266 }, 267 268 /* Xe3_LPM */ 269 270 { XE_RTP_NAME("16021865536"), 271 XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002), 272 ENGINE_CLASS(VIDEO_DECODE)), 273 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 274 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 275 }, 276 { XE_RTP_NAME("14021486841"), 277 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 278 ENGINE_CLASS(VIDEO_DECODE)), 279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 281 }, 282 283 /* Xe3P_LPG */ 284 285 { XE_RTP_NAME("14025160223"), 286 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 287 XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D, 288 DIS_ATS_WRONLY_PG)) 289 }, 290 { XE_RTP_NAME("16028780921"), 291 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 292 XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS)) 293 }, 294 { XE_RTP_NAME("14026144927"), 295 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 296 XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH | 297 L3_SQ_DISABLE_COAMA)) 298 }, 299 { XE_RTP_NAME("14025635424"), 300 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 301 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE)) 302 }, 303 { XE_RTP_NAME("16028005424"), 304 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 305 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 306 }, 307 }; 308 309 static const struct xe_rtp_entry_sr engine_was[] = { 310 /* Workarounds applying over a range of IPs */ 311 312 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 313 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 314 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 315 FF_TESSELATION_DOP_GATE_DISABLE)) 316 }, 317 { XE_RTP_NAME("1409804808"), 318 XE_RTP_RULES(GRAPHICS_VERSION(1200), 319 ENGINE_CLASS(RENDER), 320 IS_INTEGRATED), 321 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 322 }, 323 { XE_RTP_NAME("14010229206, 1409085225"), 324 XE_RTP_RULES(GRAPHICS_VERSION(1200), 325 ENGINE_CLASS(RENDER), 326 IS_INTEGRATED), 327 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 328 }, 329 { XE_RTP_NAME("1606931601"), 330 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 331 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 332 }, 333 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 334 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 335 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 336 FF_DOP_CLOCK_GATE_DISABLE)) 337 }, 338 { XE_RTP_NAME("1406941453"), 339 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 340 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 341 }, 342 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 343 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 344 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 345 FFSC_PERCTX_PREEMPT_CTRL)) 346 }, 347 { XE_RTP_NAME("18032247524"), 348 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 349 FUNC(xe_rtp_match_first_render_or_compute)), 350 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 351 }, 352 { XE_RTP_NAME("16018712365"), 353 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 354 FUNC(xe_rtp_match_first_render_or_compute)), 355 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 356 }, 357 { XE_RTP_NAME("14020338487"), 358 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 359 FUNC(xe_rtp_match_first_render_or_compute)), 360 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 361 }, 362 { XE_RTP_NAME("14018471104"), 363 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 364 FUNC(xe_rtp_match_first_render_or_compute)), 365 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 366 }, 367 /* 368 * Although this workaround isn't required for the RCS, disabling these 369 * reports has no impact for our driver or the GuC, so we go ahead and 370 * apply this to all engines for simplicity. 371 */ 372 { XE_RTP_NAME("16021639441"), 373 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), OR, 374 MEDIA_VERSION_RANGE(1301, 2000)), 375 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 376 GHWSP_CSB_REPORT_DIS | 377 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 378 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 379 }, 380 { XE_RTP_NAME("14021402888"), 381 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), ENGINE_CLASS(RENDER)), 382 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 383 }, 384 { XE_RTP_NAME("13012615864"), 385 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), 386 FUNC(xe_rtp_match_first_render_or_compute)), 387 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 388 }, 389 { XE_RTP_NAME("18041344222"), 390 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000), 391 FUNC(xe_rtp_match_first_render_or_compute), 392 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 393 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 394 }, 395 396 /* TGL */ 397 398 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 399 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 400 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 401 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 402 RC_SEMA_IDLE_MSG_DISABLE)) 403 }, 404 405 /* RKL */ 406 407 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 408 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 409 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 410 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 411 RC_SEMA_IDLE_MSG_DISABLE)) 412 }, 413 414 /* ADL-P */ 415 416 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 417 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 418 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 419 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 420 RC_SEMA_IDLE_MSG_DISABLE)) 421 }, 422 423 /* DG2 */ 424 425 { XE_RTP_NAME("22013037850"), 426 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 427 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 428 DISABLE_128B_EVICTION_COMMAND_UDW)) 429 }, 430 { XE_RTP_NAME("22014226127"), 431 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 432 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 433 }, 434 { XE_RTP_NAME("18017747507"), 435 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 436 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 437 POLYGON_TRIFAN_LINELOOP_DISABLE)) 438 }, 439 { XE_RTP_NAME("22012826095, 22013059131"), 440 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 441 FUNC(xe_rtp_match_first_render_or_compute)), 442 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 443 MAXREQS_PER_BANK, 444 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 445 }, 446 { XE_RTP_NAME("22013059131"), 447 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 448 FUNC(xe_rtp_match_first_render_or_compute)), 449 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 450 }, 451 { XE_RTP_NAME("14015227452"), 452 XE_RTP_RULES(PLATFORM(DG2), 453 FUNC(xe_rtp_match_first_render_or_compute)), 454 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 455 }, 456 { XE_RTP_NAME("18028616096"), 457 XE_RTP_RULES(PLATFORM(DG2), 458 FUNC(xe_rtp_match_first_render_or_compute)), 459 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 460 }, 461 { XE_RTP_NAME("22015475538"), 462 XE_RTP_RULES(PLATFORM(DG2), 463 FUNC(xe_rtp_match_first_render_or_compute)), 464 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 465 }, 466 { XE_RTP_NAME("22012654132"), 467 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 468 FUNC(xe_rtp_match_first_render_or_compute)), 469 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 470 /* 471 * Register can't be read back for verification on 472 * DG2 due to Wa_14012342262 473 */ 474 .read_mask = 0)) 475 }, 476 { XE_RTP_NAME("1509727124"), 477 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 478 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 479 }, 480 { XE_RTP_NAME("22012856258"), 481 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 482 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 483 }, 484 { XE_RTP_NAME("22010960976, 14013347512"), 485 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 486 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 487 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 488 }, 489 { XE_RTP_NAME("14015150844"), 490 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 491 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 492 XE_RTP_NOCHECK)) 493 }, 494 495 /* PVC */ 496 497 { XE_RTP_NAME("22014226127"), 498 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 499 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 500 }, 501 { XE_RTP_NAME("14015227452"), 502 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 503 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 504 }, 505 { XE_RTP_NAME("18020744125"), 506 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 507 ENGINE_CLASS(COMPUTE)), 508 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 509 }, 510 511 /* Xe_LPG */ 512 513 { XE_RTP_NAME("14017856879"), 514 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 515 FUNC(xe_rtp_match_first_render_or_compute)), 516 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 517 }, 518 { XE_RTP_NAME("14015150844"), 519 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 520 FUNC(xe_rtp_match_first_render_or_compute)), 521 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 522 XE_RTP_NOCHECK)) 523 }, 524 { XE_RTP_NAME("14020495402"), 525 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 526 FUNC(xe_rtp_match_first_render_or_compute)), 527 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 528 }, 529 530 /* Xe2_LPG */ 531 532 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 533 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 534 FUNC(xe_rtp_match_first_render_or_compute)), 535 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 536 }, 537 { XE_RTP_NAME("16018610683"), 538 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 539 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 540 }, 541 542 /* Xe2_HPG */ 543 544 { XE_RTP_NAME("16018737384"), 545 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2999), 546 FUNC(xe_rtp_match_first_render_or_compute)), 547 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 548 }, 549 { XE_RTP_NAME("14019811474"), 550 XE_RTP_RULES(GRAPHICS_VERSION(2001), 551 FUNC(xe_rtp_match_first_render_or_compute)), 552 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 553 }, 554 { XE_RTP_NAME("14021821874, 14022954250"), 555 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 556 FUNC(xe_rtp_match_first_render_or_compute)), 557 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 558 }, 559 560 /* Xe3_LPG */ 561 562 { XE_RTP_NAME("18034896535"), 563 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 564 FUNC(xe_rtp_match_first_render_or_compute)), 565 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 566 }, 567 { XE_RTP_NAME("16024792527"), 568 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 569 FUNC(xe_rtp_match_first_render_or_compute)), 570 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 571 SMP_FORCE_128B_OVERFETCH)) 572 }, 573 { XE_RTP_NAME("14023061436"), 574 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), 575 FUNC(xe_rtp_match_first_render_or_compute)), 576 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 577 }, 578 { XE_RTP_NAME("16023105232"), 579 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 580 GRAPHICS_VERSION_RANGE(2001, 3001)), 581 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 582 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 583 }, 584 585 /* Xe3p_LPG*/ 586 587 { XE_RTP_NAME("22021149932"), 588 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), 589 FUNC(xe_rtp_match_first_render_or_compute)), 590 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE)) 591 }, 592 { XE_RTP_NAME("14025676848"), 593 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), 594 FUNC(xe_rtp_match_first_render_or_compute)), 595 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE)) 596 }, 597 { XE_RTP_NAME("16028951944"), 598 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), 599 FUNC(xe_rtp_match_first_render_or_compute)), 600 XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS)) 601 }, 602 }; 603 604 static const struct xe_rtp_entry_sr lrc_was[] = { 605 { XE_RTP_NAME("16011163337"), 606 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 607 /* read verification is ignored due to 1608008084. */ 608 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 609 FF_MODE2_GS_TIMER_MASK, 610 FF_MODE2_GS_TIMER_224)) 611 }, 612 { XE_RTP_NAME("1604555607"), 613 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 614 /* read verification is ignored due to 1608008084. */ 615 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 616 FF_MODE2_TDS_TIMER_MASK, 617 FF_MODE2_TDS_TIMER_128)) 618 }, 619 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 620 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 621 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 622 DISABLE_CPS_AWARE_COLOR_PIPE)) 623 }, 624 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 625 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 626 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 627 PREEMPT_GPGPU_LEVEL_MASK, 628 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 629 }, 630 { XE_RTP_NAME("1806527549"), 631 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 632 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 633 }, 634 { XE_RTP_NAME("1606376872"), 635 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 636 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 637 }, 638 { XE_RTP_NAME("14019877138"), 639 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)), 640 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 641 }, 642 { XE_RTP_NAME("14019386621"), 643 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 644 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 645 }, 646 { XE_RTP_NAME("14019988906"), 647 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 648 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 649 }, 650 { XE_RTP_NAME("18033852989"), 651 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 652 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 653 }, 654 { XE_RTP_NAME("15016589081"), 655 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 656 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 657 }, 658 659 /* DG1 */ 660 661 { XE_RTP_NAME("1409044764"), 662 XE_RTP_RULES(PLATFORM(DG1)), 663 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 664 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 665 }, 666 { XE_RTP_NAME("22010493298"), 667 XE_RTP_RULES(PLATFORM(DG1)), 668 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 669 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 670 }, 671 672 /* DG2 */ 673 674 { XE_RTP_NAME("16013271637"), 675 XE_RTP_RULES(PLATFORM(DG2)), 676 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 677 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 678 }, 679 { XE_RTP_NAME("14014947963"), 680 XE_RTP_RULES(PLATFORM(DG2)), 681 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 682 PREEMPTION_VERTEX_COUNT, 683 0x4000)) 684 }, 685 { XE_RTP_NAME("18018764978"), 686 XE_RTP_RULES(PLATFORM(DG2)), 687 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 688 SCOREBOARD_STALL_FLUSH_CONTROL)) 689 }, 690 { XE_RTP_NAME("18019271663"), 691 XE_RTP_RULES(PLATFORM(DG2)), 692 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 693 }, 694 695 /* PVC */ 696 697 { XE_RTP_NAME("16017236439"), 698 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 699 FUNC(xe_rtp_match_even_instance)), 700 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 701 BCS_SWCTRL_DISABLE_256B, 702 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 703 }, 704 705 /* Xe_LPG */ 706 707 { XE_RTP_NAME("18019271663"), 708 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 709 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 710 }, 711 712 /* Xe2_LPG */ 713 714 { XE_RTP_NAME("14021567978"), 715 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 716 ENGINE_CLASS(RENDER)), 717 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 718 }, 719 { XE_RTP_NAME("14020756599"), 720 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 721 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 722 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 723 }, 724 { XE_RTP_NAME("14021490052"), 725 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 726 XE_RTP_ACTIONS(SET(FF_MODE, 727 DIS_MESH_PARTIAL_AUTOSTRIP | 728 DIS_MESH_AUTOSTRIP), 729 SET(VFLSKPD, 730 DIS_PARTIAL_AUTOSTRIP | 731 DIS_AUTOSTRIP)) 732 }, 733 734 /* Xe2_HPG */ 735 736 { XE_RTP_NAME("14020756599"), 737 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 738 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 739 }, 740 { XE_RTP_NAME("14019988906"), 741 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 742 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 743 }, 744 { XE_RTP_NAME("14019877138"), 745 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 746 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 747 }, 748 { XE_RTP_NAME("14021490052"), 749 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 750 XE_RTP_ACTIONS(SET(FF_MODE, 751 DIS_MESH_PARTIAL_AUTOSTRIP | 752 DIS_MESH_AUTOSTRIP), 753 SET(VFLSKPD, 754 DIS_PARTIAL_AUTOSTRIP | 755 DIS_AUTOSTRIP)) 756 }, 757 { XE_RTP_NAME("22021007897"), 758 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 759 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 760 }, 761 762 /* Xe3_LPG */ 763 { XE_RTP_NAME("14021490052"), 764 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 765 ENGINE_CLASS(RENDER)), 766 XE_RTP_ACTIONS(SET(FF_MODE, 767 DIS_MESH_PARTIAL_AUTOSTRIP | 768 DIS_MESH_AUTOSTRIP), 769 SET(VFLSKPD, 770 DIS_PARTIAL_AUTOSTRIP | 771 DIS_AUTOSTRIP)) 772 }, 773 { XE_RTP_NAME("22021007897"), 774 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 775 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 776 }, 777 { XE_RTP_NAME("14024681466"), 778 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 779 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 780 }, 781 { XE_RTP_NAME("15016589081"), 782 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 783 ENGINE_CLASS(RENDER)), 784 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 785 }, 786 { XE_RTP_NAME("14026781792"), 787 XE_RTP_RULES(GRAPHICS_VERSION(3510), ENGINE_CLASS(RENDER)), 788 XE_RTP_ACTIONS(SET(FF_MODE, DIS_TE_PATCH_CTRL)) 789 }, 790 }; 791 792 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 793 #include <generated/xe_wa_oob.c> 794 {} 795 }; 796 797 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 798 799 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 800 #include <generated/xe_device_wa_oob.c> 801 {} 802 }; 803 804 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 805 806 __diag_pop(); 807 808 /** 809 * xe_wa_process_device_oob - process OOB workaround table 810 * @xe: device instance to process workarounds for 811 * 812 * process OOB workaround table for this device, marking in @xe the 813 * workarounds that are active. 814 */ 815 816 void xe_wa_process_device_oob(struct xe_device *xe) 817 { 818 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 819 820 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 821 822 xe->wa_active.oob_initialized = true; 823 xe_rtp_process(&ctx, device_oob_was); 824 } 825 826 /** 827 * xe_wa_process_gt_oob - process GT OOB workaround table 828 * @gt: GT instance to process workarounds for 829 * 830 * Process OOB workaround table for this platform, marking in @gt the 831 * workarounds that are active. 832 */ 833 void xe_wa_process_gt_oob(struct xe_gt *gt) 834 { 835 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 836 837 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 838 ARRAY_SIZE(oob_was)); 839 gt->wa_active.oob_initialized = true; 840 xe_rtp_process(&ctx, oob_was); 841 } 842 843 /** 844 * xe_wa_process_gt - process GT workaround table 845 * @gt: GT instance to process workarounds for 846 * 847 * Process GT workaround table for this platform, saving in @gt all the 848 * workarounds that need to be applied at the GT level. 849 */ 850 void xe_wa_process_gt(struct xe_gt *gt) 851 { 852 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 853 854 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 855 ARRAY_SIZE(gt_was)); 856 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), 857 >->reg_sr, false); 858 } 859 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 860 861 /** 862 * xe_wa_process_engine - process engine workaround table 863 * @hwe: engine instance to process workarounds for 864 * 865 * Process engine workaround table for this platform, saving in @hwe all the 866 * workarounds that need to be applied at the engine level that match this 867 * engine. 868 */ 869 void xe_wa_process_engine(struct xe_hw_engine *hwe) 870 { 871 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 872 873 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 874 ARRAY_SIZE(engine_was)); 875 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), 876 &hwe->reg_sr, false); 877 } 878 879 /** 880 * xe_wa_process_lrc - process context workaround table 881 * @hwe: engine instance to process workarounds for 882 * 883 * Process context workaround table for this platform, saving in @hwe all the 884 * workarounds that need to be applied on context restore. These are workarounds 885 * touching registers that are part of the HW context image. 886 */ 887 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 888 { 889 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 890 891 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 892 ARRAY_SIZE(lrc_was)); 893 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), 894 &hwe->reg_lrc, true); 895 } 896 897 /** 898 * xe_wa_device_init - initialize device with workaround oob bookkeeping 899 * @xe: Xe device instance to initialize 900 * 901 * Returns 0 for success, negative with error code otherwise 902 */ 903 int xe_wa_device_init(struct xe_device *xe) 904 { 905 unsigned long *p; 906 907 p = drmm_kzalloc(&xe->drm, 908 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 909 GFP_KERNEL); 910 911 if (!p) 912 return -ENOMEM; 913 914 xe->wa_active.oob = p; 915 916 return 0; 917 } 918 919 /** 920 * xe_wa_gt_init - initialize gt with workaround bookkeeping 921 * @gt: GT instance to initialize 922 * 923 * Returns 0 for success, negative error code otherwise. 924 */ 925 int xe_wa_gt_init(struct xe_gt *gt) 926 { 927 struct xe_device *xe = gt_to_xe(gt); 928 size_t n_oob, n_lrc, n_engine, n_gt, total; 929 unsigned long *p; 930 931 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 932 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 933 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 934 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 935 total = n_gt + n_engine + n_lrc + n_oob; 936 937 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 938 if (!p) 939 return -ENOMEM; 940 941 gt->wa_active.gt = p; 942 p += n_gt; 943 gt->wa_active.engine = p; 944 p += n_engine; 945 gt->wa_active.lrc = p; 946 p += n_lrc; 947 gt->wa_active.oob = p; 948 949 return 0; 950 } 951 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 952 953 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 954 { 955 size_t idx; 956 957 drm_printf(p, "Device OOB Workarounds\n"); 958 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 959 if (device_oob_was[idx].name) 960 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 961 } 962 963 /** 964 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer. 965 * @gt: the &xe_gt 966 * @p: the &drm_printer 967 * 968 * Return: always 0. 969 */ 970 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p) 971 { 972 size_t idx; 973 974 drm_printf(p, "GT Workarounds\n"); 975 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 976 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 977 978 drm_puts(p, "\n"); 979 drm_printf(p, "Engine Workarounds\n"); 980 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 981 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 982 983 drm_puts(p, "\n"); 984 drm_printf(p, "LRC Workarounds\n"); 985 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 986 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 987 988 drm_puts(p, "\n"); 989 drm_printf(p, "OOB Workarounds\n"); 990 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 991 if (oob_was[idx].name) 992 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 993 return 0; 994 } 995 996 /* 997 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 998 * adding anything to this function; most workarounds should be implemented 999 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1000 * which are relatively rare. Since the registers these workarounds target are 1001 * outside the GT, they should only need to be applied once at device 1002 * probe/resume; they will not lose their values on any kind of GT or engine 1003 * reset. 1004 * 1005 * TODO: We may want to move this over to xe_rtp in the future once we have 1006 * enough workarounds to justify the work. 1007 */ 1008 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1009 { 1010 struct xe_mmio *mmio = &tile->mmio; 1011 1012 if (IS_SRIOV_VF(tile->xe)) 1013 return; 1014 1015 if (XE_DEVICE_WA(tile->xe, 22010954014)) 1016 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1017 } 1018