1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "regs/xe_engine_regs.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_guc_regs.h" 19 #include "regs/xe_regs.h" 20 #include "xe_device_types.h" 21 #include "xe_force_wake.h" 22 #include "xe_gt_types.h" 23 #include "xe_hw_engine_types.h" 24 #include "xe_mmio.h" 25 #include "xe_platform_types.h" 26 #include "xe_rtp.h" 27 #include "xe_sriov.h" 28 #include "xe_step.h" 29 30 /** 31 * DOC: Hardware workarounds 32 * 33 * Hardware workarounds are register programming documented to be executed in 34 * the driver that fall outside of the normal programming sequences for a 35 * platform. There are some basic categories of workarounds, depending on 36 * how/when they are applied: 37 * 38 * - LRC workarounds: workarounds that touch registers that are 39 * saved/restored to/from the HW context image. The list is emitted (via Load 40 * Register Immediate commands) once when initializing the device and saved in 41 * the default context. That default context is then used on every context 42 * creation to have a "primed golden context", i.e. a context image that 43 * already contains the changes needed to all the registers. See 44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling. 45 * 46 * - Engine workarounds: the list of these WAs is applied whenever the specific 47 * engine is reset. It's also possible that a set of engine classes share a 48 * common power domain and they are reset together. This happens on some 49 * platforms with render and compute engines. In this case (at least) one of 50 * them need to keeep the workaround programming: the approach taken in the 51 * driver is to tie those workarounds to the first compute/render engine that 52 * is registered. When executing with GuC submission, engine resets are 53 * outside of kernel driver control, hence the list of registers involved is 54 * written once, on engine initialization, and then passed to GuC, that 55 * saves/restores their values before/after the reset takes place. See 56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference. 57 * 58 * - GT workarounds: the list of these WAs is applied whenever these registers 59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * - Workaround batchbuffers: buffers that get executed automatically by the 68 * hardware on every HW context restore. These buffers are created and 69 * programmed in the default context so the hardware always go through those 70 * programming sequences when switching contexts. The support for workaround 71 * batchbuffers is enabled via these hardware mechanisms: 72 * 73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer 74 * and an offset are provided in the default context, pointing the hardware 75 * to jump to that location when that offset is reached in the context 76 * restore. When a context is being restored, this is executed after the 77 * ring context, in the middle (or beginning) of the engine context image. 78 * 79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A 80 * batchbuffer is provided in the default context, pointing the hardware to 81 * a buffer to continue executing after the engine registers are restored 82 * in a context restore sequence. 83 * 84 * Below is the timeline for a context restore sequence: 85 * 86 * .. code:: 87 * 88 * INDIRECT_CTX_OFFSET 89 * |----------->| 90 * .------------.------------.-------------.------------.--------------.-----------. 91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring | 92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | 93 * `------------'------------'-------------'------------'--------------'-----------' 94 * 95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 96 * a central place. Those are peppered around the rest of the code, as needed. 97 * There's a central place to control which workarounds are enabled: 98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and 99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. 100 * These files only record which workarounds are enabled: during early device 101 * initialization those rules are evaluated and recorded by the driver. Then 102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to 103 * implement them. 104 * 105 * .. [1] Technically, some registers are powercontext saved & restored, so they 106 * survive a suspend/resume. In practice, writing them again is not too 107 * costly and simplifies things, so it's the approach taken in the driver. 108 * 109 * .. note:: 110 * Hardware workarounds in xe work the same way as in i915, with the 111 * difference of how they are maintained in the code. In xe it uses the 112 * xe_rtp infrastructure so the workarounds can be kept in tables, following 113 * a more declarative approach rather than procedural. 114 * 115 * .. note:: 116 * When a workaround applies to every single known IP version in a range, 117 * the preferred handling is to use a single range-based RTP entry rather 118 * than individual entries for each version, even if some of the intermediate 119 * version numbers are currently unused. If a new intermediate IP version 120 * appears in the future and is enabled in the driver, any existing 121 * range-based entries that contain the new version number will need to be 122 * analyzed to determine whether their workarounds should apply to the new 123 * version, or whether any existing range based entries needs to be split 124 * into two entries that do not include the new intermediate version. 125 */ 126 127 #undef XE_REG_MCR 128 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 129 130 __diag_push(); 131 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 132 133 static const struct xe_rtp_entry_sr gt_was[] = { 134 /* Workarounds applying over a range of IPs */ 135 136 { XE_RTP_NAME("14011060649"), 137 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 138 ENGINE_CLASS(VIDEO_DECODE), 139 FUNC(xe_rtp_match_even_instance)), 140 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 141 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 142 }, 143 { XE_RTP_NAME("14011059788"), 144 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 145 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 146 }, 147 { XE_RTP_NAME("14015795083"), 148 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 149 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 150 }, 151 { XE_RTP_NAME("16021867713"), 152 XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002), 153 ENGINE_CLASS(VIDEO_DECODE)), 154 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 155 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 156 }, 157 { XE_RTP_NAME("14019449301"), 158 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000), ENGINE_CLASS(VIDEO_DECODE)), 159 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 160 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 161 }, 162 { XE_RTP_NAME("16028005424"), 163 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR, 164 MEDIA_VERSION_RANGE(1301, 3500)), 165 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 166 }, 167 168 /* DG1 */ 169 170 { XE_RTP_NAME("1409420604"), 171 XE_RTP_RULES(PLATFORM(DG1)), 172 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 173 }, 174 { XE_RTP_NAME("1408615072"), 175 XE_RTP_RULES(PLATFORM(DG1)), 176 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 177 }, 178 179 /* DG2 */ 180 181 { XE_RTP_NAME("22010523718"), 182 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 183 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 184 }, 185 { XE_RTP_NAME("14011006942"), 186 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 187 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 188 }, 189 { XE_RTP_NAME("14014830051"), 190 XE_RTP_RULES(PLATFORM(DG2)), 191 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 192 }, 193 { XE_RTP_NAME("18018781329"), 194 XE_RTP_RULES(PLATFORM(DG2)), 195 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 196 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 197 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 198 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 199 }, 200 { XE_RTP_NAME("1509235366"), 201 XE_RTP_RULES(PLATFORM(DG2)), 202 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 203 INVALIDATION_BROADCAST_MODE_DIS | 204 GLOBAL_INVALIDATION_MODE)) 205 }, 206 207 /* PVC */ 208 209 { XE_RTP_NAME("18018781329"), 210 XE_RTP_RULES(PLATFORM(PVC)), 211 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 212 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 213 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 214 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 215 }, 216 { XE_RTP_NAME("16016694945"), 217 XE_RTP_RULES(PLATFORM(PVC)), 218 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 219 }, 220 221 /* Xe_LPG */ 222 223 { XE_RTP_NAME("14018575942"), 224 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 225 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 226 }, 227 { XE_RTP_NAME("22016670082"), 228 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 229 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 230 }, 231 232 /* Xe_LPM+ */ 233 234 { XE_RTP_NAME("22016670082"), 235 XE_RTP_RULES(MEDIA_VERSION(1300)), 236 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 237 }, 238 239 /* Xe2_LPM */ 240 241 { XE_RTP_NAME("14017421178"), 242 XE_RTP_RULES(MEDIA_VERSION(2000), 243 ENGINE_CLASS(VIDEO_DECODE)), 244 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 245 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 246 }, 247 248 /* Xe2_HPG */ 249 250 { XE_RTP_NAME("16025250150"), 251 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 252 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2, 253 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK | 254 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK | 255 LSN_DIM_Z_WGT_MASK, 256 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 257 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 258 LSN_DIM_Z_WGT(1))) 259 }, 260 261 /* Xe2_HPM */ 262 263 { XE_RTP_NAME("16021867713"), 264 XE_RTP_RULES(MEDIA_VERSION(1301), 265 ENGINE_CLASS(VIDEO_DECODE)), 266 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 267 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 268 }, 269 { XE_RTP_NAME("14019449301"), 270 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 271 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 272 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 273 }, 274 275 /* Xe3_LPG */ 276 277 { XE_RTP_NAME("14021871409"), 278 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 279 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 280 }, 281 282 /* Xe3_LPM */ 283 284 { XE_RTP_NAME("16021865536"), 285 XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002), 286 ENGINE_CLASS(VIDEO_DECODE)), 287 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 288 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 289 }, 290 { XE_RTP_NAME("14021486841"), 291 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 292 ENGINE_CLASS(VIDEO_DECODE)), 293 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 294 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 295 }, 296 297 /* Xe3P_LPG */ 298 299 { XE_RTP_NAME("14025160223"), 300 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 301 XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D, 302 DIS_ATS_WRONLY_PG)) 303 }, 304 { XE_RTP_NAME("16028780921"), 305 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 306 XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS)) 307 }, 308 { XE_RTP_NAME("14026144927"), 309 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 310 XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH | 311 L3_SQ_DISABLE_COAMA)) 312 }, 313 { XE_RTP_NAME("14025635424"), 314 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 315 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE)) 316 }, 317 { XE_RTP_NAME("16028005424"), 318 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), 319 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 320 }, 321 }; 322 323 static const struct xe_rtp_entry_sr engine_was[] = { 324 /* Workarounds applying over a range of IPs */ 325 326 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 327 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 328 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 329 FF_TESSELATION_DOP_GATE_DISABLE)) 330 }, 331 { XE_RTP_NAME("1409804808"), 332 XE_RTP_RULES(GRAPHICS_VERSION(1200), 333 ENGINE_CLASS(RENDER), 334 IS_INTEGRATED), 335 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 336 }, 337 { XE_RTP_NAME("14010229206, 1409085225"), 338 XE_RTP_RULES(GRAPHICS_VERSION(1200), 339 ENGINE_CLASS(RENDER), 340 IS_INTEGRATED), 341 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 342 }, 343 { XE_RTP_NAME("1606931601"), 344 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 345 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 346 }, 347 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 348 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 349 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 350 FF_DOP_CLOCK_GATE_DISABLE)) 351 }, 352 { XE_RTP_NAME("1406941453"), 353 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 354 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 355 }, 356 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 357 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 358 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 359 FFSC_PERCTX_PREEMPT_CTRL)) 360 }, 361 { XE_RTP_NAME("18032247524"), 362 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 363 FUNC(xe_rtp_match_first_render_or_compute)), 364 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 365 }, 366 { XE_RTP_NAME("16018712365"), 367 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 368 FUNC(xe_rtp_match_first_render_or_compute)), 369 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 370 }, 371 { XE_RTP_NAME("14020338487"), 372 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 373 FUNC(xe_rtp_match_first_render_or_compute)), 374 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 375 }, 376 { XE_RTP_NAME("14018471104"), 377 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 378 FUNC(xe_rtp_match_first_render_or_compute)), 379 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 380 }, 381 /* 382 * Although this workaround isn't required for the RCS, disabling these 383 * reports has no impact for our driver or the GuC, so we go ahead and 384 * apply this to all engines for simplicity. 385 */ 386 { XE_RTP_NAME("16021639441"), 387 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), OR, 388 MEDIA_VERSION_RANGE(1301, 2000)), 389 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 390 GHWSP_CSB_REPORT_DIS | 391 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 392 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 393 }, 394 { XE_RTP_NAME("14021402888"), 395 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), ENGINE_CLASS(RENDER)), 396 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 397 }, 398 { XE_RTP_NAME("13012615864"), 399 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), 400 FUNC(xe_rtp_match_first_render_or_compute)), 401 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 402 }, 403 { XE_RTP_NAME("18041344222"), 404 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000), 405 FUNC(xe_rtp_match_first_render_or_compute), 406 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 407 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 408 }, 409 410 /* TGL */ 411 412 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 413 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 414 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 415 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 416 RC_SEMA_IDLE_MSG_DISABLE)) 417 }, 418 419 /* RKL */ 420 421 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 422 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 423 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 424 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 425 RC_SEMA_IDLE_MSG_DISABLE)) 426 }, 427 428 /* ADL-P */ 429 430 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 431 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 432 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 433 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 434 RC_SEMA_IDLE_MSG_DISABLE)) 435 }, 436 437 /* DG2 */ 438 439 { XE_RTP_NAME("22013037850"), 440 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 441 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 442 DISABLE_128B_EVICTION_COMMAND_UDW)) 443 }, 444 { XE_RTP_NAME("22014226127"), 445 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 446 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 447 }, 448 { XE_RTP_NAME("18017747507"), 449 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 450 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 451 POLYGON_TRIFAN_LINELOOP_DISABLE)) 452 }, 453 { XE_RTP_NAME("22012826095, 22013059131"), 454 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 455 FUNC(xe_rtp_match_first_render_or_compute)), 456 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 457 MAXREQS_PER_BANK, 458 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 459 }, 460 { XE_RTP_NAME("22013059131"), 461 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 462 FUNC(xe_rtp_match_first_render_or_compute)), 463 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 464 }, 465 { XE_RTP_NAME("14015227452"), 466 XE_RTP_RULES(PLATFORM(DG2), 467 FUNC(xe_rtp_match_first_render_or_compute)), 468 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 469 }, 470 { XE_RTP_NAME("18028616096"), 471 XE_RTP_RULES(PLATFORM(DG2), 472 FUNC(xe_rtp_match_first_render_or_compute)), 473 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 474 }, 475 { XE_RTP_NAME("22015475538"), 476 XE_RTP_RULES(PLATFORM(DG2), 477 FUNC(xe_rtp_match_first_render_or_compute)), 478 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 479 }, 480 { XE_RTP_NAME("22012654132"), 481 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 482 FUNC(xe_rtp_match_first_render_or_compute)), 483 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 484 /* 485 * Register can't be read back for verification on 486 * DG2 due to Wa_14012342262 487 */ 488 .read_mask = 0)) 489 }, 490 { XE_RTP_NAME("1509727124"), 491 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 492 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 493 }, 494 { XE_RTP_NAME("22012856258"), 495 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 496 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 497 }, 498 { XE_RTP_NAME("22010960976, 14013347512"), 499 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 500 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 501 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 502 }, 503 { XE_RTP_NAME("14015150844"), 504 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 505 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 506 XE_RTP_NOCHECK)) 507 }, 508 509 /* PVC */ 510 511 { XE_RTP_NAME("22014226127"), 512 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 513 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 514 }, 515 { XE_RTP_NAME("14015227452"), 516 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 517 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 518 }, 519 { XE_RTP_NAME("18020744125"), 520 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 521 ENGINE_CLASS(COMPUTE)), 522 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 523 }, 524 525 /* Xe_LPG */ 526 527 { XE_RTP_NAME("14017856879"), 528 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 529 FUNC(xe_rtp_match_first_render_or_compute)), 530 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 531 }, 532 { XE_RTP_NAME("14015150844"), 533 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 534 FUNC(xe_rtp_match_first_render_or_compute)), 535 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 536 XE_RTP_NOCHECK)) 537 }, 538 { XE_RTP_NAME("14020495402"), 539 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 540 FUNC(xe_rtp_match_first_render_or_compute)), 541 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 542 }, 543 544 /* Xe2_LPG */ 545 546 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 547 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 548 FUNC(xe_rtp_match_first_render_or_compute)), 549 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 550 }, 551 { XE_RTP_NAME("16018610683"), 552 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 553 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 554 }, 555 556 /* Xe2_HPG */ 557 558 { XE_RTP_NAME("16018737384"), 559 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2999), 560 FUNC(xe_rtp_match_first_render_or_compute)), 561 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 562 }, 563 { XE_RTP_NAME("14019811474"), 564 XE_RTP_RULES(GRAPHICS_VERSION(2001), 565 FUNC(xe_rtp_match_first_render_or_compute)), 566 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 567 }, 568 { XE_RTP_NAME("14021821874, 14022954250"), 569 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 570 FUNC(xe_rtp_match_first_render_or_compute)), 571 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 572 }, 573 574 /* Xe3_LPG */ 575 576 { XE_RTP_NAME("18034896535"), 577 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 578 FUNC(xe_rtp_match_first_render_or_compute)), 579 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 580 }, 581 { XE_RTP_NAME("16024792527"), 582 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 583 FUNC(xe_rtp_match_first_render_or_compute)), 584 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 585 SMP_FORCE_128B_OVERFETCH)) 586 }, 587 { XE_RTP_NAME("14023061436"), 588 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), 589 FUNC(xe_rtp_match_first_render_or_compute)), 590 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 591 }, 592 { XE_RTP_NAME("16023105232"), 593 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 594 GRAPHICS_VERSION_RANGE(2001, 3001)), 595 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 596 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 597 }, 598 599 /* Xe3p_LPG*/ 600 601 { XE_RTP_NAME("22021149932"), 602 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), 603 FUNC(xe_rtp_match_first_render_or_compute)), 604 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE)) 605 }, 606 { XE_RTP_NAME("14025676848"), 607 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), 608 FUNC(xe_rtp_match_first_render_or_compute)), 609 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE)) 610 }, 611 { XE_RTP_NAME("16028951944"), 612 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0), 613 FUNC(xe_rtp_match_first_render_or_compute)), 614 XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS)) 615 }, 616 }; 617 618 static const struct xe_rtp_entry_sr lrc_was[] = { 619 { XE_RTP_NAME("16011163337"), 620 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 621 /* read verification is ignored due to 1608008084. */ 622 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 623 FF_MODE2_GS_TIMER_MASK, 624 FF_MODE2_GS_TIMER_224)) 625 }, 626 { XE_RTP_NAME("1604555607"), 627 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 628 /* read verification is ignored due to 1608008084. */ 629 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 630 FF_MODE2_TDS_TIMER_MASK, 631 FF_MODE2_TDS_TIMER_128)) 632 }, 633 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 634 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 635 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 636 DISABLE_CPS_AWARE_COLOR_PIPE)) 637 }, 638 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 639 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 640 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 641 PREEMPT_GPGPU_LEVEL_MASK, 642 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 643 }, 644 { XE_RTP_NAME("1806527549"), 645 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 646 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 647 }, 648 { XE_RTP_NAME("1606376872"), 649 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 650 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 651 }, 652 { XE_RTP_NAME("14019877138"), 653 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)), 654 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 655 }, 656 { XE_RTP_NAME("14019386621"), 657 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 658 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 659 }, 660 { XE_RTP_NAME("14019988906"), 661 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 662 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 663 }, 664 { XE_RTP_NAME("18033852989"), 665 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 666 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 667 }, 668 { XE_RTP_NAME("15016589081"), 669 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 670 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 671 }, 672 673 /* DG1 */ 674 675 { XE_RTP_NAME("1409044764"), 676 XE_RTP_RULES(PLATFORM(DG1)), 677 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 678 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 679 }, 680 { XE_RTP_NAME("22010493298"), 681 XE_RTP_RULES(PLATFORM(DG1)), 682 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 683 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 684 }, 685 686 /* DG2 */ 687 688 { XE_RTP_NAME("16013271637"), 689 XE_RTP_RULES(PLATFORM(DG2)), 690 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 691 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 692 }, 693 { XE_RTP_NAME("14014947963"), 694 XE_RTP_RULES(PLATFORM(DG2)), 695 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 696 PREEMPTION_VERTEX_COUNT, 697 0x4000)) 698 }, 699 { XE_RTP_NAME("18018764978"), 700 XE_RTP_RULES(PLATFORM(DG2)), 701 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 702 SCOREBOARD_STALL_FLUSH_CONTROL)) 703 }, 704 { XE_RTP_NAME("18019271663"), 705 XE_RTP_RULES(PLATFORM(DG2)), 706 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 707 }, 708 709 /* PVC */ 710 711 { XE_RTP_NAME("16017236439"), 712 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 713 FUNC(xe_rtp_match_even_instance)), 714 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 715 BCS_SWCTRL_DISABLE_256B, 716 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 717 }, 718 719 /* Xe_LPG */ 720 721 { XE_RTP_NAME("18019271663"), 722 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 723 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 724 }, 725 726 /* Xe2_LPG */ 727 728 { XE_RTP_NAME("14021567978"), 729 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 730 ENGINE_CLASS(RENDER)), 731 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 732 }, 733 { XE_RTP_NAME("14020756599"), 734 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 735 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 736 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 737 }, 738 { XE_RTP_NAME("14021490052"), 739 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 740 XE_RTP_ACTIONS(SET(FF_MODE, 741 DIS_MESH_PARTIAL_AUTOSTRIP | 742 DIS_MESH_AUTOSTRIP), 743 SET(VFLSKPD, 744 DIS_PARTIAL_AUTOSTRIP | 745 DIS_AUTOSTRIP)) 746 }, 747 748 /* Xe2_HPG */ 749 750 { XE_RTP_NAME("14020756599"), 751 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 752 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 753 }, 754 { XE_RTP_NAME("14019988906"), 755 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 756 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 757 }, 758 { XE_RTP_NAME("14019877138"), 759 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 760 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 761 }, 762 { XE_RTP_NAME("14021490052"), 763 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 764 XE_RTP_ACTIONS(SET(FF_MODE, 765 DIS_MESH_PARTIAL_AUTOSTRIP | 766 DIS_MESH_AUTOSTRIP), 767 SET(VFLSKPD, 768 DIS_PARTIAL_AUTOSTRIP | 769 DIS_AUTOSTRIP)) 770 }, 771 { XE_RTP_NAME("22021007897"), 772 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 773 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 774 }, 775 776 /* Xe3_LPG */ 777 { XE_RTP_NAME("14021490052"), 778 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 779 ENGINE_CLASS(RENDER)), 780 XE_RTP_ACTIONS(SET(FF_MODE, 781 DIS_MESH_PARTIAL_AUTOSTRIP | 782 DIS_MESH_AUTOSTRIP), 783 SET(VFLSKPD, 784 DIS_PARTIAL_AUTOSTRIP | 785 DIS_AUTOSTRIP)) 786 }, 787 { XE_RTP_NAME("22021007897"), 788 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 789 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 790 }, 791 { XE_RTP_NAME("14024681466"), 792 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 793 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 794 }, 795 { XE_RTP_NAME("15016589081"), 796 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 797 ENGINE_CLASS(RENDER)), 798 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 799 }, 800 { XE_RTP_NAME("14026781792"), 801 XE_RTP_RULES(GRAPHICS_VERSION(3510), ENGINE_CLASS(RENDER)), 802 XE_RTP_ACTIONS(SET(FF_MODE, DIS_TE_PATCH_CTRL)) 803 }, 804 }; 805 806 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 807 #include <generated/xe_wa_oob.c> 808 {} 809 }; 810 811 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 812 813 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 814 #include <generated/xe_device_wa_oob.c> 815 {} 816 }; 817 818 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 819 820 __diag_pop(); 821 822 /** 823 * xe_wa_process_device_oob - process OOB workaround table 824 * @xe: device instance to process workarounds for 825 * 826 * process OOB workaround table for this device, marking in @xe the 827 * workarounds that are active. 828 */ 829 830 void xe_wa_process_device_oob(struct xe_device *xe) 831 { 832 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 833 834 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 835 836 xe->wa_active.oob_initialized = true; 837 xe_rtp_process(&ctx, device_oob_was); 838 } 839 840 /** 841 * xe_wa_process_gt_oob - process GT OOB workaround table 842 * @gt: GT instance to process workarounds for 843 * 844 * Process OOB workaround table for this platform, marking in @gt the 845 * workarounds that are active. 846 */ 847 void xe_wa_process_gt_oob(struct xe_gt *gt) 848 { 849 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 850 851 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 852 ARRAY_SIZE(oob_was)); 853 gt->wa_active.oob_initialized = true; 854 xe_rtp_process(&ctx, oob_was); 855 } 856 857 /** 858 * xe_wa_process_gt - process GT workaround table 859 * @gt: GT instance to process workarounds for 860 * 861 * Process GT workaround table for this platform, saving in @gt all the 862 * workarounds that need to be applied at the GT level. 863 */ 864 void xe_wa_process_gt(struct xe_gt *gt) 865 { 866 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 867 868 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 869 ARRAY_SIZE(gt_was)); 870 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), 871 >->reg_sr, false); 872 } 873 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 874 875 /** 876 * xe_wa_process_engine - process engine workaround table 877 * @hwe: engine instance to process workarounds for 878 * 879 * Process engine workaround table for this platform, saving in @hwe all the 880 * workarounds that need to be applied at the engine level that match this 881 * engine. 882 */ 883 void xe_wa_process_engine(struct xe_hw_engine *hwe) 884 { 885 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 886 887 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 888 ARRAY_SIZE(engine_was)); 889 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), 890 &hwe->reg_sr, false); 891 } 892 893 /** 894 * xe_wa_process_lrc - process context workaround table 895 * @hwe: engine instance to process workarounds for 896 * 897 * Process context workaround table for this platform, saving in @hwe all the 898 * workarounds that need to be applied on context restore. These are workarounds 899 * touching registers that are part of the HW context image. 900 */ 901 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 902 { 903 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 904 905 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 906 ARRAY_SIZE(lrc_was)); 907 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), 908 &hwe->reg_lrc, true); 909 } 910 911 /** 912 * xe_wa_device_init - initialize device with workaround oob bookkeeping 913 * @xe: Xe device instance to initialize 914 * 915 * Returns 0 for success, negative with error code otherwise 916 */ 917 int xe_wa_device_init(struct xe_device *xe) 918 { 919 unsigned long *p; 920 921 p = drmm_kzalloc(&xe->drm, 922 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 923 GFP_KERNEL); 924 925 if (!p) 926 return -ENOMEM; 927 928 xe->wa_active.oob = p; 929 930 return 0; 931 } 932 933 /** 934 * xe_wa_gt_init - initialize gt with workaround bookkeeping 935 * @gt: GT instance to initialize 936 * 937 * Returns 0 for success, negative error code otherwise. 938 */ 939 int xe_wa_gt_init(struct xe_gt *gt) 940 { 941 struct xe_device *xe = gt_to_xe(gt); 942 size_t n_oob, n_lrc, n_engine, n_gt, total; 943 unsigned long *p; 944 945 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 946 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 947 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 948 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 949 total = n_gt + n_engine + n_lrc + n_oob; 950 951 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 952 if (!p) 953 return -ENOMEM; 954 955 gt->wa_active.gt = p; 956 p += n_gt; 957 gt->wa_active.engine = p; 958 p += n_engine; 959 gt->wa_active.lrc = p; 960 p += n_lrc; 961 gt->wa_active.oob = p; 962 963 return 0; 964 } 965 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 966 967 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 968 { 969 size_t idx; 970 971 drm_printf(p, "Device OOB Workarounds\n"); 972 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 973 if (device_oob_was[idx].name) 974 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 975 } 976 977 /** 978 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer. 979 * @gt: the &xe_gt 980 * @p: the &drm_printer 981 * 982 * Return: always 0. 983 */ 984 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p) 985 { 986 size_t idx; 987 988 drm_printf(p, "GT Workarounds\n"); 989 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 990 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 991 992 drm_puts(p, "\n"); 993 drm_printf(p, "Engine Workarounds\n"); 994 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 995 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 996 997 drm_puts(p, "\n"); 998 drm_printf(p, "LRC Workarounds\n"); 999 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 1000 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 1001 1002 drm_puts(p, "\n"); 1003 drm_printf(p, "OOB Workarounds\n"); 1004 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1005 if (oob_was[idx].name) 1006 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1007 return 0; 1008 } 1009 1010 /* 1011 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1012 * adding anything to this function; most workarounds should be implemented 1013 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1014 * which are relatively rare. Since the registers these workarounds target are 1015 * outside the GT, they should only need to be applied once at device 1016 * probe/resume; they will not lose their values on any kind of GT or engine 1017 * reset. 1018 * 1019 * TODO: We may want to move this over to xe_rtp in the future once we have 1020 * enough workarounds to justify the work. 1021 */ 1022 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1023 { 1024 struct xe_mmio *mmio = &tile->mmio; 1025 1026 if (IS_SRIOV_VF(tile->xe)) 1027 return; 1028 1029 if (XE_DEVICE_WA(tile->xe, 22010954014)) 1030 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1031 } 1032