1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "regs/xe_engine_regs.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_regs.h" 19 #include "xe_device_types.h" 20 #include "xe_force_wake.h" 21 #include "xe_gt.h" 22 #include "xe_hw_engine_types.h" 23 #include "xe_mmio.h" 24 #include "xe_platform_types.h" 25 #include "xe_rtp.h" 26 #include "xe_sriov.h" 27 #include "xe_step.h" 28 29 /** 30 * DOC: Hardware workarounds 31 * 32 * Hardware workarounds are register programming documented to be executed in 33 * the driver that fall outside of the normal programming sequences for a 34 * platform. There are some basic categories of workarounds, depending on 35 * how/when they are applied: 36 * 37 * - LRC workarounds: workarounds that touch registers that are 38 * saved/restored to/from the HW context image. The list is emitted (via Load 39 * Register Immediate commands) once when initializing the device and saved in 40 * the default context. That default context is then used on every context 41 * creation to have a "primed golden context", i.e. a context image that 42 * already contains the changes needed to all the registers. See 43 * drivers/gpu/drm/xe/xe_lrc.c for default context handling. 44 * 45 * - Engine workarounds: the list of these WAs is applied whenever the specific 46 * engine is reset. It's also possible that a set of engine classes share a 47 * common power domain and they are reset together. This happens on some 48 * platforms with render and compute engines. In this case (at least) one of 49 * them need to keeep the workaround programming: the approach taken in the 50 * driver is to tie those workarounds to the first compute/render engine that 51 * is registered. When executing with GuC submission, engine resets are 52 * outside of kernel driver control, hence the list of registers involved is 53 * written once, on engine initialization, and then passed to GuC, that 54 * saves/restores their values before/after the reset takes place. See 55 * drivers/gpu/drm/xe/xe_guc_ads.c for reference. 56 * 57 * - GT workarounds: the list of these WAs is applied whenever these registers 58 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 59 * 60 * - Register whitelist: some workarounds need to be implemented in userspace, 61 * but need to touch privileged registers. The whitelist in the kernel 62 * instructs the hardware to allow the access to happen. From the kernel side, 63 * this is just a special case of a MMIO workaround (as we write the list of 64 * these to/be-whitelisted registers to some special HW registers). 65 * 66 * - Workaround batchbuffers: buffers that get executed automatically by the 67 * hardware on every HW context restore. These buffers are created and 68 * programmed in the default context so the hardware always go through those 69 * programming sequences when switching contexts. The support for workaround 70 * batchbuffers is enabled via these hardware mechanisms: 71 * 72 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer 73 * and an offset are provided in the default context, pointing the hardware 74 * to jump to that location when that offset is reached in the context 75 * restore. When a context is being restored, this is executed after the 76 * ring context, in the middle (or beginning) of the engine context image. 77 * 78 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A 79 * batchbuffer is provided in the default context, pointing the hardware to 80 * a buffer to continue executing after the engine registers are restored 81 * in a context restore sequence. 82 * 83 * Below is the timeline for a context restore sequence: 84 * 85 * .. code:: 86 * 87 * INDIRECT_CTX_OFFSET 88 * |----------->| 89 * .------------.------------.-------------.------------.--------------.-----------. 90 * |Ring | Engine | Mid-context | Engine | Post-context | Ring | 91 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | 92 * `------------'------------'-------------'------------'--------------'-----------' 93 * 94 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 95 * a central place. Those are peppered around the rest of the code, as needed. 96 * There's a central place to control which workarounds are enabled: 97 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and 98 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. 99 * These files only record which workarounds are enabled: during early device 100 * initialization those rules are evaluated and recorded by the driver. Then 101 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to 102 * implement them. 103 * 104 * .. [1] Technically, some registers are powercontext saved & restored, so they 105 * survive a suspend/resume. In practice, writing them again is not too 106 * costly and simplifies things, so it's the approach taken in the driver. 107 * 108 * .. note:: 109 * Hardware workarounds in xe work the same way as in i915, with the 110 * difference of how they are maintained in the code. In xe it uses the 111 * xe_rtp infrastructure so the workarounds can be kept in tables, following 112 * a more declarative approach rather than procedural. 113 */ 114 115 #undef XE_REG_MCR 116 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 117 118 __diag_push(); 119 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 120 121 static const struct xe_rtp_entry_sr gt_was[] = { 122 { XE_RTP_NAME("14011060649"), 123 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 124 ENGINE_CLASS(VIDEO_DECODE), 125 FUNC(xe_rtp_match_even_instance)), 126 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 127 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 128 }, 129 { XE_RTP_NAME("14011059788"), 130 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 131 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 132 }, 133 { XE_RTP_NAME("14015795083"), 134 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 135 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 136 }, 137 138 /* DG1 */ 139 140 { XE_RTP_NAME("1409420604"), 141 XE_RTP_RULES(PLATFORM(DG1)), 142 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 143 }, 144 { XE_RTP_NAME("1408615072"), 145 XE_RTP_RULES(PLATFORM(DG1)), 146 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 147 }, 148 149 /* DG2 */ 150 151 { XE_RTP_NAME("22010523718"), 152 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 153 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 154 }, 155 { XE_RTP_NAME("14011006942"), 156 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 157 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 158 }, 159 { XE_RTP_NAME("14014830051"), 160 XE_RTP_RULES(PLATFORM(DG2)), 161 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 162 }, 163 { XE_RTP_NAME("18018781329"), 164 XE_RTP_RULES(PLATFORM(DG2)), 165 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 166 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 167 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 168 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 169 }, 170 { XE_RTP_NAME("1509235366"), 171 XE_RTP_RULES(PLATFORM(DG2)), 172 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 173 INVALIDATION_BROADCAST_MODE_DIS | 174 GLOBAL_INVALIDATION_MODE)) 175 }, 176 177 /* PVC */ 178 179 { XE_RTP_NAME("18018781329"), 180 XE_RTP_RULES(PLATFORM(PVC)), 181 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 182 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 183 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 184 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 185 }, 186 { XE_RTP_NAME("16016694945"), 187 XE_RTP_RULES(PLATFORM(PVC)), 188 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 189 }, 190 191 /* Xe_LPG */ 192 193 { XE_RTP_NAME("14015795083"), 194 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 195 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 196 }, 197 { XE_RTP_NAME("14018575942"), 198 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 199 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 200 }, 201 { XE_RTP_NAME("22016670082"), 202 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 203 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 204 }, 205 206 /* Xe_LPM+ */ 207 208 { XE_RTP_NAME("16021867713"), 209 XE_RTP_RULES(MEDIA_VERSION(1300), 210 ENGINE_CLASS(VIDEO_DECODE)), 211 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 212 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 213 }, 214 { XE_RTP_NAME("22016670082"), 215 XE_RTP_RULES(MEDIA_VERSION(1300)), 216 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 217 }, 218 219 /* Xe2_LPG */ 220 221 { XE_RTP_NAME("16020975621"), 222 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 223 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 224 }, 225 { XE_RTP_NAME("14018157293"), 226 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 227 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 228 SET(XEHPC_L3CLOS_MASK(1), ~0), 229 SET(XEHPC_L3CLOS_MASK(2), ~0), 230 SET(XEHPC_L3CLOS_MASK(3), ~0)) 231 }, 232 233 /* Xe2_LPM */ 234 235 { XE_RTP_NAME("14017421178"), 236 XE_RTP_RULES(MEDIA_VERSION(2000), 237 ENGINE_CLASS(VIDEO_DECODE)), 238 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 239 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 240 }, 241 { XE_RTP_NAME("16021867713"), 242 XE_RTP_RULES(MEDIA_VERSION(2000), 243 ENGINE_CLASS(VIDEO_DECODE)), 244 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 245 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 246 }, 247 { XE_RTP_NAME("14019449301"), 248 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 249 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 250 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 251 }, 252 253 /* Xe2_HPG */ 254 255 { XE_RTP_NAME("16025250150"), 256 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 257 XE_RTP_ACTIONS(SET(LSN_VC_REG2, 258 LSN_LNI_WGT(1) | 259 LSN_LNE_WGT(1) | 260 LSN_DIM_X_WGT(1) | 261 LSN_DIM_Y_WGT(1) | 262 LSN_DIM_Z_WGT(1))) 263 }, 264 265 /* Xe2_HPM */ 266 267 { XE_RTP_NAME("16021867713"), 268 XE_RTP_RULES(MEDIA_VERSION(1301), 269 ENGINE_CLASS(VIDEO_DECODE)), 270 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 271 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 272 }, 273 { XE_RTP_NAME("14019449301"), 274 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 275 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 276 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 277 }, 278 279 /* Xe3_LPG */ 280 281 { XE_RTP_NAME("14021871409"), 282 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 283 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 284 }, 285 286 /* Xe3_LPM */ 287 288 { XE_RTP_NAME("16021867713"), 289 XE_RTP_RULES(MEDIA_VERSION(3000), 290 ENGINE_CLASS(VIDEO_DECODE)), 291 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 292 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 293 }, 294 { XE_RTP_NAME("16021865536"), 295 XE_RTP_RULES(MEDIA_VERSION(3000), 296 ENGINE_CLASS(VIDEO_DECODE)), 297 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 298 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 299 }, 300 { XE_RTP_NAME("16021865536"), 301 XE_RTP_RULES(MEDIA_VERSION(3002), 302 ENGINE_CLASS(VIDEO_DECODE)), 303 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 304 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 305 }, 306 { XE_RTP_NAME("16021867713"), 307 XE_RTP_RULES(MEDIA_VERSION(3002), 308 ENGINE_CLASS(VIDEO_DECODE)), 309 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 310 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 311 }, 312 { XE_RTP_NAME("14021486841"), 313 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 314 ENGINE_CLASS(VIDEO_DECODE)), 315 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 316 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 317 }, 318 }; 319 320 static const struct xe_rtp_entry_sr engine_was[] = { 321 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 322 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 323 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 324 FF_TESSELATION_DOP_GATE_DISABLE)) 325 }, 326 { XE_RTP_NAME("1409804808"), 327 XE_RTP_RULES(GRAPHICS_VERSION(1200), 328 ENGINE_CLASS(RENDER), 329 IS_INTEGRATED), 330 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 331 }, 332 { XE_RTP_NAME("14010229206, 1409085225"), 333 XE_RTP_RULES(GRAPHICS_VERSION(1200), 334 ENGINE_CLASS(RENDER), 335 IS_INTEGRATED), 336 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 337 }, 338 { XE_RTP_NAME("1606931601"), 339 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 340 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 341 }, 342 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 343 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 344 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 345 FF_DOP_CLOCK_GATE_DISABLE)) 346 }, 347 { XE_RTP_NAME("1406941453"), 348 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 349 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 350 }, 351 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 352 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 353 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 354 FFSC_PERCTX_PREEMPT_CTRL)) 355 }, 356 357 /* TGL */ 358 359 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 360 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 361 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 362 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 363 RC_SEMA_IDLE_MSG_DISABLE)) 364 }, 365 366 /* RKL */ 367 368 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 369 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 370 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 371 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 372 RC_SEMA_IDLE_MSG_DISABLE)) 373 }, 374 375 /* ADL-P */ 376 377 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 378 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 379 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 380 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 381 RC_SEMA_IDLE_MSG_DISABLE)) 382 }, 383 384 /* DG2 */ 385 386 { XE_RTP_NAME("22013037850"), 387 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 388 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 389 DISABLE_128B_EVICTION_COMMAND_UDW)) 390 }, 391 { XE_RTP_NAME("22014226127"), 392 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 393 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 394 }, 395 { XE_RTP_NAME("18017747507"), 396 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 397 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 398 POLYGON_TRIFAN_LINELOOP_DISABLE)) 399 }, 400 { XE_RTP_NAME("22012826095, 22013059131"), 401 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 402 FUNC(xe_rtp_match_first_render_or_compute)), 403 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 404 MAXREQS_PER_BANK, 405 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 406 }, 407 { XE_RTP_NAME("22013059131"), 408 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 409 FUNC(xe_rtp_match_first_render_or_compute)), 410 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 411 }, 412 { XE_RTP_NAME("14015227452"), 413 XE_RTP_RULES(PLATFORM(DG2), 414 FUNC(xe_rtp_match_first_render_or_compute)), 415 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 416 }, 417 { XE_RTP_NAME("18028616096"), 418 XE_RTP_RULES(PLATFORM(DG2), 419 FUNC(xe_rtp_match_first_render_or_compute)), 420 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 421 }, 422 { XE_RTP_NAME("22015475538"), 423 XE_RTP_RULES(PLATFORM(DG2), 424 FUNC(xe_rtp_match_first_render_or_compute)), 425 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 426 }, 427 { XE_RTP_NAME("22012654132"), 428 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 429 FUNC(xe_rtp_match_first_render_or_compute)), 430 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 431 /* 432 * Register can't be read back for verification on 433 * DG2 due to Wa_14012342262 434 */ 435 .read_mask = 0)) 436 }, 437 { XE_RTP_NAME("1509727124"), 438 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 439 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 440 }, 441 { XE_RTP_NAME("22012856258"), 442 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 443 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 444 }, 445 { XE_RTP_NAME("22010960976, 14013347512"), 446 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 447 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 448 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 449 }, 450 { XE_RTP_NAME("14015150844"), 451 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 452 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 453 XE_RTP_NOCHECK)) 454 }, 455 456 /* PVC */ 457 458 { XE_RTP_NAME("22014226127"), 459 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 460 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 461 }, 462 { XE_RTP_NAME("14015227452"), 463 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 464 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 465 }, 466 { XE_RTP_NAME("18020744125"), 467 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 468 ENGINE_CLASS(COMPUTE)), 469 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 470 }, 471 { XE_RTP_NAME("14014999345"), 472 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 473 GRAPHICS_STEP(B0, C0)), 474 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 475 }, 476 477 /* Xe_LPG */ 478 479 { XE_RTP_NAME("14017856879"), 480 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 481 FUNC(xe_rtp_match_first_render_or_compute)), 482 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 483 }, 484 { XE_RTP_NAME("14015150844"), 485 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 486 FUNC(xe_rtp_match_first_render_or_compute)), 487 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 488 XE_RTP_NOCHECK)) 489 }, 490 { XE_RTP_NAME("14020495402"), 491 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 492 FUNC(xe_rtp_match_first_render_or_compute)), 493 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 494 }, 495 496 /* Xe2_LPG */ 497 498 { XE_RTP_NAME("18032247524"), 499 XE_RTP_RULES(GRAPHICS_VERSION(2004), 500 FUNC(xe_rtp_match_first_render_or_compute)), 501 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 502 }, 503 { XE_RTP_NAME("16018712365"), 504 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 505 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 506 }, 507 { XE_RTP_NAME("14018957109"), 508 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 509 FUNC(xe_rtp_match_first_render_or_compute)), 510 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 511 }, 512 { XE_RTP_NAME("14020338487"), 513 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 514 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 515 }, 516 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 517 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 518 FUNC(xe_rtp_match_first_render_or_compute)), 519 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 520 }, 521 { XE_RTP_NAME("14019322943"), 522 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 523 FUNC(xe_rtp_match_first_render_or_compute)), 524 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 525 }, 526 { XE_RTP_NAME("14018471104"), 527 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 528 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 529 }, 530 /* 531 * These two workarounds are the same, just applying to different 532 * engines. Although Wa_18032095049 (for the RCS) isn't required on 533 * all steppings, disabling these reports has no impact for our 534 * driver or the GuC, so we go ahead and treat it the same as 535 * Wa_16021639441 which does apply to all steppings. 536 */ 537 { XE_RTP_NAME("18032095049, 16021639441"), 538 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 539 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 540 GHWSP_CSB_REPORT_DIS | 541 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 542 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 543 }, 544 { XE_RTP_NAME("16018610683"), 545 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 546 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 547 }, 548 { XE_RTP_NAME("14021402888"), 549 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 550 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 551 }, 552 { XE_RTP_NAME("13012615864"), 553 XE_RTP_RULES(GRAPHICS_VERSION(2004), 554 FUNC(xe_rtp_match_first_render_or_compute)), 555 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 556 }, 557 558 /* Xe2_HPG */ 559 560 { XE_RTP_NAME("16018712365"), 561 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 562 FUNC(xe_rtp_match_first_render_or_compute)), 563 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 564 }, 565 { XE_RTP_NAME("16018737384"), 566 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 567 FUNC(xe_rtp_match_first_render_or_compute)), 568 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 569 }, 570 { XE_RTP_NAME("14019988906"), 571 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 572 FUNC(xe_rtp_match_first_render_or_compute)), 573 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 574 }, 575 { XE_RTP_NAME("14019877138"), 576 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 577 FUNC(xe_rtp_match_first_render_or_compute)), 578 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 579 }, 580 { XE_RTP_NAME("14020338487"), 581 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 582 FUNC(xe_rtp_match_first_render_or_compute)), 583 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 584 }, 585 { XE_RTP_NAME("18032247524"), 586 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 587 FUNC(xe_rtp_match_first_render_or_compute)), 588 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 589 }, 590 { XE_RTP_NAME("14018471104"), 591 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 592 FUNC(xe_rtp_match_first_render_or_compute)), 593 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 594 }, 595 /* 596 * Although this workaround isn't required for the RCS, disabling these 597 * reports has no impact for our driver or the GuC, so we go ahead and 598 * apply this to all engines for simplicity. 599 */ 600 { XE_RTP_NAME("16021639441"), 601 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 602 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 603 GHWSP_CSB_REPORT_DIS | 604 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 605 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 606 }, 607 { XE_RTP_NAME("14019811474"), 608 XE_RTP_RULES(GRAPHICS_VERSION(2001), 609 FUNC(xe_rtp_match_first_render_or_compute)), 610 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 611 }, 612 { XE_RTP_NAME("14021402888"), 613 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 614 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 615 }, 616 { XE_RTP_NAME("14021821874, 14022954250"), 617 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 618 FUNC(xe_rtp_match_first_render_or_compute)), 619 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 620 }, 621 { XE_RTP_NAME("13012615864"), 622 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 623 FUNC(xe_rtp_match_first_render_or_compute)), 624 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 625 }, 626 { XE_RTP_NAME("18041344222"), 627 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 628 FUNC(xe_rtp_match_first_render_or_compute), 629 FUNC(xe_rtp_match_not_sriov_vf), 630 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 631 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 632 }, 633 634 /* Xe2_LPM */ 635 636 { XE_RTP_NAME("16021639441"), 637 XE_RTP_RULES(MEDIA_VERSION(2000)), 638 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 639 GHWSP_CSB_REPORT_DIS | 640 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 641 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 642 }, 643 644 /* Xe2_HPM */ 645 646 { XE_RTP_NAME("16021639441"), 647 XE_RTP_RULES(MEDIA_VERSION(1301)), 648 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 649 GHWSP_CSB_REPORT_DIS | 650 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 651 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 652 }, 653 654 /* Xe3_LPG */ 655 656 { XE_RTP_NAME("14021402888"), 657 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 658 FUNC(xe_rtp_match_first_render_or_compute)), 659 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 660 }, 661 { XE_RTP_NAME("18034896535"), 662 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 663 FUNC(xe_rtp_match_first_render_or_compute)), 664 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 665 }, 666 { XE_RTP_NAME("16024792527"), 667 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 668 FUNC(xe_rtp_match_first_render_or_compute)), 669 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 670 SMP_FORCE_128B_OVERFETCH)) 671 }, 672 { XE_RTP_NAME("14023061436"), 673 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 674 FUNC(xe_rtp_match_first_render_or_compute), OR, 675 GRAPHICS_VERSION_RANGE(3003, 3005), 676 FUNC(xe_rtp_match_first_render_or_compute)), 677 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 678 }, 679 { XE_RTP_NAME("13012615864"), 680 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR, 681 GRAPHICS_VERSION_RANGE(3003, 3005), 682 FUNC(xe_rtp_match_first_render_or_compute)), 683 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 684 }, 685 { XE_RTP_NAME("16023105232"), 686 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 687 GRAPHICS_VERSION_RANGE(2001, 3001)), 688 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 689 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 690 }, 691 { XE_RTP_NAME("14021402888"), 692 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)), 693 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 694 }, 695 { XE_RTP_NAME("18041344222"), 696 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 697 FUNC(xe_rtp_match_first_render_or_compute), 698 FUNC(xe_rtp_match_not_sriov_vf), 699 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 700 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 701 }, 702 }; 703 704 static const struct xe_rtp_entry_sr lrc_was[] = { 705 { XE_RTP_NAME("16011163337"), 706 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 707 /* read verification is ignored due to 1608008084. */ 708 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 709 FF_MODE2_GS_TIMER_MASK, 710 FF_MODE2_GS_TIMER_224)) 711 }, 712 { XE_RTP_NAME("1604555607"), 713 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 714 /* read verification is ignored due to 1608008084. */ 715 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 716 FF_MODE2_TDS_TIMER_MASK, 717 FF_MODE2_TDS_TIMER_128)) 718 }, 719 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 720 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 721 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 722 DISABLE_CPS_AWARE_COLOR_PIPE)) 723 }, 724 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 725 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 726 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 727 PREEMPT_GPGPU_LEVEL_MASK, 728 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 729 }, 730 { XE_RTP_NAME("1806527549"), 731 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 732 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 733 }, 734 { XE_RTP_NAME("1606376872"), 735 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 736 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 737 }, 738 739 /* DG1 */ 740 741 { XE_RTP_NAME("1409044764"), 742 XE_RTP_RULES(PLATFORM(DG1)), 743 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 744 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 745 }, 746 { XE_RTP_NAME("22010493298"), 747 XE_RTP_RULES(PLATFORM(DG1)), 748 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 749 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 750 }, 751 752 /* DG2 */ 753 754 { XE_RTP_NAME("16013271637"), 755 XE_RTP_RULES(PLATFORM(DG2)), 756 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 757 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 758 }, 759 { XE_RTP_NAME("14014947963"), 760 XE_RTP_RULES(PLATFORM(DG2)), 761 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 762 PREEMPTION_VERTEX_COUNT, 763 0x4000)) 764 }, 765 { XE_RTP_NAME("18018764978"), 766 XE_RTP_RULES(PLATFORM(DG2)), 767 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 768 SCOREBOARD_STALL_FLUSH_CONTROL)) 769 }, 770 { XE_RTP_NAME("18019271663"), 771 XE_RTP_RULES(PLATFORM(DG2)), 772 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 773 }, 774 { XE_RTP_NAME("14019877138"), 775 XE_RTP_RULES(PLATFORM(DG2)), 776 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 777 }, 778 779 /* PVC */ 780 781 { XE_RTP_NAME("16017236439"), 782 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 783 FUNC(xe_rtp_match_even_instance)), 784 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 785 BCS_SWCTRL_DISABLE_256B, 786 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 787 }, 788 789 /* Xe_LPG */ 790 791 { XE_RTP_NAME("18019271663"), 792 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 793 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 794 }, 795 { XE_RTP_NAME("14019877138"), 796 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 797 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 798 }, 799 800 /* Xe2_LPG */ 801 802 { XE_RTP_NAME("16020518922"), 803 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 804 ENGINE_CLASS(RENDER)), 805 XE_RTP_ACTIONS(SET(FF_MODE, 806 DIS_TE_AUTOSTRIP | 807 DIS_MESH_PARTIAL_AUTOSTRIP | 808 DIS_MESH_AUTOSTRIP), 809 SET(VFLSKPD, 810 DIS_PARTIAL_AUTOSTRIP | 811 DIS_AUTOSTRIP)) 812 }, 813 { XE_RTP_NAME("14019386621"), 814 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 815 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 816 }, 817 { XE_RTP_NAME("14019877138"), 818 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 819 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 820 }, 821 { XE_RTP_NAME("14020013138"), 822 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 823 ENGINE_CLASS(RENDER)), 824 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 825 }, 826 { XE_RTP_NAME("14019988906"), 827 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 828 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 829 }, 830 { XE_RTP_NAME("16020183090"), 831 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 832 ENGINE_CLASS(RENDER)), 833 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 834 }, 835 { XE_RTP_NAME("18033852989"), 836 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 837 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 838 }, 839 { XE_RTP_NAME("14021567978"), 840 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 841 ENGINE_CLASS(RENDER)), 842 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 843 }, 844 { XE_RTP_NAME("14020756599"), 845 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 846 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 847 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 848 }, 849 { XE_RTP_NAME("14021490052"), 850 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 851 XE_RTP_ACTIONS(SET(FF_MODE, 852 DIS_MESH_PARTIAL_AUTOSTRIP | 853 DIS_MESH_AUTOSTRIP), 854 SET(VFLSKPD, 855 DIS_PARTIAL_AUTOSTRIP | 856 DIS_AUTOSTRIP)) 857 }, 858 { XE_RTP_NAME("15016589081"), 859 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 860 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 861 }, 862 863 /* Xe2_HPG */ 864 { XE_RTP_NAME("15010599737"), 865 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 866 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 867 }, 868 { XE_RTP_NAME("14019386621"), 869 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 870 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 871 }, 872 { XE_RTP_NAME("14020756599"), 873 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 874 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 875 }, 876 { XE_RTP_NAME("14021490052"), 877 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 878 XE_RTP_ACTIONS(SET(FF_MODE, 879 DIS_MESH_PARTIAL_AUTOSTRIP | 880 DIS_MESH_AUTOSTRIP), 881 SET(VFLSKPD, 882 DIS_PARTIAL_AUTOSTRIP | 883 DIS_AUTOSTRIP)) 884 }, 885 { XE_RTP_NAME("15016589081"), 886 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 887 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 888 }, 889 { XE_RTP_NAME("22021007897"), 890 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 891 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 892 }, 893 { XE_RTP_NAME("18033852989"), 894 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 895 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 896 }, 897 898 /* Xe3_LPG */ 899 { XE_RTP_NAME("14021490052"), 900 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 901 ENGINE_CLASS(RENDER)), 902 XE_RTP_ACTIONS(SET(FF_MODE, 903 DIS_MESH_PARTIAL_AUTOSTRIP | 904 DIS_MESH_AUTOSTRIP), 905 SET(VFLSKPD, 906 DIS_PARTIAL_AUTOSTRIP | 907 DIS_AUTOSTRIP)) 908 }, 909 { XE_RTP_NAME("22021007897"), 910 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 911 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 912 }, 913 { XE_RTP_NAME("14024681466"), 914 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 915 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 916 }, 917 { XE_RTP_NAME("15016589081"), 918 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 919 ENGINE_CLASS(RENDER)), 920 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 921 }, 922 }; 923 924 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 925 #include <generated/xe_wa_oob.c> 926 {} 927 }; 928 929 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 930 931 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 932 #include <generated/xe_device_wa_oob.c> 933 {} 934 }; 935 936 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 937 938 __diag_pop(); 939 940 /** 941 * xe_wa_process_device_oob - process OOB workaround table 942 * @xe: device instance to process workarounds for 943 * 944 * process OOB workaround table for this device, marking in @xe the 945 * workarounds that are active. 946 */ 947 948 void xe_wa_process_device_oob(struct xe_device *xe) 949 { 950 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 951 952 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 953 954 xe->wa_active.oob_initialized = true; 955 xe_rtp_process(&ctx, device_oob_was); 956 } 957 958 /** 959 * xe_wa_process_gt_oob - process GT OOB workaround table 960 * @gt: GT instance to process workarounds for 961 * 962 * Process OOB workaround table for this platform, marking in @gt the 963 * workarounds that are active. 964 */ 965 void xe_wa_process_gt_oob(struct xe_gt *gt) 966 { 967 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 968 969 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 970 ARRAY_SIZE(oob_was)); 971 gt->wa_active.oob_initialized = true; 972 xe_rtp_process(&ctx, oob_was); 973 } 974 975 /** 976 * xe_wa_process_gt - process GT workaround table 977 * @gt: GT instance to process workarounds for 978 * 979 * Process GT workaround table for this platform, saving in @gt all the 980 * workarounds that need to be applied at the GT level. 981 */ 982 void xe_wa_process_gt(struct xe_gt *gt) 983 { 984 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 985 986 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 987 ARRAY_SIZE(gt_was)); 988 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 989 } 990 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 991 992 /** 993 * xe_wa_process_engine - process engine workaround table 994 * @hwe: engine instance to process workarounds for 995 * 996 * Process engine workaround table for this platform, saving in @hwe all the 997 * workarounds that need to be applied at the engine level that match this 998 * engine. 999 */ 1000 void xe_wa_process_engine(struct xe_hw_engine *hwe) 1001 { 1002 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 1003 1004 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 1005 ARRAY_SIZE(engine_was)); 1006 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 1007 } 1008 1009 /** 1010 * xe_wa_process_lrc - process context workaround table 1011 * @hwe: engine instance to process workarounds for 1012 * 1013 * Process context workaround table for this platform, saving in @hwe all the 1014 * workarounds that need to be applied on context restore. These are workarounds 1015 * touching registers that are part of the HW context image. 1016 */ 1017 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 1018 { 1019 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 1020 1021 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 1022 ARRAY_SIZE(lrc_was)); 1023 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 1024 } 1025 1026 /** 1027 * xe_wa_device_init - initialize device with workaround oob bookkeeping 1028 * @xe: Xe device instance to initialize 1029 * 1030 * Returns 0 for success, negative with error code otherwise 1031 */ 1032 int xe_wa_device_init(struct xe_device *xe) 1033 { 1034 unsigned long *p; 1035 1036 p = drmm_kzalloc(&xe->drm, 1037 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 1038 GFP_KERNEL); 1039 1040 if (!p) 1041 return -ENOMEM; 1042 1043 xe->wa_active.oob = p; 1044 1045 return 0; 1046 } 1047 1048 /** 1049 * xe_wa_gt_init - initialize gt with workaround bookkeeping 1050 * @gt: GT instance to initialize 1051 * 1052 * Returns 0 for success, negative error code otherwise. 1053 */ 1054 int xe_wa_gt_init(struct xe_gt *gt) 1055 { 1056 struct xe_device *xe = gt_to_xe(gt); 1057 size_t n_oob, n_lrc, n_engine, n_gt, total; 1058 unsigned long *p; 1059 1060 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 1061 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 1062 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 1063 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 1064 total = n_gt + n_engine + n_lrc + n_oob; 1065 1066 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 1067 if (!p) 1068 return -ENOMEM; 1069 1070 gt->wa_active.gt = p; 1071 p += n_gt; 1072 gt->wa_active.engine = p; 1073 p += n_engine; 1074 gt->wa_active.lrc = p; 1075 p += n_lrc; 1076 gt->wa_active.oob = p; 1077 1078 return 0; 1079 } 1080 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 1081 1082 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 1083 { 1084 size_t idx; 1085 1086 drm_printf(p, "Device OOB Workarounds\n"); 1087 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 1088 if (device_oob_was[idx].name) 1089 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 1090 } 1091 1092 /** 1093 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer. 1094 * @gt: the &xe_gt 1095 * @p: the &drm_printer 1096 * 1097 * Return: always 0. 1098 */ 1099 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p) 1100 { 1101 size_t idx; 1102 1103 drm_printf(p, "GT Workarounds\n"); 1104 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 1105 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 1106 1107 drm_puts(p, "\n"); 1108 drm_printf(p, "Engine Workarounds\n"); 1109 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 1110 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 1111 1112 drm_puts(p, "\n"); 1113 drm_printf(p, "LRC Workarounds\n"); 1114 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 1115 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 1116 1117 drm_puts(p, "\n"); 1118 drm_printf(p, "OOB Workarounds\n"); 1119 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1120 if (oob_was[idx].name) 1121 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1122 return 0; 1123 } 1124 1125 /* 1126 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1127 * adding anything to this function; most workarounds should be implemented 1128 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1129 * which are relatively rare. Since the registers these workarounds target are 1130 * outside the GT, they should only need to be applied once at device 1131 * probe/resume; they will not lose their values on any kind of GT or engine 1132 * reset. 1133 * 1134 * TODO: We may want to move this over to xe_rtp in the future once we have 1135 * enough workarounds to justify the work. 1136 */ 1137 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1138 { 1139 struct xe_mmio *mmio = &tile->mmio; 1140 1141 if (IS_SRIOV_VF(tile->xe)) 1142 return; 1143 1144 if (XE_DEVICE_WA(tile->xe, 22010954014)) 1145 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1146 } 1147